Commit f9a19cab authored by Tristan Gingold's avatar Tristan Gingold

Fix association order (and remove one extra useless generic).

parent f210991d
......@@ -408,8 +408,7 @@ begin
generic map (
g_CLOCK_PERIOD => g_CLOCK_PERIOD,
g_WB_DATA_WIDTH => g_WB_DATA_WIDTH,
g_WB_ADDR_WIDTH => g_WB_ADDR_WIDTH,
g_DECODE_AM => g_DECODE_AM
g_WB_ADDR_WIDTH => g_WB_ADDR_WIDTH
)
port map (
clk_i => clk_i,
......@@ -435,8 +434,8 @@ begin
VME_DATA_DIR_o => VME_DATA_DIR_o,
VME_DATA_OE_N_o => VME_DATA_OE_N_o,
VME_AM_i => VME_AM_i,
VME_IACK_n_i => s_VME_IACK_n,
VME_IACKIN_n_i => s_VME_IACKIN_n,
VME_IACK_n_i => s_VME_IACK_n,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
-- WB signals
......
......@@ -71,8 +71,7 @@ entity VME_bus is
generic (
g_CLOCK_PERIOD : integer;
g_WB_DATA_WIDTH : integer;
g_WB_ADDR_WIDTH : integer;
g_DECODE_AM : boolean
g_WB_ADDR_WIDTH : integer
);
port (
clk_i : in std_logic;
......
......@@ -128,6 +128,7 @@ package vme64x_pack is
g_CLOCK_PERIOD : integer := c_CLOCK_PERIOD;
g_WB_DATA_WIDTH : integer := c_DATA_WIDTH;
g_WB_ADDR_WIDTH : integer := c_ADDR_WIDTH;
g_DECODE_AM : boolean := true;
g_USER_CSR_EXT : boolean := false;
g_MANUFACTURER_ID : std_logic_vector(23 downto 0) := c_CERN_ID;
g_BOARD_ID : std_logic_vector(31 downto 0) := c_SVEC_ID;
......
......@@ -214,7 +214,6 @@ begin -- wrapper
VME_BERR_o => VME_BERR_o,
VME_DTACK_n_o => VME_DTACK_n_o,
VME_RETRY_n_o => VME_RETRY_n_o,
VME_RETRY_OE_o => VME_RETRY_OE_o,
VME_LWORD_n_i => VME_LWORD_n_b_i,
VME_LWORD_n_o => VME_LWORD_n_b_o,
VME_ADDR_i => VME_ADDR_b_i,
......@@ -230,6 +229,7 @@ begin -- wrapper
VME_DATA_OE_N_o => VME_DATA_OE_N_o,
VME_ADDR_DIR_o => VME_ADDR_DIR_o,
VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
VME_RETRY_OE_o => VME_RETRY_OE_o,
DAT_i => dat_in,
DAT_o => dat_out,
......@@ -242,6 +242,8 @@ begin -- wrapper
WE_o => master_o.we,
STALL_i => master_i.stall,
irq_level_i => irq_level_i,
irq_vector_i => irq_vector_i,
user_csr_addr_o => user_csr_addr_o,
user_csr_data_i => user_csr_data_i,
user_csr_data_o => user_csr_data_o,
......@@ -249,10 +251,8 @@ begin -- wrapper
user_cr_addr_o => user_cr_addr_o,
user_cr_data_i => user_cr_data_i,
irq_i => irq_i,
irq_ack_o => irq_ack_o,
irq_vector_i => irq_vector_i,
irq_level_i => irq_level_i
irq_i => irq_i
);
master_o.dat <= dat_out(31 downto 0);
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment