Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
V
VME64x core
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
VME64x core
Commits
ef710744
Commit
ef710744
authored
Jan 24, 2020
by
Tristan Gingold
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
vme_bus: add asynchronous control of dtack.
parent
a9f18940
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
27 additions
and
1 deletion
+27
-1
vme_bus.vhd
hdl/rtl/vme_bus.vhd
+27
-1
No files found.
hdl/rtl/vme_bus.vhd
View file @
ef710744
...
@@ -127,6 +127,10 @@ architecture rtl of vme_bus is
...
@@ -127,6 +127,10 @@ architecture rtl of vme_bus is
signal
vme_odff_dtack_n
:
std_logic
;
signal
vme_odff_dtack_n
:
std_logic
;
signal
vme_odff_dtack_oe
:
std_logic
;
signal
vme_odff_dtack_oe
:
std_logic
;
-- If set, dtack is controled directly from ds.
-- Otherwise, it is controled by vme_odff_dtack_n.
signal
vme_dtack_async_ctrl
:
std_logic
;
-- Register containing the address. Initialized from VME, adjusted
-- Register containing the address. Initialized from VME, adjusted
-- by address decoder, and incremented during DMA.
-- by address decoder, and incremented during DMA.
signal
addr_reg
:
std_logic_vector
(
31
downto
0
);
signal
addr_reg
:
std_logic_vector
(
31
downto
0
);
...
@@ -304,6 +308,7 @@ begin
...
@@ -304,6 +308,7 @@ begin
-- VME
-- VME
vme_odff_dtack_oe
<=
'0'
;
vme_odff_dtack_oe
<=
'0'
;
vme_odff_dtack_n
<=
'1'
;
vme_odff_dtack_n
<=
'1'
;
vme_dtack_async_ctrl
<=
'0'
;
vme_odff_data_dir
<=
'0'
;
vme_odff_data_dir
<=
'0'
;
vme_odff_addr_dir
<=
'0'
;
vme_odff_addr_dir
<=
'0'
;
vme_odff_lword_n
<=
'0'
;
vme_odff_lword_n
<=
'0'
;
...
@@ -331,6 +336,7 @@ begin
...
@@ -331,6 +336,7 @@ begin
decode_start_o
<=
'0'
;
decode_start_o
<=
'0'
;
vme_odff_dtack_oe
<=
'0'
;
vme_odff_dtack_oe
<=
'0'
;
vme_odff_dtack_n
<=
'1'
;
vme_odff_dtack_n
<=
'1'
;
vme_dtack_async_ctrl
<=
'0'
;
vme_berr_n_o
<=
'1'
;
vme_berr_n_o
<=
'1'
;
vme_iackout_n_o
<=
'1'
;
vme_iackout_n_o
<=
'1'
;
irq_ack_o
<=
'0'
;
irq_ack_o
<=
'0'
;
...
@@ -446,6 +452,8 @@ begin
...
@@ -446,6 +452,8 @@ begin
vme_odff_addr_dir
<=
'1'
;
vme_odff_addr_dir
<=
'1'
;
vme_odff_data_dir
<=
'1'
;
vme_odff_data_dir
<=
'1'
;
vme_dtack_async_ctrl
<=
'1'
;
vme_odff_addr
<=
data_reg
(
63
downto
33
);
vme_odff_addr
<=
data_reg
(
63
downto
33
);
vme_odff_lword_n
<=
data_reg
(
32
);
vme_odff_lword_n
<=
data_reg
(
32
);
vme_odff_data
<=
data_reg
(
31
downto
0
);
vme_odff_data
<=
data_reg
(
31
downto
0
);
...
@@ -479,6 +487,7 @@ begin
...
@@ -479,6 +487,7 @@ begin
-- vme bus for at least one cycle).
-- vme bus for at least one cycle).
vme_odff_dtack_oe
<=
'1'
;
vme_odff_dtack_oe
<=
'1'
;
vme_odff_dtack_n
<=
s_err
;
vme_odff_dtack_n
<=
s_err
;
vme_dtack_async_ctrl
<=
'0'
;
s_mainFSMstate
<=
DTACK_LOW
;
s_mainFSMstate
<=
DTACK_LOW
;
else
else
...
@@ -595,6 +604,13 @@ begin
...
@@ -595,6 +604,13 @@ begin
vme_berr_n_o
<=
'0'
;
vme_berr_n_o
<=
'0'
;
else
else
vme_odff_dtack_n
<=
'0'
;
vme_odff_dtack_n
<=
'0'
;
if
vme_idff_write_n
=
'1'
and
g_VME32
and
s_transferType
=
MBLT
then
-- Early release for MBLT.
vme_dtack_async_ctrl
<=
'1'
;
end
if
;
end
if
;
end
if
;
-- ANSI/VITA 1-1994 Rule 2.57
-- ANSI/VITA 1-1994 Rule 2.57
...
@@ -930,6 +946,16 @@ begin
...
@@ -930,6 +946,16 @@ begin
vme_data_o
<=
vme_odff_data
;
vme_data_o
<=
vme_odff_data
;
vme_lword_n_o
<=
vme_odff_lword_n
;
vme_lword_n_o
<=
vme_odff_lword_n
;
vme_dtack_n_o
<=
vme_odff_dtack_n
;
vme_dtack_oe_o
<=
vme_odff_dtack_oe
;
vme_dtack_oe_o
<=
vme_odff_dtack_oe
;
process
(
vme_odff_dtack_n
,
vme_nsync_ds_n_i
,
vme_dtack_async_ctrl
)
begin
if
vme_dtack_async_ctrl
=
'0'
then
vme_dtack_n_o
<=
vme_odff_dtack_n
;
else
-- Asserted (to 0) as soon as one ds signal is asserted (to 0).
-- Negated (to 1) as soon as both ds signal is negated (to 1).
vme_dtack_n_o
<=
vme_nsync_ds_n_i
(
0
)
and
vme_nsync_ds_n_i
(
1
);
end
if
;
end
process
;
end
rtl
;
end
rtl
;
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment