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VME64x core
Commits
e0f5eaad
Commit
e0f5eaad
authored
Oct 26, 2018
by
Tom Levens
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Implement amnesia address if parity is wrong
Signed-off-by:
Tom Levens
<
tom.levens@cern.ch
>
parent
ae052e76
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2 changed files
with
17 additions
and
15 deletions
+17
-15
vme_cr_csr_space.vhd
hdl/rtl/vme_cr_csr_space.vhd
+2
-12
xvme64x_core.vhd
hdl/rtl/xvme64x_core.vhd
+15
-3
No files found.
hdl/rtl/vme_cr_csr_space.vhd
View file @
e0f5eaad
...
@@ -121,7 +121,7 @@ entity vme_cr_csr_space is
...
@@ -121,7 +121,7 @@ entity vme_cr_csr_space is
clk_i
:
in
std_logic
;
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
vme_ga_i
:
in
std_logic_vector
(
5
downto
0
);
vme_ga_i
:
in
std_logic_vector
(
4
downto
0
);
vme_berr_n_i
:
in
std_logic
;
vme_berr_n_i
:
in
std_logic
;
bar_o
:
out
std_logic_vector
(
4
downto
0
);
bar_o
:
out
std_logic_vector
(
4
downto
0
);
module_enable_o
:
out
std_logic
;
module_enable_o
:
out
std_logic
;
...
@@ -146,7 +146,6 @@ end vme_cr_csr_space;
...
@@ -146,7 +146,6 @@ end vme_cr_csr_space;
architecture
rtl
of
vme_cr_csr_space
is
architecture
rtl
of
vme_cr_csr_space
is
signal
s_addr
:
unsigned
(
18
downto
2
);
signal
s_addr
:
unsigned
(
18
downto
2
);
signal
s_ga_parity
:
std_logic
;
signal
s_reg_bar
:
std_logic_vector
(
7
downto
0
);
signal
s_reg_bar
:
std_logic_vector
(
7
downto
0
);
signal
s_reg_bit_reg
:
std_logic_vector
(
7
downto
0
);
signal
s_reg_bit_reg
:
std_logic_vector
(
7
downto
0
);
signal
s_reg_cram_owner
:
std_logic_vector
(
7
downto
0
);
signal
s_reg_cram_owner
:
std_logic_vector
(
7
downto
0
);
...
@@ -309,11 +308,6 @@ begin
...
@@ -309,11 +308,6 @@ begin
s_addr
<=
c_END_CSR
s_addr
<=
c_END_CSR
else
'0'
;
else
'0'
;
-- If the crate is not driving the GA lines or the parity is even the BAR
-- register is set to 0x00 and the board will not answer CR/CSR accesses.
s_ga_parity
<=
vme_ga_i
(
5
)
xor
vme_ga_i
(
4
)
xor
vme_ga_i
(
3
)
xor
vme_ga_i
(
2
)
xor
vme_ga_i
(
1
)
xor
vme_ga_i
(
0
);
-- Write
-- Write
process
(
clk_i
)
process
(
clk_i
)
-- Write to ADER bytes, if implemented. Take advantage of
-- Write to ADER bytes, if implemented. Take advantage of
...
@@ -332,11 +326,7 @@ begin
...
@@ -332,11 +326,7 @@ begin
begin
begin
if
rising_edge
(
clk_i
)
then
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
if
rst_n_i
=
'0'
then
if
s_ga_parity
=
'1'
then
s_reg_bar
<=
vme_ga_i
&
"000"
;
s_reg_bar
<=
(
not
vme_ga_i
(
4
downto
0
))
&
"000"
;
else
s_reg_bar
<=
x"00"
;
end
if
;
s_reg_bit_reg
<=
x"00"
;
s_reg_bit_reg
<=
x"00"
;
s_reg_cram_owner
<=
x"00"
;
s_reg_cram_owner
<=
x"00"
;
s_reg_usr_bit_reg
<=
x"00"
;
s_reg_usr_bit_reg
<=
x"00"
;
...
...
hdl/rtl/xvme64x_core.vhd
View file @
e0f5eaad
...
@@ -187,6 +187,8 @@ architecture rtl of xvme64x_core is
...
@@ -187,6 +187,8 @@ architecture rtl of xvme64x_core is
signal
s_vme_irq_n_o
:
std_logic_vector
(
7
downto
1
);
signal
s_vme_irq_n_o
:
std_logic_vector
(
7
downto
1
);
signal
s_irq_ack
:
std_logic
;
signal
s_irq_ack
:
std_logic
;
signal
s_irq_pending
:
std_logic
;
signal
s_irq_pending
:
std_logic
;
signal
s_ga
:
std_logic_vector
(
4
downto
0
);
signal
s_ga_parity
:
std_logic
;
-- CR/CSR
-- CR/CSR
signal
s_cr_csr_addr
:
std_logic_vector
(
18
downto
2
);
signal
s_cr_csr_addr
:
std_logic_vector
(
18
downto
2
);
...
@@ -415,6 +417,16 @@ begin
...
@@ -415,6 +417,16 @@ begin
vme_irq_n_o
=>
vme_o
.
irq_n
vme_irq_n_o
=>
vme_o
.
irq_n
);
);
------------------------------------------------------------------------------
-- Geographical address
------------------------------------------------------------------------------
s_ga_parity
<=
vme_i
.
ga
(
5
)
xor
vme_i
.
ga
(
4
)
xor
vme_i
.
ga
(
3
)
xor
vme_i
.
ga
(
2
)
xor
vme_i
.
ga
(
1
)
xor
vme_i
.
ga
(
0
);
-- ANSI/VITA 1.1-1997 Recommendation 3.8: set the "amnesia address"
-- of 0x1E if bad parity.
s_ga
<=
not
vme_i
.
ga
(
4
downto
0
)
when
s_ga_parity
=
'1'
else
'1'
&
x"e"
;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- CR/CSR space
-- CR/CSR space
------------------------------------------------------------------------------
------------------------------------------------------------------------------
...
@@ -440,7 +452,7 @@ begin
...
@@ -440,7 +452,7 @@ begin
clk_i
=>
clk_i
,
clk_i
=>
clk_i
,
rst_n_i
=>
s_reset_n
,
rst_n_i
=>
s_reset_n
,
vme_ga_i
=>
vme_i
.
ga
,
vme_ga_i
=>
s_
ga
,
vme_berr_n_i
=>
s_vme_berr_n
,
vme_berr_n_i
=>
s_vme_berr_n
,
bar_o
=>
s_bar
,
bar_o
=>
s_bar
,
module_enable_o
=>
s_module_enable
,
module_enable_o
=>
s_module_enable
,
...
@@ -493,8 +505,8 @@ begin
...
@@ -493,8 +505,8 @@ begin
user_cr_addr_o
<=
(
others
=>
'0'
);
user_cr_addr_o
<=
(
others
=>
'0'
);
s_module_enable
<=
'1'
;
s_module_enable
<=
'1'
;
s_module_reset
<=
'0'
;
s_module_reset
<=
'0'
;
s_bar
<=
(
others
=>
'0'
)
;
s_bar
<=
s_ga
;
s_ader
<=
compute_static_ader
(
not
vme_i
.
ga
(
4
downto
0
)
);
s_ader
<=
compute_static_ader
(
s_ga
);
end
generate
;
end
generate
;
user_csr_addr_o
<=
s_user_csr_addr
;
user_csr_addr_o
<=
s_user_csr_addr
;
...
...
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