vme_bus: 2eSST improvements.

Use transfer rate to select number of cycles for setup and hold. Prefetch earlier.

vme_bus: 2eSST improvements.
Use transfer rate to select number of cycles for setup and hold. Prefetch earlier.
def8d371 · Tristan Gingold · 710dbc16 · def8d371
Commit def8d371 authored Jun 04, 2020 by Tristan Gingold
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Showing with 47 additions and 17 deletions

vme_bus.vhd hdl/rtl/vme_bus.vhd +47 -17

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--- a/hdl/rtl/vme_bus.vhd
+++ b/hdl/rtl/vme_bus.vhd
@@ -76,7 +76,7 @@ entity vme_bus is
    --  [15:12]      setup
    --  [19:16]      hold          320MB/s
    --  [23:20]      setup
-    data_timing     : in  std_logic_vector(23 downto 0) := x"11_22_22";
+    data_timing     : in  std_logic_vector(23 downto 0) := x"21_12_22";
    -- WB signals
    wb_stb_o        : out std_logic;
@@ -242,6 +242,7 @@ architecture rtl of vme_bus is
  signal s_DS_latch_count           : unsigned (2 downto 0);
  signal s_setup : unsigned(3 downto 0);
+  signal s_sst_timing : std_logic_vector(7 downto 0);
  -- WB FSM states
  type t_WBFSMstates is (
@@ -722,6 +723,7 @@ begin
            if vme_ds_n_i = "11" then
              vme_idff_addr    <= vme_addr_i;
              vme_idff_lword_n <= vme_lword_n_i;
+              vme_idff_data    <= vme_data_i;
              vme_xam <= addr_reg(7 downto 0);
@@ -739,6 +741,16 @@ begin
            vme_odff_addr_dir  <= '0';
            vme_cycles <= unsigned (vme_idff_addr (15 downto 8));
+            case vme_idff_data(1 downto 0) is
+              when "10" =>
+                --  2eSST-320
+                s_sst_timing <= data_timing(23 downto 16);
+              when "01" =>
+                --  2eSST-267
+                s_sst_timing <= data_timing(15 downto 8);
+              when others =>
+                s_sst_timing <= data_timing(7 downto 0);
+            end case;
            if vme_ds_n_i = "10" and s_wb_done = '1' then
              s_mainFSMstate <= VME_2E_TURN;
@@ -755,29 +767,32 @@ begin
              s_2e_dtack <= '0';
              --  Load the setup counter.
-              s_setup <= unsigned (data_timing(7 downto 4));
+              s_setup <= unsigned (s_sst_timing(7 downto 4));
+              --  Prefetch
+              s_wb_start <= '1';
              s_mainFSMstate <= VME_2E_DATA;
            end if;
          when VME_2E_DATA | VME_2E_SETUP =>
+            --  Setup: drive data and wait.
            vme_odff_dtack_oe  <= '1';
            vme_odff_dtack_n   <= s_2e_dtack;
            vme_odff_data_dir  <= '1';
            vme_odff_addr_dir  <= '1';
-            vme_odff_addr    <= data_reg(63 downto 33);
-            vme_odff_lword_n <= data_reg(32);
-            vme_odff_data    <= data_reg(31 downto 0);
            if s_mainFSMstate = VME_2E_DATA then
-              --  Prefetch
+              vme_odff_addr    <= data_reg(63 downto 33);
-              s_wb_start <= '1';
+              vme_odff_lword_n <= data_reg(32);
+              vme_odff_data    <= data_reg(31 downto 0);
            end if;
            if s_setup = 0 then
+              --  End of setup: will flip dtack.
              s_mainFSMstate <= VME_2E_DTACK;
              --  Load the hold counter.
-              s_setup <= unsigned (data_timing(3 downto 0));
+              s_setup <= unsigned (s_sst_timing(3 downto 0));
              s_2e_dtack <= not s_2e_dtack;
            else
              s_setup <= s_setup - 1;
@@ -785,6 +800,7 @@ begin
            end if;
          when VME_2E_DTACK =>
+            --  Drives new dtack.
            vme_odff_dtack_oe  <= '1';
            vme_odff_dtack_n   <= s_2e_dtack;
            vme_odff_data_dir  <= '1';
@@ -792,14 +808,19 @@ begin
            if s_setup = 0 then
              if s_2e_dtack = '0' and vme_cycles = 1 then
+                --  That was the last transfer.
                vme_berr_n_o <= '0';
                vme_odff_retry_n <= '0';
                vme_odff_retry_oe <= '1';
                s_mainFSMstate <= VME_2E_DONE;
              elsif s_wb_done = '1' then
                s_mainFSMstate <= VME_2E_DATA;
+                --  Prefetch
+                s_wb_start <= '1';
                --  Load the setup counter.
-                s_setup <= unsigned (data_timing(7 downto 4));
+                s_setup <= unsigned (s_sst_timing(7 downto 4));
                if s_2e_dtack = '0' then
                  vme_cycles <= vme_cycles - 1;
                end if;
@@ -1031,6 +1052,7 @@ begin
            if wb_ack_i = '1' or wb_err_i = '1' then
              -- WB ack
+              -- For classic mode, be sure strobe is negated.
              wb_stb_o <= '0';
              if s_transferType /= SINGLE then
@@ -1088,8 +1110,16 @@ begin
                  -- MBLT
                  s_wb_dataPhase <= '0';
-                  -- STB is 0, wait one cycle before the 2nd xfer.
+                  case g_WB_MODE is
-                  s_WBFSMstate <= MEMORY_PAUSE;
+                    when CLASSIC =>
+                      -- STB is 0, wait one cycle before the 2nd xfer.
+                      s_WBFSMstate <= MEMORY_PAUSE;
+                    when PIPELINED =>
+                      -- No need to pause, can directly start a new xfer.
+                      wb_stb_o <= '1';
+                      s_stall  <= '1';
+                      s_WBFSMstate <= MEMORY_REQ;
+                  end case;
                else
                  s_wb_done <= '1';
                  s_WBFSMstate <= IDLE;
@@ -1119,11 +1149,11 @@ begin
  -- WB Master
-   g_wb_addr32: if g_VME32 generate
+  g_wb_addr32: if g_VME32 generate
-     with g_WB_GRANULARITY select
+    with g_WB_GRANULARITY select
-       wb_adr_o <= "00" & addr_reg(31 downto 2) when WORD,
+      wb_adr_o <= "00" & addr_reg(31 downto 2) when WORD,
-                   addr_reg(31 downto 2) & "00" when BYTE;
+                  addr_reg(31 downto 2) & "00" when BYTE;
-   end generate;
+  end generate;
  g_wb_addr16: if not g_VME32 generate
     with g_WB_GRANULARITY select
        wb_adr_o <= "0" & addr_reg(31 downto 1) when WORD,