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VME64x core
Commit dcc45631 authored by dpedrett's avatar dpedrett
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vfc top level, ucf and testbench files updated 

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@192 665b4545-5c6b-4c24-801b-41150b02b44b
parent 10dfcdb0
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hdl/boards/vfc/SFpga.ucf
View file @ dcc45631
...@@ -241,7 +241,7 @@ NET "clk_i" LOC = B14; ...@@ -241,7 +241,7 @@ NET "clk_i" LOC = B14;
NET "clk_i" TNM_NET = "clk_i_group"; NET "clk_i" TNM_NET = "clk_i_group";
#TIMESPEC TS_clk_i = PERIOD "clk_i" 50 ns HIGH 50%; #TIMESPEC TS_clk_i = PERIOD "clk_i" 50 ns HIGH 50%;
#Created by Constraints Editor (xc6slx150t-fgg676-3) - 2011/06/30 #Created by Constraints Editor (xc6slx150t-fgg676-3) - 2011/06/30
TIMESPEC "TS_clk_i" = PERIOD "clk_i_group" 40 ns HIGH 50%; TIMESPEC "TS_clk_i" = PERIOD "clk_i_group" 50 ns HIGH 50%;
# Add by Davide for debug # Add by Davide for debug
NET "leds[0]" LOC = P5; NET "leds[0]" LOC = P5;
NET "leds[1]" LOC = R4; NET "leds[1]" LOC = R4;
......
hdl/boards/vfc/rtl/IRQ_Generator_Top.vhd
View file @ dcc45631
...@@ -40,8 +40,8 @@ ...@@ -40,8 +40,8 @@
-- Authors: -- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) -- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch) -- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012 -- Date 11/2012
-- Version v0.02 -- Version v0.03
--______________________________________________________________________________ --______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE -- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------ -- ------------------------------------
...@@ -64,8 +64,8 @@ ...@@ -64,8 +64,8 @@
-- Entity declaration -- Entity declaration
--=========================================================================== --===========================================================================
entity IRQ_Generator_Top is entity IRQ_Generator_Top is
generic(g_width : integer := c_width; generic(g_wb_data_width : integer := c_width;
g_addr_width : integer := c_addr_width g_wb_addr_width : integer := c_addr_width
); );
port ( -- IRQ_Generator port ( -- IRQ_Generator
clk_i : in std_logic; clk_i : in std_logic;
...@@ -75,15 +75,15 @@ generic(g_width : integer := c_width; ...@@ -75,15 +75,15 @@ generic(g_width : integer := c_width;
-- wb slave side -- wb slave side
cyc_i : in std_logic; cyc_i : in std_logic;
stb_i : in std_logic; stb_i : in std_logic;
adr_i : in std_logic_vector (g_addr_width - 1 downto 0); adr_i : in std_logic_vector (g_wb_addr_width - 1 downto 0);
sel_i : in std_logic_vector (f_div8(g_width) - 1 downto 0); sel_i : in std_logic_vector (f_div8(g_wb_data_width) - 1 downto 0);
we_i : in std_logic; we_i : in std_logic;
dat_i : in std_logic_vector (g_width - 1 downto 0); dat_i : in std_logic_vector (g_wb_data_width - 1 downto 0);
ack_o : out std_logic; ack_o : out std_logic;
err_o : out std_logic; err_o : out std_logic;
rty_o : out std_logic; rty_o : out std_logic;
stall_o : out std_logic; stall_o : out std_logic;
dat_o : out std_logic_vector (g_width - 1 downto 0) dat_o : out std_logic_vector (g_wb_data_width - 1 downto 0)
); );
end IRQ_Generator_Top; end IRQ_Generator_Top;
--=========================================================================== --===========================================================================
...@@ -99,7 +99,7 @@ signal s_Int_Count_o : std_logic_vector(31 downto 0); ...@@ -99,7 +99,7 @@ signal s_Int_Count_o : std_logic_vector(31 downto 0);
signal s_Read_IntCount : std_logic; signal s_Read_IntCount : std_logic;
signal s_data : std_logic_vector(31 downto 0); signal s_data : std_logic_vector(31 downto 0);
signal s_data_f : std_logic_vector(31 downto 0); signal s_data_f : std_logic_vector(31 downto 0);
signal s_data_o : std_logic_vector(g_width - 1 downto 0); signal s_data_o : std_logic_vector(g_wb_data_width - 1 downto 0);
signal s_IntCount_sel : std_logic; signal s_IntCount_sel : std_logic;
signal s_Freq_sel : std_logic; signal s_Freq_sel : std_logic;
signal s_wea : std_logic; signal s_wea : std_logic;
...@@ -141,7 +141,7 @@ s_en_Freq <= '1' when (s_Freq_sel = '1' and s_wea = '1') else '0'; ...@@ -141,7 +141,7 @@ s_en_Freq <= '1' when (s_Freq_sel = '1' and s_wea = '1') else '0';
-- the WB data bus is 32 or 64 bit width, so the following processes have been -- the WB data bus is 32 or 64 bit width, so the following processes have been
-- added: -- added:
gen64 : if (g_width = 64) generate gen64 : if (g_wb_data_width = 64) generate
s_data <= dat_i(63 downto 32); s_data <= dat_i(63 downto 32);
s_data_f <= dat_i(31 downto 0); s_data_f <= dat_i(31 downto 0);
s_data_o <= s_INT_COUNT & s_FREQ; s_data_o <= s_INT_COUNT & s_FREQ;
...@@ -151,7 +151,7 @@ gen64 : if (g_width = 64) generate ...@@ -151,7 +151,7 @@ gen64 : if (g_width = 64) generate
'0'; '0';
end generate gen64; end generate gen64;
gen32 : if (g_width = 32) generate gen32 : if (g_wb_data_width = 32) generate
s_data <= dat_i; s_data <= dat_i;
s_data_f <= dat_i; s_data_f <= dat_i;
s_data_o <= s_INT_COUNT when s_IntCount_sel = '1' else s_data_o <= s_INT_COUNT when s_IntCount_sel = '1' else
......
hdl/boards/vfc/rtl/IRQ_generator.vhd
View file @ dcc45631
...@@ -57,8 +57,8 @@ ...@@ -57,8 +57,8 @@
-- Authors: -- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) -- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch) -- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012 -- Date 11/2012
-- Version v0.02 -- Version v0.03
--______________________________________________________________________________ --______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE -- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------ -- ------------------------------------
......
hdl/boards/vfc/rtl/TOP_LEVEL.vhd
View file @ dcc45631
This diff is collapsed.
hdl/boards/vfc/rtl/WB_Bridge.vhd
View file @ dcc45631
...@@ -20,8 +20,8 @@ ...@@ -20,8 +20,8 @@
-- Authors: -- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) -- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch) -- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012 -- Date 11/2012
-- Version v0.02 -- Version v0.03
--______________________________________________________________________________ --______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE -- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------ -- ------------------------------------
...@@ -45,8 +45,8 @@ use work.vme64x_pack.all; ...@@ -45,8 +45,8 @@ use work.vme64x_pack.all;
-- Entity declaration -- Entity declaration
--=========================================================================== --===========================================================================
entity WB_Bridge is entity WB_Bridge is
generic(g_width : integer := c_width; generic(g_wb_data_width : integer := c_width;
g_addr_width : integer := c_addr_width g_wb_addr_width : integer := c_addr_width
); );
Port ( clk_i : in std_logic; Port ( clk_i : in std_logic;
rst_i : in std_logic; rst_i : in std_logic;
...@@ -54,26 +54,26 @@ generic(g_width : integer := c_width; ...@@ -54,26 +54,26 @@ generic(g_width : integer := c_width;
Int_Req_o : out std_logic; Int_Req_o : out std_logic;
cyc_i : in std_logic; cyc_i : in std_logic;
stb_i : in std_logic; stb_i : in std_logic;
adr_i : in std_logic_vector (g_addr_width - 1 downto 0); adr_i : in std_logic_vector (g_wb_addr_width - 1 downto 0);
dat_i : in std_logic_vector (g_width - 1 downto 0); dat_i : in std_logic_vector (g_wb_data_width - 1 downto 0);
sel_i : in std_logic_vector (f_div8(g_width) - 1 downto 0); sel_i : in std_logic_vector (f_div8(g_wb_data_width) - 1 downto 0);
we_i : in std_logic; we_i : in std_logic;
ack_o : out std_logic; ack_o : out std_logic;
err_o : out std_logic; err_o : out std_logic;
rty_o : out std_logic; rty_o : out std_logic;
stall_o : out std_logic; stall_o : out std_logic;
dat_o : out std_logic_vector (g_width - 1 downto 0); dat_o : out std_logic_vector (g_wb_data_width - 1 downto 0);
m_cyc_o : out std_logic; m_cyc_o : out std_logic;
m_stb_o : out std_logic; m_stb_o : out std_logic;
m_adr_o : out std_logic_vector (g_addr_width - 1 downto 0); m_adr_o : out std_logic_vector (g_wb_addr_width - 1 downto 0);
m_dat_o : out std_logic_vector (g_width - 1 downto 0); m_dat_o : out std_logic_vector (g_wb_data_width - 1 downto 0);
m_sel_o : out std_logic_vector (f_div8(g_width) - 1 downto 0); m_sel_o : out std_logic_vector (f_div8(g_wb_data_width) - 1 downto 0);
m_we_o : out std_logic; m_we_o : out std_logic;
m_ack_i : in std_logic; m_ack_i : in std_logic;
m_err_i : in std_logic; m_err_i : in std_logic;
m_stall_i : in std_logic; m_stall_i : in std_logic;
m_rty_i : in std_logic; m_rty_i : in std_logic;
m_dat_i : in std_logic_vector (g_width - 1 downto 0)); m_dat_i : in std_logic_vector (g_wb_data_width - 1 downto 0));
end WB_Bridge; end WB_Bridge;
--=========================================================================== --===========================================================================
-- Architecture declaration -- Architecture declaration
...@@ -89,11 +89,11 @@ signal s_ack_gen : std_logic; ...@@ -89,11 +89,11 @@ signal s_ack_gen : std_logic;
signal s_err_gen : std_logic; signal s_err_gen : std_logic;
signal s_rty_gen : std_logic; signal s_rty_gen : std_logic;
signal s_stall_gen : std_logic; signal s_stall_gen : std_logic;
signal s_data_o_gen : std_logic_vector(g_width - 1 downto 0); signal s_data_o_gen : std_logic_vector(g_wb_data_width - 1 downto 0);
component IRQ_Generator_Top is component IRQ_Generator_Top is
generic(g_width : integer := c_width; generic(g_wb_data_width : integer := c_width;
g_addr_width : integer := c_addr_width g_wb_addr_width : integer := c_addr_width
); );
port( port(
clk_i : in std_logic; clk_i : in std_logic;
...@@ -101,16 +101,16 @@ signal s_data_o_gen : std_logic_vector(g_width - 1 downto 0); ...@@ -101,16 +101,16 @@ signal s_data_o_gen : std_logic_vector(g_width - 1 downto 0);
Int_Ack_i : in std_logic; Int_Ack_i : in std_logic;
cyc_i : in std_logic; cyc_i : in std_logic;
stb_i : in std_logic; stb_i : in std_logic;
adr_i : in std_logic_vector(g_addr_width - 1 downto 0); adr_i : in std_logic_vector(g_wb_addr_width - 1 downto 0);
sel_i : in std_logic_vector(f_div8(g_width) - 1 downto 0); sel_i : in std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
we_i : in std_logic; we_i : in std_logic;
dat_i : in std_logic_vector(g_width - 1 downto 0); dat_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
Int_Req_o : out std_logic; Int_Req_o : out std_logic;
ack_o : out std_logic; ack_o : out std_logic;
err_o : out std_logic; err_o : out std_logic;
rty_o : out std_logic; rty_o : out std_logic;
stall_o : out std_logic; stall_o : out std_logic;
dat_o : out std_logic_vector(g_width - 1 downto 0) dat_o : out std_logic_vector(g_wb_data_width - 1 downto 0)
); );
end component IRQ_Generator_Top; end component IRQ_Generator_Top;
--=========================================================================== --===========================================================================
...@@ -121,11 +121,11 @@ begin ...@@ -121,11 +121,11 @@ begin
-- check if the IRQ Generator is addressed (0x00 or 0x04). -- check if the IRQ Generator is addressed (0x00 or 0x04).
-- if not s_WbAppl is '1' and the component work as a bridge -- if not s_WbAppl is '1' and the component work as a bridge
-- between the vme64x core and the Wb Application -- between the vme64x core and the Wb Application
genIRQGen64 : if (g_width = 64) generate genIRQGen64 : if (g_wb_data_width = 64) generate
s_IRQGen <= '1' when (unsigned(adr_i) = 0) else '0'; s_IRQGen <= '1' when (unsigned(adr_i) = 0) else '0';
end generate genIRQGen64; end generate genIRQGen64;
genIRQGen32 : if (g_width = 32) generate genIRQGen32 : if (g_wb_data_width = 32) generate
s_IRQGen <= '1' when unsigned(adr_i) = 0 or s_IRQGen <= '1' when unsigned(adr_i) = 0 or
unsigned(adr_i) = 1 else '0'; unsigned(adr_i) = 1 else '0';
end generate genIRQGen32; end generate genIRQGen32;
...@@ -154,8 +154,8 @@ m_sel_o <= sel_i; ...@@ -154,8 +154,8 @@ m_sel_o <= sel_i;
m_we_o <= we_i; m_we_o <= we_i;
---------------------------------------------------------------------- ----------------------------------------------------------------------
Inst_IRQ_Generator_Top: IRQ_Generator_Top Inst_IRQ_Generator_Top: IRQ_Generator_Top
generic map(g_width => g_width, generic map(g_wb_data_width => g_wb_data_width,
g_addr_width => g_addr_width g_wb_addr_width => g_wb_addr_width
) )
port map( port map(
clk_i => clk_i, clk_i => clk_i,
......
hdl/boards/vfc/rtl/ram_8bits.vhd
View file @ dcc45631
...@@ -9,8 +9,8 @@ ...@@ -9,8 +9,8 @@
-- Authors: -- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) -- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch) -- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012 -- Date 11/2012
-- Version v0.02 -- Version v0.03
--______________________________________________________________________________ --______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE -- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------ -- ------------------------------------
......
hdl/boards/vfc/rtl/spram.vhd
View file @ dcc45631
...@@ -11,8 +11,8 @@ ...@@ -11,8 +11,8 @@
-- Authors: -- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) -- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch) -- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012 -- Date 11/2012
-- Version v0.02 -- Version v0.03
--______________________________________________________________________________ --______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE -- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------ -- ------------------------------------
......
hdl/boards/vfc/rtl/xwb_ram.vhd
View file @ dcc45631
...@@ -38,8 +38,8 @@ ...@@ -38,8 +38,8 @@
-- Authors: -- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) -- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch) -- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012 -- Date 11/2012
-- Version v0.02 -- Version v0.03
--______________________________________________________________________________ --______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE -- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------ -- ------------------------------------
......
hdl/boards/vfc/sim/testbench/VME64x_SIM_Package.vhd
View file @ dcc45631
...@@ -9,7 +9,7 @@ ...@@ -9,7 +9,7 @@
-- --
-- Company : CERN -- Company : CERN
-- --
-- Description : VME64x procedures for test the VME64x Slave -- Description : VME64x procedures for test the VME64x core
library IEEE; library IEEE;
library std; library std;
...@@ -236,7 +236,7 @@ begin ...@@ -236,7 +236,7 @@ begin
assert(VME64xBus_In.Vme64xBerrN /= '1') report "THE SLAVE ASSERTED THE Berr LINE" severity error; assert(VME64xBus_In.Vme64xBerrN /= '1') report "THE SLAVE ASSERTED THE Berr LINE" severity error;
else else
ShiftData(write_n => '1', s_dataTransferType => s_dataTransferType, s_dataToShift => VME64xBus_In.Vme64xDATA, v_dataToShiftOut => v_dataToReceiveOut); ShiftData(write_n => '1', s_dataTransferType => s_dataTransferType, s_dataToShift => VME64xBus_In.Vme64xDATA, v_dataToShiftOut => v_dataToReceiveOut);
assert (v_dataToReceiveOut /= s_dataToReceive)report "CORRECT DATA!!!" severity error; -- assert (v_dataToReceiveOut /= s_dataToReceive)report "CORRECT DATA!!!" severity error;
assert (v_dataToReceiveOut = s_dataToReceive)report "RECEIVED WRONG DATA!!!" severity failure; assert (v_dataToReceiveOut = s_dataToReceive)report "RECEIVED WRONG DATA!!!" severity failure;
--assert (VME64xBus_In.Vme64xDATA = s_dataToReceive)report "Error Received Wrong Data" severity failure; --assert (VME64xBus_In.Vme64xDATA = s_dataToReceive)report "Error Received Wrong Data" severity failure;
--wait for 10 ns; --wait for 10 ns;
...@@ -465,7 +465,7 @@ DataType : out std_logic_vector (3 downto 0)) is ...@@ -465,7 +465,7 @@ DataType : out std_logic_vector (3 downto 0)) is
assert(VME64xBus_In.Vme64xBerrN /= '1') report "THE SLAVE ASSERTED THE Berr LINE" severity error; assert(VME64xBus_In.Vme64xBerrN /= '1') report "THE SLAVE ASSERTED THE Berr LINE" severity error;
else else
ShiftData(write_n => '1', s_dataTransferType => s_dataTransferType, s_dataToShift => VME64xBus_In.Vme64xDATA, v_dataToShiftOut => v_dataToReceiveOut); ShiftData(write_n => '1', s_dataTransferType => s_dataTransferType, s_dataToShift => VME64xBus_In.Vme64xDATA, v_dataToShiftOut => v_dataToReceiveOut);
assert (v_dataToReceiveOut /= s_dataToReceive)report "CORRECT DATA!!!" severity error; -- assert (v_dataToReceiveOut /= s_dataToReceive)report "CORRECT DATA!!!" severity error;
assert (v_dataToReceiveOut = s_dataToReceive)report "RECEIVED WRONG DATA!!!" severity failure; assert (v_dataToReceiveOut = s_dataToReceive)report "RECEIVED WRONG DATA!!!" severity failure;
end if; end if;
...@@ -529,7 +529,7 @@ DataType : out std_logic_vector (3 downto 0)) is ...@@ -529,7 +529,7 @@ DataType : out std_logic_vector (3 downto 0)) is
exit; exit;
else else
v_dataToReceiveOut := VME64xBus_In.Vme64xDATA; v_dataToReceiveOut := VME64xBus_In.Vme64xDATA;
assert (v_dataToReceiveOut /= s_Buffer_BLT(n))report "CORRECT DATA!!!" severity error; -- assert (v_dataToReceiveOut /= s_Buffer_BLT(n))report "CORRECT DATA!!!" severity error;
assert (v_dataToReceiveOut = s_Buffer_BLT(n))report "RECEIVED WRONG DATA!!!" severity failure; assert (v_dataToReceiveOut = s_Buffer_BLT(n))report "RECEIVED WRONG DATA!!!" severity failure;
end if; end if;
VME64xBus_Out.Vme64xDs0N <= '1'; VME64xBus_Out.Vme64xDs0N <= '1';
...@@ -739,7 +739,7 @@ DataType : out std_logic_vector (3 downto 0)) is ...@@ -739,7 +739,7 @@ DataType : out std_logic_vector (3 downto 0)) is
v_dataToReceiveOut(31 downto 0) := VME64xBus_In.Vme64xDATA; v_dataToReceiveOut(31 downto 0) := VME64xBus_In.Vme64xDATA;
v_dataToReceiveOut(32) := VME64xBus_In.Vme64xLWORDN; v_dataToReceiveOut(32) := VME64xBus_In.Vme64xLWORDN;
--assert (v_dataToReceiveOut /= s_Buffer_MBLT(n))report "CORRECT DATA!!!" severity error; --assert (v_dataToReceiveOut /= s_Buffer_MBLT(n))report "CORRECT DATA!!!" severity error;
--assert (v_dataToReceiveOut = s_Buffer_MBLT(n))report "RECEIVED WRONG DATA!!!" severity failure; assert (v_dataToReceiveOut = s_Buffer_MBLT(n))report "RECEIVED WRONG DATA!!!" severity failure;
--NB start to read from the first location written otherwise use n + x --NB start to read from the first location written otherwise use n + x
VME64xBus_Out.Vme64xDs0N <= '1'; VME64xBus_Out.Vme64xDs0N <= '1';
VME64xBus_Out.Vme64xDs1N <= '1'; VME64xBus_Out.Vme64xDs1N <= '1';
...@@ -971,7 +971,7 @@ DataType : out std_logic_vector (3 downto 0)) is ...@@ -971,7 +971,7 @@ DataType : out std_logic_vector (3 downto 0)) is
assert(VME64xBus_In.Vme64xBerrN /= '1') report "THE SLAVE ASSERTED THE Berr LINE" severity error; assert(VME64xBus_In.Vme64xBerrN /= '1') report "THE SLAVE ASSERTED THE Berr LINE" severity error;
else else
ShiftData(write_n => '1', s_dataTransferType => s_dataTransferType, s_dataToShift => VME64xBus_In.Vme64xDATA, v_dataToShiftOut => v_dataToReceiveOut); ShiftData(write_n => '1', s_dataTransferType => s_dataTransferType, s_dataToShift => VME64xBus_In.Vme64xDATA, v_dataToShiftOut => v_dataToReceiveOut);
assert (v_dataToReceiveOut /= s_dataToReceive)report "CORRECT DATA!!!" severity error; --assert (v_dataToReceiveOut /= s_dataToReceive)report "CORRECT DATA!!!" severity error;
assert (v_dataToReceiveOut = s_dataToReceive)report "RECEIVED WRONG DATA!!!" severity failure; assert (v_dataToReceiveOut = s_dataToReceive)report "RECEIVED WRONG DATA!!!" severity failure;
end if; end if;
VME64xBus_Out.Vme64xLWORDN <= '1'; VME64xBus_Out.Vme64xLWORDN <= '1';
...@@ -1112,7 +1112,7 @@ DataType : out std_logic_vector (3 downto 0)) is ...@@ -1112,7 +1112,7 @@ DataType : out std_logic_vector (3 downto 0)) is
exit; exit;
else else
v_dataToReceiveOut := VME64xBus_In.Vme64xDATA; v_dataToReceiveOut := VME64xBus_In.Vme64xDATA;
assert (v_dataToReceiveOut /= s_Buffer_BLT(n))report "CORRECT DATA!!!" severity error; --assert (v_dataToReceiveOut /= s_Buffer_BLT(n))report "CORRECT DATA!!!" severity error;
assert (v_dataToReceiveOut = s_Buffer_BLT(n))report "RECEIVED WRONG DATA!!!" severity failure; assert (v_dataToReceiveOut = s_Buffer_BLT(n))report "RECEIVED WRONG DATA!!!" severity failure;
end if; end if;
VME64xBus_Out.Vme64xDs0N <= '1'; VME64xBus_Out.Vme64xDs0N <= '1';
...@@ -1265,7 +1265,7 @@ DataType : out std_logic_vector (3 downto 0)) is ...@@ -1265,7 +1265,7 @@ DataType : out std_logic_vector (3 downto 0)) is
v_dataToReceiveOut(63 downto 33) := VME64xBus_In.Vme64xADDR; v_dataToReceiveOut(63 downto 33) := VME64xBus_In.Vme64xADDR;
v_dataToReceiveOut(31 downto 0) := VME64xBus_In.Vme64xDATA; v_dataToReceiveOut(31 downto 0) := VME64xBus_In.Vme64xDATA;
v_dataToReceiveOut(32) := VME64xBus_In.Vme64xLWORDN; v_dataToReceiveOut(32) := VME64xBus_In.Vme64xLWORDN;
assert (v_dataToReceiveOut /= s_Buffer_MBLT(n))report "CORRECT DATA!!!" severity error; --assert (v_dataToReceiveOut /= s_Buffer_MBLT(n))report "CORRECT DATA!!!" severity error;
assert (v_dataToReceiveOut = s_Buffer_MBLT(n))report "RECEIVED WRONG DATA!!!" severity failure; assert (v_dataToReceiveOut = s_Buffer_MBLT(n))report "RECEIVED WRONG DATA!!!" severity failure;
--NB start to read from the first location written otherwise use n + x --NB start to read from the first location written otherwise use n + x
VME64xBus_Out.Vme64xDs0N <= '1'; VME64xBus_Out.Vme64xDs0N <= '1';
...@@ -1458,7 +1458,7 @@ DataType : out std_logic_vector (3 downto 0)) is ...@@ -1458,7 +1458,7 @@ DataType : out std_logic_vector (3 downto 0)) is
v_dataToReceiveOut(63 downto 33) := VME64xBus_In.Vme64xADDR; v_dataToReceiveOut(63 downto 33) := VME64xBus_In.Vme64xADDR;
v_dataToReceiveOut(31 downto 0) := VME64xBus_In.Vme64xDATA; v_dataToReceiveOut(31 downto 0) := VME64xBus_In.Vme64xDATA;
v_dataToReceiveOut(32) := VME64xBus_In.Vme64xLWORDN; v_dataToReceiveOut(32) := VME64xBus_In.Vme64xLWORDN;
assert (v_dataToReceiveOut /= s_Buffer_MBLT(n))report "CORRECT DATA!!!" severity error; --assert (v_dataToReceiveOut /= s_Buffer_MBLT(n))report "CORRECT DATA!!!" severity error;
assert (v_dataToReceiveOut = s_Buffer_MBLT(n))report "RECEIVED WRONG DATA!!!" severity failure; assert (v_dataToReceiveOut = s_Buffer_MBLT(n))report "RECEIVED WRONG DATA!!!" severity failure;
--NB start to read from the first location written otherwise use n + x --NB start to read from the first location written otherwise use n + x
n := n + 1; n := n + 1;
......
hdl/boards/vfc/sim/testbench/VME64x_TB.vhd
View file @ dcc45631
This diff is collapsed.
hdl/boards/vfc/syn/VME64xTest.xise
View file @ dcc45631
...@@ -15,10 +15,6 @@ ...@@ -15,10 +15,6 @@
<version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/> <version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/>
<files> <files>
<file xil_pn:name="../rtl/TOP_LEVEL.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../rtl/IRQ_generator.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../rtl/IRQ_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/> <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
...@@ -132,6 +128,10 @@ ...@@ -132,6 +128,10 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/> <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file> </file>
<file xil_pn:name="../rtl/TOP_LEVEL.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
</files> </files>
<autoManagedFiles> <autoManagedFiles>
...@@ -255,7 +255,7 @@ ...@@ -255,7 +255,7 @@
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/> <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> <property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/> <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="uut" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
...@@ -295,8 +295,8 @@ ...@@ -295,8 +295,8 @@
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/> <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/> <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> <property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="uut" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> <property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="uut" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/> <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
...@@ -392,8 +392,9 @@ ...@@ -392,8 +392,9 @@
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/VME64x_TB" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/VME64x_TB" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.VME64x_TB" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.VME64x_TB" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="work.VME64x_TB" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="uut" xil_pn:valueState="non-default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/> <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/> <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
......
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