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VME64x core
Commits
d3eaf709
Commit
d3eaf709
authored
Oct 11, 2017
by
Tristan Gingold
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Use gc_sync_register to perform async synchronization.
parent
e4d8ca3c
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52 additions
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33 deletions
+52
-33
VME64xCore_Top.vhd
hdl/rtl/VME64xCore_Top.vhd
+52
-33
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hdl/rtl/VME64xCore_Top.vhd
View file @
d3eaf709
...
@@ -305,13 +305,12 @@ architecture RTL of VME64xCore_Top is
...
@@ -305,13 +305,12 @@ architecture RTL of VME64xCore_Top is
signal
s_am
:
std_logic_vector
(
5
downto
0
);
signal
s_am
:
std_logic_vector
(
5
downto
0
);
-- Oversampled input signals
-- Oversampled input signals
constant
nbr_stages
:
natural
:
=
2
;
-- Number of stages for synchronizers
signal
s_VME_RST_n
:
std_logic
;
signal
s_VME_RST_n
:
std_logic_vector
(
nbr_stages
-
1
downto
0
);
signal
s_VME_AS_n
:
std_logic
;
signal
s_VME_AS_n
:
std_logic_vector
(
nbr_stages
-
1
downto
0
);
signal
s_VME_WRITE_n
:
std_logic
;
signal
s_VME_WRITE_n
:
std_logic_vector
(
nbr_stages
-
1
downto
0
);
signal
s_VME_DS_n
:
std_logic_vector
(
1
downto
0
);
signal
s_VME_DS_n
:
std_logic_vector
(
2
*
nbr_stages
-
1
downto
0
);
signal
s_VME_IACK_n
:
std_logic
;
signal
s_VME_IACK_n
:
std_logic_vector
(
nbr_stages
-
1
downto
0
);
signal
s_VME_IACKIN_n
:
std_logic
;
signal
s_VME_IACKIN_n
:
std_logic_vector
(
nbr_stages
-
1
downto
0
);
-- CR/CSR parameter arrays
-- CR/CSR parameter arrays
-- ADEM array has an extra index (-1) to simplify looping while checking the
-- ADEM array has an extra index (-1) to simplify looping while checking the
...
@@ -354,27 +353,47 @@ begin
...
@@ -354,27 +353,47 @@ begin
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Metastability
-- Metastability
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Input oversampling & edge detection; oversampling the input data is
-- Input oversampling: oversampling the input data is
-- necessary to avoid metastability problems. With 3 samples the probability
-- necessary to avoid metastability problems, but of course the transfer rate
-- of metastability problem will be very low but of course the transfer rate
-- will be slow down a little.
-- will be slow down a little.
process
(
clk_i
)
-- NOTE: the reset value is '0', which means that all signals are active
begin
-- at reset. But not for a long time and so is s_VME_RST_n.
if
rising_edge
(
clk_i
)
then
inst_vme_rst_resync
:
entity
work
.
gc_sync_register
s_VME_RST_n
<=
VME_RST_n_i
generic
map
(
g_width
=>
1
)
&
s_VME_RST_n
(
nbr_stages
-
1
downto
1
);
port
map
(
clk_i
=>
clk_i
,
s_VME_AS_n
<=
VME_AS_n_i
rst_n_a_i
=>
rst_n_i
,
&
s_VME_AS_n
(
nbr_stages
-
1
downto
1
);
d_i
(
0
)
=>
VME_RST_n_i
,
s_VME_WRITE_n
<=
VME_WRITE_n_i
q_o
(
0
)
=>
s_VME_RST_n
);
&
s_VME_WRITE_n
(
nbr_stages
-
1
downto
1
);
inst_vme_as_resync
:
entity
work
.
gc_sync_register
s_VME_DS_n
<=
VME_DS_n_i
generic
map
(
g_width
=>
1
)
&
s_VME_DS_n
(
2
*
nbr_stages
-
1
downto
2
);
port
map
(
clk_i
=>
clk_i
,
s_VME_IACK_n
<=
VME_IACK_n_i
rst_n_a_i
=>
rst_n_i
,
&
s_VME_IACK_n
(
nbr_stages
-
1
downto
1
);
d_i
(
0
)
=>
VME_AS_n_i
,
s_VME_IACKIN_n
<=
VME_IACKIN_n_i
q_o
(
0
)
=>
s_VME_AS_n
);
&
s_VME_IACKIN_n
(
nbr_stages
-
1
downto
1
);
inst_vme_write_resync
:
entity
work
.
gc_sync_register
end
if
;
generic
map
(
g_width
=>
1
)
end
process
;
port
map
(
clk_i
=>
clk_i
,
rst_n_a_i
=>
rst_n_i
,
d_i
(
0
)
=>
VME_WRITE_n_i
,
q_o
(
0
)
=>
s_VME_WRITE_n
);
inst_vme_ds_resync
:
entity
work
.
gc_sync_register
generic
map
(
g_width
=>
2
)
port
map
(
clk_i
=>
clk_i
,
rst_n_a_i
=>
rst_n_i
,
d_i
=>
VME_DS_n_i
,
q_o
=>
s_VME_DS_n
);
inst_vme_iack_resync
:
entity
work
.
gc_sync_register
generic
map
(
g_width
=>
1
)
port
map
(
clk_i
=>
clk_i
,
rst_n_a_i
=>
rst_n_i
,
d_i
(
0
)
=>
VME_IACK_n_i
,
q_o
(
0
)
=>
s_VME_IACK_n
);
inst_vme_iackin_resync
:
entity
work
.
gc_sync_register
generic
map
(
g_width
=>
1
)
port
map
(
clk_i
=>
clk_i
,
rst_n_a_i
=>
rst_n_i
,
d_i
(
0
)
=>
VME_IACKIN_n_i
,
q_o
(
0
)
=>
s_VME_IACKIN_n
);
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- VME Bus
-- VME Bus
...
@@ -390,13 +409,13 @@ begin
...
@@ -390,13 +409,13 @@ begin
rst_i
=>
s_reset
,
rst_i
=>
s_reset
,
-- VME
-- VME
VME_AS_n_i
=>
s_VME_AS_n
(
0
)
,
VME_AS_n_i
=>
s_VME_AS_n
,
VME_LWORD_n_o
=>
VME_LWORD_n_o
,
VME_LWORD_n_o
=>
VME_LWORD_n_o
,
VME_LWORD_n_i
=>
VME_LWORD_n_i
,
VME_LWORD_n_i
=>
VME_LWORD_n_i
,
VME_RETRY_n_o
=>
VME_RETRY_n_o
,
VME_RETRY_n_o
=>
VME_RETRY_n_o
,
VME_RETRY_OE_o
=>
VME_RETRY_OE_o
,
VME_RETRY_OE_o
=>
VME_RETRY_OE_o
,
VME_WRITE_n_i
=>
s_VME_WRITE_n
(
0
)
,
VME_WRITE_n_i
=>
s_VME_WRITE_n
,
VME_DS_n_i
=>
s_VME_DS_n
(
1
downto
0
)
,
VME_DS_n_i
=>
s_VME_DS_n
,
VME_DTACK_n_o
=>
VME_DTACK_n_o
,
VME_DTACK_n_o
=>
VME_DTACK_n_o
,
VME_DTACK_OE_o
=>
VME_DTACK_OE_o
,
VME_DTACK_OE_o
=>
VME_DTACK_OE_o
,
VME_BERR_n_o
=>
s_vme_berr_n
,
VME_BERR_n_o
=>
s_vme_berr_n
,
...
@@ -409,8 +428,8 @@ begin
...
@@ -409,8 +428,8 @@ begin
VME_DATA_DIR_o
=>
VME_DATA_DIR_o
,
VME_DATA_DIR_o
=>
VME_DATA_DIR_o
,
VME_DATA_OE_N_o
=>
VME_DATA_OE_N_o
,
VME_DATA_OE_N_o
=>
VME_DATA_OE_N_o
,
VME_AM_i
=>
VME_AM_i
,
VME_AM_i
=>
VME_AM_i
,
VME_IACK_n_i
=>
s_VME_IACK_n
(
0
)
,
VME_IACK_n_i
=>
s_VME_IACK_n
,
VME_IACKIN_n_i
=>
s_VME_IACKIN_n
(
0
)
,
VME_IACKIN_n_i
=>
s_VME_IACKIN_n
,
VME_IACKOUT_n_o
=>
VME_IACKOUT_n_o
,
VME_IACKOUT_n_o
=>
VME_IACKOUT_n_o
,
-- WB signals
-- WB signals
...
@@ -447,7 +466,7 @@ begin
...
@@ -447,7 +466,7 @@ begin
irq_ack_o
=>
s_irq_ack
irq_ack_o
=>
s_irq_ack
);
);
s_reset
<=
(
not
rst_n_i
)
or
(
not
s_VME_RST_n
(
0
)
);
s_reset
<=
(
not
rst_n_i
)
or
(
not
s_VME_RST_n
);
s_reset_n
<=
not
s_reset
;
s_reset_n
<=
not
s_reset
;
rst_n_o
<=
not
(
s_reset
or
s_module_reset
);
rst_n_o
<=
not
(
s_reset
or
s_module_reset
);
...
...
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