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VME64x core
Commits
d1683381
Commit
d1683381
authored
Sep 20, 2017
by
Tristan Gingold
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Plain Diff
Only support 32b data WB bus.
parent
01b08fee
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Showing
4 changed files
with
54 additions
and
140 deletions
+54
-140
VME64xCore_Top.vhd
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
+2
-2
VME_Wb_master.vhd
hdl/vme64x-core/rtl/VME_Wb_master.vhd
+23
-107
VME_bus.vhd
hdl/vme64x-core/rtl/VME_bus.vhd
+26
-28
vme64x_pack.vhd
hdl/vme64x-core/rtl/vme64x_pack.vhd
+3
-3
No files found.
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @
d1683381
...
...
@@ -111,8 +111,8 @@ use work.vme64x_pack.all;
entity
VME64xCore_Top
is
generic
(
g_CLOCK_PERIOD
:
integer
:
=
c_CLOCK_PERIOD
;
-- Clock period (ns)
g_WB_DATA_WIDTH
:
integer
:
=
c_DATA_WIDTH
;
-- WB data width:
must be 32 or 64
g_WB_ADDR_WIDTH
:
integer
:
=
c_ADDR_WIDTH
;
-- WB addr width:
64 or less
g_WB_DATA_WIDTH
:
integer
:
=
c_DATA_WIDTH
;
-- WB data width:
= 32
g_WB_ADDR_WIDTH
:
integer
:
=
c_ADDR_WIDTH
;
-- WB addr width:
<= 32
g_USER_CSR_EXT
:
boolean
:
=
false
;
-- Use external user CSR
-- Manufacturer ID: IEEE OUID
...
...
hdl/vme64x-core/rtl/VME_Wb_master.vhd
View file @
d1683381
...
...
@@ -82,9 +82,9 @@ entity VME_Wb_master is
cardSel_i
:
in
std_logic
;
reset_i
:
in
std_logic
;
BERRcondition_i
:
in
std_logic
;
sel_i
:
in
std_logic_vector
(
7
downto
0
);
locDataInSwap_i
:
in
std_logic_vector
(
63
downto
0
);
locDataOut_o
:
out
std_logic_vector
(
63
downto
0
);
sel_i
:
in
std_logic_vector
(
3
downto
0
);
locDataInSwap_i
:
in
std_logic_vector
(
31
downto
0
);
locDataOut_o
:
out
std_logic_vector
(
31
downto
0
);
rel_locAddr_i
:
in
std_logic_vector
(
31
downto
0
);
memAckWb_o
:
out
std_logic
;
err_o
:
out
std_logic
;
...
...
@@ -105,14 +105,9 @@ entity VME_Wb_master is
end
VME_Wb_master
;
architecture
Behavioral
of
VME_Wb_master
is
signal
s_shift_dx
:
std_logic
;
signal
s_cyc
:
std_logic
;
signal
s_AckWithError
:
std_logic
;
signal
s_wbData_i
:
std_logic_vector
(
63
downto
0
);
signal
s_memAckWB_d1
:
std_logic
;
signal
s_cyc
:
std_logic
;
begin
-- stb handler
process
(
clk_i
)
begin
...
...
@@ -146,82 +141,9 @@ begin
end
if
;
end
process
;
-- shift data and address for WB data bus 64 bits
gen64
:
if
(
g_WB_DATA_WIDTH
=
64
)
generate
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
locAddr_o
(
63
downto
29
)
<=
(
others
=>
'0'
);
locAddr_o
(
28
downto
0
)
<=
rel_locAddr_i
(
31
downto
3
);
end
if
;
end
process
;
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
case
sel_i
is
when
"10000000"
=>
WBdata_o
<=
std_logic_vector
(
unsigned
(
locDataInSwap_i
)
sll
56
);
when
"01000000"
=>
WBdata_o
<=
std_logic_vector
(
unsigned
(
locDataInSwap_i
)
sll
48
);
when
"00100000"
=>
WBdata_o
<=
std_logic_vector
(
unsigned
(
locDataInSwap_i
)
sll
40
);
when
"00010000"
=>
WBdata_o
<=
std_logic_vector
(
unsigned
(
locDataInSwap_i
)
sll
32
);
when
"00001000"
=>
WBdata_o
<=
std_logic_vector
(
unsigned
(
locDataInSwap_i
)
sll
24
);
when
"00000100"
=>
WBdata_o
<=
std_logic_vector
(
unsigned
(
locDataInSwap_i
)
sll
16
);
when
"00000010"
=>
WBdata_o
<=
std_logic_vector
(
unsigned
(
locDataInSwap_i
)
sll
8
);
when
"00000001"
=>
WBdata_o
<=
locDataInSwap_i
;
when
"11000000"
=>
WBdata_o
<=
std_logic_vector
(
unsigned
(
locDataInSwap_i
)
sll
48
);
when
"00110000"
=>
WBdata_o
<=
std_logic_vector
(
unsigned
(
locDataInSwap_i
)
sll
32
);
when
"00001100"
=>
WBdata_o
<=
std_logic_vector
(
unsigned
(
locDataInSwap_i
)
sll
16
);
when
"00000011"
=>
WBdata_o
<=
locDataInSwap_i
;
when
"11110000"
=>
WBdata_o
<=
std_logic_vector
(
unsigned
(
locDataInSwap_i
)
sll
32
);
when
"00001111"
=>
WBdata_o
<=
locDataInSwap_i
;
when
"11111111"
=>
WBdata_o
<=
locDataInSwap_i
;
when
others
=>
null
;
end
case
;
WbSel_o
<=
std_logic_vector
(
sel_i
);
end
if
;
end
process
;
process
(
sel_i
,
s_wbData_i
)
begin
case
sel_i
is
when
"00000010"
=>
locDataOut_o
<=
std_logic_vector
(
resize
(
unsigned
(
s_wbData_i
(
15
downto
0
))
srl
8
,
locDataOut_o
'length
));
when
"00000100"
=>
locDataOut_o
<=
std_logic_vector
(
resize
(
unsigned
(
s_wbData_i
(
23
downto
0
))
srl
16
,
locDataOut_o
'length
));
when
"00001000"
=>
locDataOut_o
<=
std_logic_vector
(
resize
(
unsigned
(
s_wbData_i
(
31
downto
0
))
srl
24
,
locDataOut_o
'length
));
when
"00010000"
=>
locDataOut_o
<=
std_logic_vector
(
resize
(
unsigned
(
s_wbData_i
(
39
downto
0
))
srl
32
,
locDataOut_o
'length
));
when
"00100000"
=>
locDataOut_o
<=
std_logic_vector
(
resize
(
unsigned
(
s_wbData_i
(
47
downto
0
))
srl
40
,
locDataOut_o
'length
));
when
"01000000"
=>
locDataOut_o
<=
std_logic_vector
(
resize
(
unsigned
(
s_wbData_i
(
55
downto
0
))
srl
48
,
locDataOut_o
'length
));
when
"10000000"
=>
locDataOut_o
<=
std_logic_vector
(
resize
(
unsigned
(
s_wbData_i
(
63
downto
0
))
srl
56
,
locDataOut_o
'length
));
when
"00001100"
=>
locDataOut_o
<=
std_logic_vector
(
resize
(
unsigned
(
s_wbData_i
(
31
downto
0
))
srl
16
,
locDataOut_o
'length
));
when
"00110000"
=>
locDataOut_o
<=
std_logic_vector
(
resize
(
unsigned
(
s_wbData_i
(
47
downto
0
))
srl
32
,
locDataOut_o
'length
));
when
"11000000"
=>
locDataOut_o
<=
std_logic_vector
(
resize
(
unsigned
(
s_wbData_i
(
63
downto
0
))
srl
48
,
locDataOut_o
'length
));
when
"00000001"
=>
locDataOut_o
<=
std_logic_vector
(
resize
(
unsigned
(
s_wbData_i
(
7
downto
0
)),
locDataOut_o
'length
));
when
"00000011"
=>
locDataOut_o
<=
std_logic_vector
(
resize
(
unsigned
(
s_wbData_i
(
15
downto
0
)),
locDataOut_o
'length
));
when
"00001111"
=>
locDataOut_o
<=
std_logic_vector
(
resize
(
unsigned
(
s_wbData_i
(
31
downto
0
)),
locDataOut_o
'length
));
when
"11110000"
=>
locDataOut_o
<=
std_logic_vector
(
resize
(
unsigned
(
s_wbData_i
(
63
downto
0
))
srl
32
,
locDataOut_o
'length
));
when
"11111111"
=>
locDataOut_o
<=
std_logic_vector
(
resize
(
unsigned
(
s_wbData_i
(
63
downto
0
)),
locDataOut_o
'length
));
when
others
=>
locDataOut_o
<=
(
others
=>
'0'
);
end
case
;
end
process
;
end
generate
gen64
;
-- shift data and address for WB data bus 32 bits
gen32
:
if
(
g_WB_DATA_WIDTH
=
32
)
generate
assert
g_WB_DATA_WIDTH
=
32
severity
failure
;
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
...
...
@@ -233,14 +155,11 @@ begin
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
WBdata_o
<=
locDataInSwap_i
(
31
downto
0
)
;
WbSel_o
<=
sel_i
(
3
downto
0
)
;
WBdata_o
<=
locDataInSwap_i
;
WbSel_o
<=
sel_i
;
end
if
;
end
process
;
locDataOut_o
<=
s_wbData_i
;
end
generate
gen32
;
err_o
<=
err_i
;
rty_o
<=
rty_i
;
...
...
@@ -251,12 +170,9 @@ begin
begin
if
rising_edge
(
clk_i
)
then
if
memAckWB_i
=
'1'
then
s_wbData_i
<=
(
others
=>
'0'
);
s_wbData_i
(
wbData_i
'range
)
<=
wbData_i
;
locDataOut_o
<=
wbData_i
;
end
if
;
s_memAckWb_d1
<=
memAckWB_i
or
s_AckWithError
or
rty_i
;
memAckWb_o
<=
memAckWB_i
or
s_AckWithError
or
rty_i
;
end
if
;
end
process
;
memAckWb_o
<=
s_memAckWB_d1
;
end
Behavioral
;
hdl/vme64x-core/rtl/VME_bus.vhd
View file @
d1683381
...
...
@@ -227,7 +227,7 @@ architecture RTL of VME_bus is
signal
s_card_sel
:
std_logic
;
-- WB memory is addressed
-- WishBone signals
signal
s_sel
:
std_logic_vector
(
7
downto
0
);
-- SEL WB
signal
s_sel
:
std_logic_vector
(
3
downto
0
);
-- SEL WB
-- Error signals
signal
s_BERRcondition
:
std_logic
;
-- Condition to set BERR
...
...
@@ -259,6 +259,9 @@ architecture RTL of VME_bus is
-- True if endianness converters are supported.
constant
c_SWAPPER_EN
:
boolean
:
=
False
;
begin
-- Consistency check.
assert
g_WB_DATA_WIDTH
=
32
report
"g_WB_DATA_WIDTH must be set to 32"
severity
failure
;
-- These output signals are connected to the buffers on the board
-- SN74VMEH22501A Function table: (A is fpga, B is VME connector)
...
...
@@ -347,7 +350,7 @@ begin
s_retry
<=
'0'
;
s_BERR_out
<=
'0'
;
s_mainFSMstate
<=
IDLE
;
s_sel
<=
"0000
0000
"
;
s_sel
<=
"0000"
;
s_ADDRlatched
<=
(
others
=>
'0'
);
s_LWORDlatched_n
<=
'0'
;
...
...
@@ -393,6 +396,8 @@ begin
when
REFORMAT_ADDRESS
=>
-- Reformat address according to the mode (A16, A24, A32)
-- FIXME: not needed if ADEM are correctly reduced to not compare
-- MSBs of A16 or A24 addresses.
case
s_addressingType
is
when
A16
=>
s_ADDRlatched
(
31
downto
16
)
<=
(
others
=>
'0'
);
-- A16
...
...
@@ -455,7 +460,20 @@ begin
s_transferActive
<=
'1'
;
if
s_DS_latch_count
=
0
then
s_mainFSMstate
<=
CHECK_TRANSFER_TYPE
;
-- Read DS (which is delayed to avoid metastability).
s_DSlatched
<=
VME_DS_n_i
;
-- Read DATA (which are stable)
s_locDataIn
(
63
downto
33
)
<=
VME_ADDR_i
;
s_locDataIn
(
32
)
<=
VME_LWORD_n_i
;
if
s_LWORDlatched_n
=
'1'
and
s_ADDRlatched
(
1
)
=
'0'
then
-- Word/byte access with A1=0
s_locDataIn
(
31
downto
16
)
<=
VME_DATA_i
(
15
downto
0
);
s_locDataIn
(
15
downto
0
)
<=
VME_DATA_i
(
15
downto
0
);
else
s_locDataIn
(
31
downto
0
)
<=
VME_DATA_i
;
end
if
;
else
s_mainFSMstate
<=
LATCH_DS
;
s_DS_latch_count
<=
s_DS_latch_count
-
1
;
...
...
@@ -468,15 +486,11 @@ begin
s_dataPhase
<=
s_dataPhase
;
s_transferActive
<=
'1'
;
-- Translate DS+LWORD+
MBLT+AS
to WB byte selects
-- Translate DS+LWORD+
ADDR
to WB byte selects
if
s_LWORDlatched_n
=
'0'
then
if
s_transferType
=
MBLT
then
s_sel
<=
"11111111"
;
s_sel
<=
"1111"
;
else
s_sel
<=
"00001111"
;
end
if
;
else
s_sel
<=
"00000000"
;
s_sel
<=
"0000"
;
case
s_ADDRlatched
(
1
)
is
when
'0'
=>
s_sel
(
3
downto
2
)
<=
not
s_DSlatched
;
...
...
@@ -745,22 +759,6 @@ begin
-- Data Handler Process
------------------------------------------------------------------------------
-- This process aligns the VME data input in the lsb
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
s_locDataIn
(
63
downto
33
)
<=
VME_ADDR_i
;
s_locDataIn
(
32
)
<=
VME_LWORD_n_i
;
if
s_LWORDlatched_n
=
'1'
and
s_ADDRlatched
(
1
)
=
'0'
then
-- Word/byte access with A1=0
s_locDataIn
(
31
downto
16
)
<=
VME_DATA_i
(
15
downto
0
);
s_locDataIn
(
15
downto
0
)
<=
VME_DATA_i
(
15
downto
0
);
else
s_locDataIn
(
31
downto
0
)
<=
VME_DATA_i
;
end
if
;
end
if
;
end
process
;
gen_swapper_ena
:
if
c_SWAPPER_EN
generate
-- Swap the data during read or write operation
-- sel= 000 --> No swap
...
...
@@ -808,8 +806,8 @@ begin
reset_i
=>
s_wbMaster_rst
,
BERRcondition_i
=>
s_BERRcondition
,
sel_i
=>
s_sel
,
locDataInSwap_i
=>
s_locDataInSwap
,
locDataOut_o
=>
s_locDataOutWb
,
locDataInSwap_i
=>
s_locDataInSwap
(
31
downto
0
)
,
locDataOut_o
=>
s_locDataOutWb
(
31
downto
0
)
,
rel_locAddr_i
=>
s_locAddr
,
memAckWb_o
=>
s_AckWb
,
err_o
=>
s_err
,
...
...
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @
d1683381
...
...
@@ -361,8 +361,8 @@ package vme64x_pack is
cardSel_i
:
in
std_logic
;
reset_i
:
in
std_logic
;
BERRcondition_i
:
in
std_logic
;
sel_i
:
in
std_logic_vector
(
7
downto
0
);
locDataInSwap_i
:
in
std_logic_vector
(
63
downto
0
);
sel_i
:
in
std_logic_vector
(
3
downto
0
);
locDataInSwap_i
:
in
std_logic_vector
(
31
downto
0
);
rel_locAddr_i
:
in
std_logic_vector
(
31
downto
0
);
RW_i
:
in
std_logic
;
stall_i
:
in
std_logic
;
...
...
@@ -370,7 +370,7 @@ package vme64x_pack is
err_i
:
in
std_logic
;
wbData_i
:
in
std_logic_vector
(
g_WB_DATA_WIDTH
-1
downto
0
);
memAckWB_i
:
in
std_logic
;
locDataOut_o
:
out
std_logic_vector
(
63
downto
0
);
locDataOut_o
:
out
std_logic_vector
(
31
downto
0
);
memAckWb_o
:
out
std_logic
;
err_o
:
out
std_logic
;
rty_o
:
out
std_logic
;
...
...
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