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VME64x core
Commit c8c252f8 authored by Tristan Gingold's avatar Tristan Gingold
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Fix style (lines too long)

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hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @ c8c252f8
...@@ -475,7 +475,7 @@ begin ...@@ -475,7 +475,7 @@ begin
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Output -- Output
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
VME_IRQ_o <= not s_VME_IRQ_n_o; -- The buffers will invert again the logic level VME_IRQ_o <= not s_VME_IRQ_n_o; -- The buffers will invert again the signal
irq_ack_o <= s_irq_ack; irq_ack_o <= s_irq_ack;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
......
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
View file @ c8c252f8
...@@ -207,16 +207,17 @@ architecture rtl of VME_CR_CSR_Space is ...@@ -207,16 +207,17 @@ architecture rtl of VME_CR_CSR_Space is
signal s_cram_we : std_logic; signal s_cram_we : std_logic;
-- Addresses -- Addresses
constant c_BEG_CR : unsigned(18 downto 2) := to_unsigned(16#00000#/4, 17); subtype crcsr_addr is unsigned(18 downto 2);
constant c_END_CR : unsigned(18 downto 2) := to_unsigned(16#00fff#/4, 17); constant c_BEG_CR : crcsr_addr := to_unsigned(16#00000#/4, 17);
constant c_BEG_CSR : unsigned(18 downto 2) := to_unsigned(16#7ff60#/4, 17); constant c_END_CR : crcsr_addr := to_unsigned(16#00fff#/4, 17);
constant c_END_CSR : unsigned(18 downto 2) := to_unsigned(16#7ffff#/4, 17); constant c_BEG_CSR : crcsr_addr := to_unsigned(16#7ff60#/4, 17);
constant c_BEG_USER_CR : unsigned(18 downto 2) := unsigned(g_BEG_USER_CR(18 downto 2)); constant c_END_CSR : crcsr_addr := to_unsigned(16#7ffff#/4, 17);
constant c_END_USER_CR : unsigned(18 downto 2) := unsigned(g_END_USER_CR(18 downto 2)); constant c_BEG_USER_CR : crcsr_addr := unsigned(g_BEG_USER_CR(18 downto 2));
constant c_BEG_USER_CSR : unsigned(18 downto 2) := unsigned(g_BEG_USER_CSR(18 downto 2)); constant c_END_USER_CR : crcsr_addr := unsigned(g_END_USER_CR(18 downto 2));
constant c_END_USER_CSR : unsigned(18 downto 2) := unsigned(g_END_USER_CSR(18 downto 2)); constant c_BEG_USER_CSR : crcsr_addr := unsigned(g_BEG_USER_CSR(18 downto 2));
constant c_BEG_CRAM : unsigned(18 downto 2) := unsigned(g_BEG_CRAM(18 downto 2)); constant c_END_USER_CSR : crcsr_addr := unsigned(g_END_USER_CSR(18 downto 2));
constant c_END_CRAM : unsigned(18 downto 2) := unsigned(g_END_CRAM(18 downto 2)); constant c_BEG_CRAM : crcsr_addr := unsigned(g_BEG_CRAM(18 downto 2));
constant c_END_CRAM : crcsr_addr := unsigned(g_END_CRAM(18 downto 2));
constant c_BAR_REG : integer := 16#7ffff#/4; constant c_BAR_REG : integer := 16#7ffff#/4;
constant c_BIT_SET_REG : integer := 16#7fffb#/4; constant c_BIT_SET_REG : integer := 16#7fffb#/4;
...@@ -258,33 +259,33 @@ architecture rtl of VME_CR_CSR_Space is ...@@ -258,33 +259,33 @@ architecture rtl of VME_CR_CSR_Space is
variable cr : t_cr_array(0 to 511) := (others => x"00"); variable cr : t_cr_array(0 to 511) := (others => x"00");
variable crc : unsigned(7 downto 0) := x"00"; variable crc : unsigned(7 downto 0) := x"00";
begin begin
cr(16#001# to 16#003#) := (x"00", x"03", x"ff"); -- Length of CR (excluding checksum) cr(16#001# to 16#003#) := (x"00", x"03", x"ff"); -- Length of CR
cr(16#004#) := x"81"; -- CR data access width cr(16#004#) := x"81"; -- CR DAW
cr(16#005#) := x"81"; -- CSR data access width cr(16#005#) := x"81"; -- CSR DAW
cr(16#006#) := x"02"; -- CR/CSR space specification ID cr(16#006#) := x"02"; -- CR/CSR spec id
cr(16#007#) := x"43"; -- ASCII "C" cr(16#007#) := x"43"; -- ASCII "C"
cr(16#008#) := x"52"; -- ASCII "R" cr(16#008#) := x"52"; -- ASCII "R"
cr(16#009# to 16#00b#) := f_cr_vec(g_MANUFACTURER_ID); -- Manufacturer ID cr(16#009# to 16#00b#) := f_cr_vec(g_MANUFACTURER_ID); -- Manufacturer ID
cr(16#00c# to 16#00f#) := f_cr_vec(g_BOARD_ID); -- Board ID cr(16#00c# to 16#00f#) := f_cr_vec(g_BOARD_ID); -- Board ID
cr(16#010# to 16#013#) := f_cr_vec(g_REVISION_ID); -- Revision ID cr(16#010# to 16#013#) := f_cr_vec(g_REVISION_ID); -- Revision ID
cr(16#014# to 16#016#) := f_cr_vec(g_ASCII_PTR); -- Pointer to an ASCII string cr(16#014# to 16#016#) := f_cr_vec(g_ASCII_PTR); -- String ptr
cr(16#01f#) := g_PROGRAM_ID; -- Program ID cr(16#01f#) := g_PROGRAM_ID; -- Program ID
cr(16#020# to 16#022#) := f_cr_vec(g_BEG_USER_CR); -- Beg user CR cr(16#020# to 16#022#) := f_cr_vec(g_BEG_USER_CR); -- Beg user CR
cr(16#023# to 16#025#) := f_cr_vec(g_END_USER_CR); -- End user CR cr(16#023# to 16#025#) := f_cr_vec(g_END_USER_CR); -- End user CR
cr(16#026# to 16#028#) := f_cr_vec(g_BEG_CRAM); -- Beg CRAM cr(16#026# to 16#028#) := f_cr_vec(g_BEG_CRAM); -- Beg CRAM
cr(16#029# to 16#02b#) := f_cr_vec(g_END_CRAM); -- End CRAM cr(16#029# to 16#02b#) := f_cr_vec(g_END_CRAM); -- End CRAM
cr(16#02c# to 16#02e#) := f_cr_vec(g_BEG_USER_CSR); -- Beg user CSR cr(16#02c# to 16#02e#) := f_cr_vec(g_BEG_USER_CSR); -- Beg user CSR
cr(16#02f# to 16#031#) := f_cr_vec(g_END_USER_CSR); -- End user CSR cr(16#02f# to 16#031#) := f_cr_vec(g_END_USER_CSR); -- End user CSR
cr(16#032# to 16#034#) := f_cr_vec(g_BEG_SN); -- Beg serial number cr(16#032# to 16#034#) := f_cr_vec(g_BEG_SN); -- Beg serial number
cr(16#035# to 16#037#) := f_cr_vec(g_END_SN); -- End serial number cr(16#035# to 16#037#) := f_cr_vec(g_END_SN); -- End serial number
cr(16#038#) := x"04"; -- Slave characteristics parameter cr(16#038#) := x"04"; -- Slave param
cr(16#039#) := x"00"; -- User-defined slave char. param. cr(16#039#) := x"00"; -- User-defined
cr(16#03d#) := x"0e"; -- Interrupter capabilities cr(16#03d#) := x"0e"; -- Interrupt cap
cr(16#03f#) := x"81"; -- CRAM data access width cr(16#03f#) := x"81"; -- CRAM DAW
for i in 0 to 7 loop for i in 0 to 7 loop
cr(16#040#+i) := g_DAWPR(i); -- Function X DAWPR cr(16#040#+i) := g_DAWPR(i); -- DAWPR
cr(16#048#+i*8 to 16#04f#+i*8) := f_cr_vec(g_AMCAP(i)); -- Function X AMCAP cr(16#048#+i*8 to 16#04f#+i*8) := f_cr_vec(g_AMCAP(i)); -- AMCAP
cr(16#188#+i*4 to 16#18b#+i*4) := f_cr_vec(g_ADEM(i)); -- Function X ADEM cr(16#188#+i*4 to 16#18b#+i*4) := f_cr_vec(g_ADEM(i)); -- ADEM
end loop; end loop;
for i in cr'range loop for i in cr'range loop
crc := crc + unsigned(cr(i)); crc := crc + unsigned(cr(i));
......
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @ c8c252f8
...@@ -71,46 +71,53 @@ package vme64x_pack is ...@@ -71,46 +71,53 @@ package vme64x_pack is
-- AM table. -- AM table.
-- References: -- References:
-- Table 2-3 "Address Modifier Codes" pages 21/22 VME64std ANSI/VITA 1-1994 -- Table 2-3 "Address Modifier Codes" pages 21/22 VME64std ANSI/VITA 1-1994
-- Table 2.4 "Extended Address Modifier Code" page 12 2eSST ANSI/VITA 1.5-2003(R2009) -- Table 2.4 "Extended Address Modifier Code" page 12 2eSST
constant c_AM_A24_S_SUP : std_logic_vector(5 downto 0) := "111101"; -- 0x3d -- ANSI/VITA 1.5-2003(R2009)
constant c_AM_A24_S : std_logic_vector(5 downto 0) := "111001"; -- 0x39 subtype am_vec_type is std_logic_vector(5 downto 0);
constant c_AM_A24_BLT : std_logic_vector(5 downto 0) := "111011"; -- 0x3b constant c_AM_A24_S_SUP : am_vec_type := "111101"; -- 0x3d
constant c_AM_A24_BLT_SUP : std_logic_vector(5 downto 0) := "111111"; -- 0x3f constant c_AM_A24_S : am_vec_type := "111001"; -- 0x39
constant c_AM_A24_MBLT : std_logic_vector(5 downto 0) := "111000"; -- 0x38 constant c_AM_A24_BLT : am_vec_type := "111011"; -- 0x3b
constant c_AM_A24_MBLT_SUP : std_logic_vector(5 downto 0) := "111100"; -- 0x3c constant c_AM_A24_BLT_SUP : am_vec_type := "111111"; -- 0x3f
constant c_AM_A24_LCK : std_logic_vector(5 downto 0) := "110010"; -- 0x32 constant c_AM_A24_MBLT : am_vec_type := "111000"; -- 0x38
constant c_AM_CR_CSR : std_logic_vector(5 downto 0) := "101111"; -- 0x2f constant c_AM_A24_MBLT_SUP : am_vec_type := "111100"; -- 0x3c
constant c_AM_A16 : std_logic_vector(5 downto 0) := "101001"; -- 0x29 constant c_AM_A24_LCK : am_vec_type := "110010"; -- 0x32
constant c_AM_A16_SUP : std_logic_vector(5 downto 0) := "101101"; -- 0x2d constant c_AM_CR_CSR : am_vec_type := "101111"; -- 0x2f
constant c_AM_A16_LCK : std_logic_vector(5 downto 0) := "101100"; -- 0x2c constant c_AM_A16 : am_vec_type := "101001"; -- 0x29
constant c_AM_A32 : std_logic_vector(5 downto 0) := "001001"; -- 0x09 constant c_AM_A16_SUP : am_vec_type := "101101"; -- 0x2d
constant c_AM_A32_SUP : std_logic_vector(5 downto 0) := "001101"; -- 0x0d constant c_AM_A16_LCK : am_vec_type := "101100"; -- 0x2c
constant c_AM_A32_BLT : std_logic_vector(5 downto 0) := "001011"; -- 0x0b constant c_AM_A32 : am_vec_type := "001001"; -- 0x09
constant c_AM_A32_BLT_SUP : std_logic_vector(5 downto 0) := "001111"; -- 0x0f constant c_AM_A32_SUP : am_vec_type := "001101"; -- 0x0d
constant c_AM_A32_MBLT : std_logic_vector(5 downto 0) := "001000"; -- 0x08 constant c_AM_A32_BLT : am_vec_type := "001011"; -- 0x0b
constant c_AM_A32_MBLT_SUP : std_logic_vector(5 downto 0) := "001100"; -- 0x0c constant c_AM_A32_BLT_SUP : am_vec_type := "001111"; -- 0x0f
constant c_AM_A32_LCK : std_logic_vector(5 downto 0) := "000101"; -- 0x05 constant c_AM_A32_MBLT : am_vec_type := "001000"; -- 0x08
constant c_AM_A64 : std_logic_vector(5 downto 0) := "000001"; -- 0x01 constant c_AM_A32_MBLT_SUP : am_vec_type := "001100"; -- 0x0c
constant c_AM_A64_BLT : std_logic_vector(5 downto 0) := "000011"; -- 0x03 constant c_AM_A32_LCK : am_vec_type := "000101"; -- 0x05
constant c_AM_A64_MBLT : std_logic_vector(5 downto 0) := "000000"; -- 0x00 constant c_AM_A64 : am_vec_type := "000001"; -- 0x01
constant c_AM_A64_LCK : std_logic_vector(5 downto 0) := "000100"; -- 0x04 constant c_AM_A64_BLT : am_vec_type := "000011"; -- 0x03
constant c_AM_2EVME_6U : std_logic_vector(5 downto 0) := "100000"; -- 0x20 constant c_AM_A64_MBLT : am_vec_type := "000000"; -- 0x00
constant c_AM_2EVME_3U : std_logic_vector(5 downto 0) := "100001"; -- 0x21 constant c_AM_A64_LCK : am_vec_type := "000100"; -- 0x04
constant c_AM_2EVME_6U : am_vec_type := "100000"; -- 0x20
constant c_AM_2EVME_3U : am_vec_type := "100001"; -- 0x21
constant c_AM_A32_2EVME : std_logic_vector(7 downto 0) := "00000001"; -- 0x01 subtype xam_vec_type is std_logic_vector(7 downto 0);
constant c_AM_A64_2EVME : std_logic_vector(7 downto 0) := "00000010"; -- 0x02 constant c_AM_A32_2EVME : xam_vec_type := "00000001"; -- 0x01
constant c_AM_A32_2ESST : std_logic_vector(7 downto 0) := "00010001"; -- 0x11 constant c_AM_A64_2EVME : xam_vec_type := "00000010"; -- 0x02
constant c_AM_A64_2ESST : std_logic_vector(7 downto 0) := "00010010"; -- 0x12 constant c_AM_A32_2ESST : xam_vec_type := "00010001"; -- 0x11
constant c_AM_A64_2ESST : xam_vec_type := "00010010"; -- 0x12
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Types -- Types
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- CR/CSR parameter arrays -- CR/CSR parameter arrays
type t_adem_array is array (integer range <>) of std_logic_vector( 31 downto 0); type t_adem_array is
type t_ader_array is array (integer range <>) of std_logic_vector( 31 downto 0); array (integer range <>) of std_logic_vector( 31 downto 0);
type t_amcap_array is array (integer range <>) of std_logic_vector( 63 downto 0); type t_ader_array is
type t_dawpr_array is array (integer range <>) of std_logic_vector( 7 downto 0); array (integer range <>) of std_logic_vector( 31 downto 0);
type t_amcap_array is
array (integer range <>) of std_logic_vector( 63 downto 0);
type t_dawpr_array is
array (integer range <>) of std_logic_vector( 7 downto 0);
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Components -- Components
...@@ -135,30 +142,31 @@ package vme64x_pack is ...@@ -135,30 +142,31 @@ package vme64x_pack is
g_END_USER_CSR : std_logic_vector(23 downto 0) := x"07ff5f"; g_END_USER_CSR : std_logic_vector(23 downto 0) := x"07ff5f";
g_BEG_SN : std_logic_vector(23 downto 0) := x"000000"; g_BEG_SN : std_logic_vector(23 downto 0) := x"000000";
g_END_SN : std_logic_vector(23 downto 0) := x"000000"; g_END_SN : std_logic_vector(23 downto 0) := x"000000";
g_F0_ADEM : std_logic_vector( 31 downto 0) := x"ff000000";
g_F0_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_0000ff00"; g_F0_ADEM : std_logic_vector( 31 downto 0) := x"ff000000";
g_F0_DAWPR : std_logic_vector( 7 downto 0) := x"84"; g_F0_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_0000ff00";
g_F1_ADEM : std_logic_vector( 31 downto 0) := x"fff80000"; g_F0_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F1_AMCAP : std_logic_vector( 63 downto 0) := x"ff000000_00000000"; g_F1_ADEM : std_logic_vector( 31 downto 0) := x"fff80000";
g_F1_DAWPR : std_logic_vector( 7 downto 0) := x"84"; g_F1_AMCAP : std_logic_vector( 63 downto 0) := x"ff000000_00000000";
g_F2_ADEM : std_logic_vector( 31 downto 0) := x"00000000"; g_F1_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F2_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000"; g_F2_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F2_DAWPR : std_logic_vector( 7 downto 0) := x"84"; g_F2_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F3_ADEM : std_logic_vector( 31 downto 0) := x"00000000"; g_F2_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F3_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000"; g_F3_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F3_DAWPR : std_logic_vector( 7 downto 0) := x"84"; g_F3_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F4_ADEM : std_logic_vector( 31 downto 0) := x"00000000"; g_F3_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F4_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000"; g_F4_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F4_DAWPR : std_logic_vector( 7 downto 0) := x"84"; g_F4_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F5_ADEM : std_logic_vector( 31 downto 0) := x"00000000"; g_F4_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F5_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000"; g_F5_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F5_DAWPR : std_logic_vector( 7 downto 0) := x"84"; g_F5_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F6_ADEM : std_logic_vector( 31 downto 0) := x"00000000"; g_F5_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F6_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000"; g_F6_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F6_DAWPR : std_logic_vector( 7 downto 0) := x"84"; g_F6_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F7_ADEM : std_logic_vector( 31 downto 0) := x"00000000"; g_F6_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F7_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000"; g_F7_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F7_DAWPR : std_logic_vector( 7 downto 0) := x"84" g_F7_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F7_DAWPR : std_logic_vector( 7 downto 0) := x"84"
); );
port ( port (
clk_i : in std_logic; clk_i : in std_logic;
......
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