Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
V
VME64x core
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
VME64x core
Commits
c0affb7f
Commit
c0affb7f
authored
Nov 30, 2017
by
Tristan Gingold
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Remove g_decoder extractors, simplify a bit the code.
parent
cfc5b68e
Show whitespace changes
Inline
Side-by-side
Showing
4 changed files
with
17 additions
and
48 deletions
+17
-48
vme64x_pkg.vhd
hdl/rtl/vme64x_pkg.vhd
+0
-6
vme_cr_csr_space.vhd
hdl/rtl/vme_cr_csr_space.vhd
+9
-11
vme_funct_match.vhd
hdl/rtl/vme_funct_match.vhd
+4
-5
xvme64x_core.vhd
hdl/rtl/xvme64x_core.vhd
+4
-26
No files found.
hdl/rtl/vme64x_pkg.vhd
View file @
c0affb7f
...
@@ -117,14 +117,8 @@ package vme64x_pkg is
...
@@ -117,14 +117,8 @@ package vme64x_pkg is
-- CR/CSR parameter arrays
-- CR/CSR parameter arrays
subtype
t_vme_func_index
is
natural
range
0
to
7
;
subtype
t_vme_func_index
is
natural
range
0
to
7
;
type
t_adem_array
is
array
(
t_vme_func_index
range
<>
)
of
std_logic_vector
(
31
downto
0
);
type
t_ader_array
is
type
t_ader_array
is
array
(
t_vme_func_index
range
<>
)
of
std_logic_vector
(
31
downto
0
);
array
(
t_vme_func_index
range
<>
)
of
std_logic_vector
(
31
downto
0
);
type
t_amcap_array
is
array
(
t_vme_func_index
range
<>
)
of
std_logic_vector
(
63
downto
0
);
type
t_dawpr_array
is
array
(
t_vme_func_index
range
<>
)
of
std_logic_vector
(
7
downto
0
);
type
t_vme64x_in
is
record
type
t_vme64x_in
is
record
as_n
:
std_logic
;
as_n
:
std_logic
;
...
...
hdl/rtl/vme_cr_csr_space.vhd
View file @
c0affb7f
...
@@ -122,10 +122,7 @@ entity vme_cr_csr_space is
...
@@ -122,10 +122,7 @@ entity vme_cr_csr_space is
g_END_USER_CSR
:
std_logic_vector
(
23
downto
0
);
g_END_USER_CSR
:
std_logic_vector
(
23
downto
0
);
g_BEG_SN
:
std_logic_vector
(
23
downto
0
);
g_BEG_SN
:
std_logic_vector
(
23
downto
0
);
g_END_SN
:
std_logic_vector
(
23
downto
0
);
g_END_SN
:
std_logic_vector
(
23
downto
0
);
g_ADEM
:
t_adem_array
(
0
to
7
);
g_DECODER
:
t_vme64x_decoder_arr
);
g_AMCAP
:
t_amcap_array
(
0
to
7
);
g_DAWPR
:
t_dawpr_array
(
0
to
7
)
);
port
(
port
(
clk_i
:
in
std_logic
;
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
...
@@ -149,8 +146,7 @@ entity vme_cr_csr_space is
...
@@ -149,8 +146,7 @@ entity vme_cr_csr_space is
user_cr_addr_o
:
out
std_logic_vector
(
18
downto
2
);
user_cr_addr_o
:
out
std_logic_vector
(
18
downto
2
);
user_cr_data_i
:
in
std_logic_vector
(
7
downto
0
);
user_cr_data_i
:
in
std_logic_vector
(
7
downto
0
);
ader_o
:
out
t_ader_array
ader_o
:
out
t_ader_array
);
);
end
vme_cr_csr_space
;
end
vme_cr_csr_space
;
architecture
rtl
of
vme_cr_csr_space
is
architecture
rtl
of
vme_cr_csr_space
is
...
@@ -275,9 +271,9 @@ architecture rtl of vme_cr_csr_space is
...
@@ -275,9 +271,9 @@ architecture rtl of vme_cr_csr_space is
cr
(
16
#
03
d
#
)
:
=
x"0e"
;
-- Interrupt cap
cr
(
16
#
03
d
#
)
:
=
x"0e"
;
-- Interrupt cap
cr
(
16
#
03
f
#
)
:
=
x"81"
;
-- CRAM DAW
cr
(
16
#
03
f
#
)
:
=
x"81"
;
-- CRAM DAW
for
i
in
0
to
7
loop
for
i
in
0
to
7
loop
cr
(
16
#
040
#
+
i
)
:
=
g_
DAWPR
(
i
);
-- DAWPR
cr
(
16
#
040
#
+
i
)
:
=
g_
decoder
(
i
)
.
dawpr
;
cr
(
16
#
048
#
+
i
*
8
to
16
#
04
f
#
+
i
*
8
)
:
=
f_cr_vec
(
g_
AMCAP
(
i
));
-- AMCAP
cr
(
16
#
048
#
+
i
*
8
to
16
#
04
f
#
+
i
*
8
)
:
=
f_cr_vec
(
g_
decoder
(
i
)
.
amcap
);
cr
(
16
#
188
#
+
i
*
4
to
16
#
18
b
#
+
i
*
4
)
:
=
f_cr_vec
(
g_
ADEM
(
i
));
-- ADEM
cr
(
16
#
188
#
+
i
*
4
to
16
#
18
b
#
+
i
*
4
)
:
=
f_cr_vec
(
g_
decoder
(
i
)
.
adem
);
end
loop
;
end
loop
;
for
i
in
cr
'range
loop
for
i
in
cr
'range
loop
crc
:
=
crc
+
unsigned
(
cr
(
i
));
crc
:
=
crc
+
unsigned
(
cr
(
i
));
...
@@ -438,9 +434,11 @@ begin
...
@@ -438,9 +434,11 @@ begin
module_enable_o
<=
s_reg_bit_reg
(
c_ENABLE_BIT
);
module_enable_o
<=
s_reg_bit_reg
(
c_ENABLE_BIT
);
module_reset_o
<=
s_reg_bit_reg
(
c_RESET_BIT
);
module_reset_o
<=
s_reg_bit_reg
(
c_RESET_BIT
);
-- Only keep ADER bits that are used for comparison. Save a little bit of
-- resources.
gen_ader_o
:
for
i
in
s_reg_ader
'range
generate
gen_ader_o
:
for
i
in
s_reg_ader
'range
generate
ader_o
(
i
)
<=
ader_o
(
i
)
<=
s_reg_ader
(
i
)
and
((
g_
ADEM
(
i
)
and
c_ADEM_MASK
)
or
c_ADER_MASK
);
s_reg_ader
(
i
)
and
((
g_
decoder
(
i
)
.
adem
and
c_ADEM_MASK
)
or
c_ADER_MASK
);
end
generate
;
end
generate
;
-- Read
-- Read
...
@@ -453,7 +451,7 @@ begin
...
@@ -453,7 +451,7 @@ begin
if
idx
<=
ader_o
'high
then
if
idx
<=
ader_o
'high
then
v_byte
:
=
3
-
to_integer
(
s_addr
(
3
downto
2
));
v_byte
:
=
3
-
to_integer
(
s_addr
(
3
downto
2
));
ader
:
=
s_reg_ader
(
idx
)
ader
:
=
s_reg_ader
(
idx
)
and
((
g_
ADEM
(
idx
)
and
c_ADEM_MASK
)
or
c_ADER_MASK
);
and
((
g_
decoder
(
idx
)
.
adem
and
c_ADEM_MASK
)
or
c_ADER_MASK
);
s_csr_data
<=
ader
(
8
*
v_byte
+
7
downto
8
*
v_byte
);
s_csr_data
<=
ader
(
8
*
v_byte
+
7
downto
8
*
v_byte
);
end
if
;
end
if
;
end
Get_ADER
;
end
Get_ADER
;
...
...
hdl/rtl/vme_funct_match.vhd
View file @
c0affb7f
...
@@ -38,8 +38,7 @@ use work.vme64x_pkg.all;
...
@@ -38,8 +38,7 @@ use work.vme64x_pkg.all;
entity
vme_funct_match
is
entity
vme_funct_match
is
generic
(
generic
(
g_ADEM
:
t_adem_array
(
0
to
7
);
g_DECODER
:
t_vme64x_decoder_arr
;
g_AMCAP
:
t_amcap_array
(
0
to
7
);
g_DECODE_AM
:
boolean
g_DECODE_AM
:
boolean
);
);
port
(
port
(
...
@@ -78,14 +77,14 @@ begin
...
@@ -78,14 +77,14 @@ begin
gen_match_loop
:
for
i
in
ader_i
'range
generate
gen_match_loop
:
for
i
in
ader_i
'range
generate
-- True in case of match
-- True in case of match
s_function
(
i
)
<=
s_function
(
i
)
<=
'1'
when
(((
addr_i
(
t_ADEM_M
)
and
g_
ADEM
(
i
)
(
t_ADEM_M
))
'1'
when
(((
addr_i
(
t_ADEM_M
)
and
g_
decoder
(
i
)
.
adem
(
t_ADEM_M
))
=
ader_i
(
i
)(
t_ADEM_M
))
=
ader_i
(
i
)(
t_ADEM_M
))
and
((
am_i
=
ader_i
(
i
)(
t_ADER_AM
))
and
((
am_i
=
ader_i
(
i
)(
t_ADER_AM
))
or
not
g_DECODE_AM
))
or
not
g_DECODE_AM
))
else
'0'
;
else
'0'
;
-- True if the AM part of ADER is enabled by AMCAP
-- True if the AM part of ADER is enabled by AMCAP
s_ader_am_valid
(
i
)
<=
s_ader_am_valid
(
i
)
<=
g_
AMCAP
(
i
)
(
to_integer
(
unsigned
(
ader_i
(
i
)(
t_ADER_AM
))));
g_
decoder
(
i
)
.
amcap
(
to_integer
(
unsigned
(
ader_i
(
i
)(
t_ADER_AM
))));
end
generate
;
end
generate
;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
...
@@ -128,7 +127,7 @@ begin
...
@@ -128,7 +127,7 @@ begin
if
s_function_sel_valid
=
'1'
then
if
s_function_sel_valid
=
'1'
then
mask
:
=
(
others
=>
'0'
);
mask
:
=
(
others
=>
'0'
);
mask
(
t_ADEM_M
)
:
=
g_
ADEM
(
s_function_sel
)
(
t_ADEM_M
);
mask
(
t_ADEM_M
)
:
=
g_
decoder
(
s_function_sel
)
.
adem
(
t_ADEM_M
);
addr_o
<=
addr_i
and
not
mask
;
addr_o
<=
addr_i
and
not
mask
;
decode_sel_o
<=
'1'
;
decode_sel_o
<=
'1'
;
else
else
...
...
hdl/rtl/xvme64x_core.vhd
View file @
c0affb7f
...
@@ -244,30 +244,11 @@ architecture rtl of xvme64x_core is
...
@@ -244,30 +244,11 @@ architecture rtl of xvme64x_core is
signal
s_VME_IACK_n
:
std_logic
;
signal
s_VME_IACK_n
:
std_logic
;
signal
s_VME_IACKIN_n
:
std_logic
;
signal
s_VME_IACKIN_n
:
std_logic
;
-- CR/CSR parameter arrays
constant
c_ADEM
:
t_adem_array
(
0
to
7
)
:
=
(
g_decoder
(
0
)
.
adem
,
g_decoder
(
1
)
.
adem
,
g_decoder
(
2
)
.
adem
,
g_decoder
(
3
)
.
adem
,
g_decoder
(
4
)
.
adem
,
g_decoder
(
5
)
.
adem
,
g_decoder
(
6
)
.
adem
,
g_decoder
(
7
)
.
adem
);
constant
c_AMCAP
:
t_amcap_array
(
0
to
7
)
:
=
(
g_decoder
(
0
)
.
amcap
,
g_decoder
(
1
)
.
amcap
,
g_decoder
(
2
)
.
amcap
,
g_decoder
(
3
)
.
amcap
,
g_decoder
(
4
)
.
amcap
,
g_decoder
(
5
)
.
amcap
,
g_decoder
(
6
)
.
amcap
,
g_decoder
(
7
)
.
amcap
);
constant
c_DAWPR
:
t_dawpr_array
(
0
to
7
)
:
=
(
g_decoder
(
0
)
.
dawpr
,
g_decoder
(
1
)
.
dawpr
,
g_decoder
(
2
)
.
dawpr
,
g_decoder
(
3
)
.
dawpr
,
g_decoder
(
4
)
.
dawpr
,
g_decoder
(
5
)
.
dawpr
,
g_decoder
(
6
)
.
dawpr
,
g_decoder
(
7
)
.
dawpr
);
-- List of supported AM.
-- List of supported AM.
constant
c_AMCAP_ALLOWED
:
std_logic_vector
(
63
downto
0
)
:
=
constant
c_AMCAP_ALLOWED
:
std_logic_vector
(
63
downto
0
)
:
=
(
16
#
3
c
#
to
16
#
3
f
#
=>
'1'
,
-- A24
(
16
#
38
#
to
16
#
3
f
#
=>
'1'
,
-- A24
16
#
38
#
to
16
#
3
b
#
=>
'1'
,
16
#
2
d
#
|
16
#
29
#
=>
'1'
,
-- A16
16
#
2
d
#
|
16
#
29
#
=>
'1'
,
-- A16
16
#
0
c
#
to
16
#
0
f
#
=>
'1'
,
-- A32
16
#
08
#
to
16
#
0
f
#
=>
'1'
,
-- A32
16
#
08
#
to
16
#
0
b
#
=>
'1'
,
others
=>
'0'
);
others
=>
'0'
);
begin
begin
assert
g_CLOCK_PERIOD
>
0
report
"g_CLOCK_PERIOD generic must be set"
assert
g_CLOCK_PERIOD
>
0
report
"g_CLOCK_PERIOD generic must be set"
...
@@ -419,8 +400,7 @@ begin
...
@@ -419,8 +400,7 @@ begin
inst_vme_funct_match
:
entity
work
.
vme_funct_match
inst_vme_funct_match
:
entity
work
.
vme_funct_match
generic
map
(
generic
map
(
g_ADEM
=>
c_ADEM
,
g_decoder
=>
g_decoder
,
g_AMCAP
=>
c_AMCAP
,
g_DECODE_AM
=>
g_DECODE_AM
g_DECODE_AM
=>
g_DECODE_AM
)
)
port
map
(
port
map
(
...
@@ -476,9 +456,7 @@ begin
...
@@ -476,9 +456,7 @@ begin
g_END_USER_CSR
=>
g_END_USER_CSR
,
g_END_USER_CSR
=>
g_END_USER_CSR
,
g_BEG_SN
=>
g_BEG_SN
,
g_BEG_SN
=>
g_BEG_SN
,
g_END_SN
=>
g_END_SN
,
g_END_SN
=>
g_END_SN
,
g_ADEM
=>
c_ADEM
,
g_decoder
=>
g_decoder
g_AMCAP
=>
c_AMCAP
,
g_DAWPR
=>
c_DAWPR
)
)
port
map
(
port
map
(
clk_i
=>
clk_i
,
clk_i
=>
clk_i
,
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment