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VME64x core
Commit b78dfe65 authored by dpedrett's avatar dpedrett
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Top Level used to test the vme64x core on the SVEC board 

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@166 665b4545-5c6b-4c24-801b-41150b02b44b
parent ecaaaece
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Showing with 56 additions and 46 deletions
hdl/boards/svec/rtl/TOP_LEVEL.vhd
View file @ b78dfe65
......@@ -84,10 +84,20 @@ use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.wishbone_pkg.all;
use work.vme64x_pack.all;
use work.genram_pkg.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity TOP_LEVEL is
generic(--WB data width:
g_width : integer := 64; --c_width;
-- WB addr width:
g_addr_width : integer := 11; --c_addr_width;
--CRAM size in the CR/CSR space (bytes):
g_CRAM_SIZE : integer := 1024; --c_CRAM_SIZE;
--My WB slave memory:
g_WB_memory_size : integer := 1024 -- c_SIZE
);
port(
clk_i : in std_logic;
Reset : in std_logic; -- hand reset; button PB1
......@@ -141,17 +151,17 @@ component VME64xCore_Top is
VME_GA_i : in std_logic_vector(5 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_LWORD_n_b_i : in std_logic;
VME_LWORD_n_b_o : out std_logic;
VME_ADDR_b_i : in std_logic_vector(31 downto 1);
VME_ADDR_b_o : out std_logic_vector(31 downto 1);
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_LWORD_n_i : in std_logic;
VME_LWORD_n_o : out std_logic;
VME_ADDR_i : in std_logic_vector(31 downto 1);
VME_ADDR_o : out std_logic_vector(31 downto 1);
VME_DATA_i : in std_logic_vector(31 downto 0);
VME_DATA_o : out std_logic_vector(31 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IRQ_o : out std_logic_vector(6 downto 0);
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
......@@ -172,16 +182,16 @@ component VME64xCore_Top is
WE_o : out std_logic;
-- IRQ Generator
IRQ_i : in std_logic;
INT_ack : out std_logic;
INT_ack_o : out std_logic;
reset_o : out std_logic;
-- for debug:
leds : out std_logic_vector(7 downto 0)
debug : out std_logic_vector(7 downto 0)
);
end component VME64xCore_Top;
component xwb_ram is
generic(
g_size : natural := 256;
g_size : integer := 256;
g_init_file : string := "";
g_must_have_init_file : boolean := true;
g_slave1_interface_mode : t_wishbone_interface_mode;
......@@ -228,26 +238,26 @@ generic(g_width : integer := c_width;
);
end component WB_Bridge;
signal WbDat_i : std_logic_vector(c_width - 1 downto 0);
signal WbDat_o : std_logic_vector(c_width - 1 downto 0);
signal WbAdr_o : std_logic_vector(c_addr_width - 1 downto 0);
signal WbDat_i : std_logic_vector(g_width - 1 downto 0);
signal WbDat_o : std_logic_vector(g_width - 1 downto 0);
signal WbAdr_o : std_logic_vector(g_addr_width - 1 downto 0);
signal WbCyc_o : std_logic;
signal WbErr_i : std_logic;
signal WbRty_i : std_logic;
signal WbSel_o : std_logic_vector(f_div8(c_width) - 1 downto 0);
signal WbSel_o : std_logic_vector(f_div8(g_width) - 1 downto 0);
signal WbStb_o : std_logic;
signal WbAck_i : std_logic;
signal WbWe_o : std_logic;
signal WbStall_i : std_logic;
signal WbIrq_i : std_logic;
signal WbMemDat_i : std_logic_vector(c_width - 1 downto 0);
signal WbMemDat_o : std_logic_vector(c_width - 1 downto 0);
signal WbMemAdr_i : std_logic_vector(c_addr_width - 1 downto 0);
signal WbMemDat_i : std_logic_vector(g_width - 1 downto 0);
signal WbMemDat_o : std_logic_vector(g_width - 1 downto 0);
signal WbMemAdr_i : std_logic_vector(g_addr_width - 1 downto 0);
signal WbMemCyc_i : std_logic;
signal WbMemErr_o : std_logic;
signal WbMemRty_o : std_logic;
signal WbMemSel_i : std_logic_vector(f_div8(c_width) - 1 downto 0);
signal WbMemSel_i : std_logic_vector(f_div8(g_width) - 1 downto 0);
signal WbMemStb_i : std_logic;
signal WbMemAck_o : std_logic;
signal WbMemWe_i : std_logic;
......@@ -274,8 +284,8 @@ begin
Inst_VME64xCore_Top: VME64xCore_Top
generic map(
g_width => c_width,
g_addr_width => c_addr_width
g_width => g_width,
g_addr_width => g_addr_width
)
port map(
-- VME
......@@ -289,13 +299,13 @@ port map(
VME_BERR_o => VME_BERR_o,
VME_DTACK_n_o => VME_DTACK_n_o,
VME_RETRY_n_o => VME_RETRY_n_o,
VME_LWORD_n_b_i => VME_LWORD_n_b,
VME_LWORD_n_b_o => s_VME_LWORD_n_b_o,
VME_ADDR_b_i => VME_ADDR_b,
VME_ADDR_b_o => s_VME_ADDR_b_o,
VME_DATA_b_i => VME_DATA_b,
VME_DATA_b_o => s_VME_DATA_b_o,
VME_IRQ_n_o => VME_IRQ_n_o,
VME_LWORD_n_i => VME_LWORD_n_b,
VME_LWORD_n_o => s_VME_LWORD_n_b_o,
VME_ADDR_i => VME_ADDR_b,
VME_ADDR_o => s_VME_ADDR_b_o,
VME_DATA_i => VME_DATA_b,
VME_DATA_o => s_VME_DATA_b_o,
VME_IRQ_o => VME_IRQ_n_o,
VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_IACK_n_i => VME_IACK_n_i,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
......@@ -320,14 +330,14 @@ port map(
STALL_i => WbStall_i,
--IRQ Generator
IRQ_i => WbIrq_i,
INT_ack => s_INT_ack,
INT_ack_o => s_INT_ack,
reset_o => s_rst,
-- Add by Davide for debug:
leds => leds
debug => leds
);
Inst_xwb_ram: xwb_ram
generic map(g_size => 256,
generic map(g_size => g_WB_memory_size,
g_init_file => "",
g_must_have_init_file => false,
g_slave1_interface_mode => PIPELINED,
......@@ -350,8 +360,8 @@ Inst_xwb_ram: xwb_ram
Inst_WB_Bridge: WB_Bridge
generic map(
g_width => c_width,
g_addr_width => c_addr_width
g_width => g_width,
g_addr_width => g_addr_width
)
port map(
clk_i => clk_in,
......@@ -434,7 +444,7 @@ port map(
port map (
CLKFBOUT => s_fb, -- 1-bit output: PLL_BASE feedback output
-- CLKOUT0 - CLKOUT5: 1-bit (each) output: Clock outputs
CLKOUT0 => clk_in_buf, --clk 80 MHz
CLKOUT0 => clk_in_buf, --clk 100 MHz
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
......
hdl/boards/svec/rtl/WB_Bridge.vhd
View file @ b78dfe65
......@@ -154,8 +154,8 @@ m_sel_o <= sel_i;
m_we_o <= we_i;
----------------------------------------------------------------------
Inst_IRQ_Generator_Top: IRQ_Generator_Top
generic map(g_width => c_width,
g_addr_width => c_addr_width
generic map(g_width => g_width,
g_addr_width => g_addr_width
)
port map(
clk_i => clk_i,
......
hdl/boards/svec/rtl/genram_pkg.vhd
View file @ b78dfe65
......@@ -41,7 +41,7 @@ use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
package genram_pkg is
constant c_SIZE : natural := 1024;
constant c_SIZE : integer := 256;
function f_log2_size (A : natural) return natural;
-- Single-port synchronous RAM
......
hdl/boards/svec/rtl/ram_8bits.vhd
View file @ b78dfe65
......@@ -34,7 +34,7 @@ use work.genram_pkg.all;
--===========================================================================
entity ram_8bits is
generic (
size : natural := c_SIZE
size : integer := c_SIZE
);
Port ( addr : in std_logic_vector (f_log2_size(size)-1 downto 0);
di : in std_logic_vector (7 downto 0);
......
hdl/boards/svec/rtl/spram.vhd
View file @ b78dfe65
......@@ -40,8 +40,8 @@ use work.wishbone_pkg.all;
entity spram is
generic (
-- standard parameters
g_data_width : natural := c_wishbone_data_width;
g_size : natural := c_SIZE;
g_data_width : integer := c_wishbone_data_width;
g_size : integer := c_SIZE;
-- if true, the user can write individual bytes by using bwe_i
g_with_byte_enable : boolean := true; --not used
-- RAM read-on-write conflict resolution. Can be "read_first" (read-then-write)
......@@ -73,7 +73,7 @@ constant c_num_bytes : integer := (g_data_width)/8;
begin
spram: for i in 0 to c_num_bytes-1 generate
ram8bits : entity work.ram_8bits
generic map(size => c_SIZE)
generic map(size => g_size)
port map(addr => a_i,
di => d_i(8*i+7 downto 8*i),
do => q_o(8*i+7 downto 8*i),
......
hdl/boards/svec/rtl/wishbone_pkg.vhd
View file @ b78dfe65
......@@ -7,7 +7,7 @@ library work;
package wishbone_pkg is
constant c_wishbone_address_width : integer := 64;
constant c_wishbone_address_width : integer := 11;
constant c_wishbone_data_width : integer := 64;
subtype t_wishbone_address is
......
hdl/boards/svec/rtl/xwb_ram.vhd
View file @ b78dfe65
......@@ -65,7 +65,7 @@ use work.wishbone_pkg.all;
--===========================================================================
entity xwb_ram is
generic(
g_size : natural := c_SIZE;
g_size : integer := c_SIZE;
g_init_file : string := "";
g_must_have_init_file : boolean := false;
g_slave1_interface_mode : t_wishbone_interface_mode;
......@@ -106,7 +106,7 @@ begin
generic map(
-- standard parameters
g_data_width => c_wishbone_data_width,
g_size => c_SIZE,
g_size => g_size,
g_with_byte_enable => true,
g_init_file => "",
g_addr_conflict_resolution => "read_first"
......@@ -114,7 +114,7 @@ begin
port map(
clk_i => clk_sys_i,
bwe_i => s_bwea,
a_i => slave1_i.adr(f_log2_size(c_SIZE)-1 downto 0),
a_i => slave1_i.adr(f_log2_size(g_size)-1 downto 0),
d_i => slave1_i.dat,
q_o => slave1_o.dat
);
......@@ -136,8 +136,8 @@ begin
s_stall <= '0';
slave1_o.stall <= s_stall;
slave1_o.err <= '0';
slave1_o.rty <= '0';
slave1_o.err <= '0'; --slave1_out.ack;
slave1_o.rty <= '0'; -- '0';
slave1_o.ack <= slave1_out.ack;
end struct;
......
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