Commit abcf3e01 authored by Tristan Gingold's avatar Tristan Gingold

vme_bus: simplify code, move enumeration type declaration to the arch.

parent a80b3d14
This diff is collapsed.
......@@ -113,55 +113,6 @@ package vme64x_pack is
type t_xamcap_array is array (integer range <>) of std_logic_vector(255 downto 0);
type t_dawpr_array is array (integer range <>) of std_logic_vector( 7 downto 0);
type t_typeOfDataTransfer is (
D08_0,
D08_1,
D08_2,
D08_3,
D16_01,
D16_23,
D32,
D64,
TypeError
);
type t_addressingType is (
A24,
A24_BLT,
A24_MBLT,
CR_CSR,
A16,
A32,
A32_BLT,
A32_MBLT,
A64,
A64_BLT,
A64_MBLT,
AM_Error
);
type t_transferType is (
SINGLE,
BLT,
MBLT,
error
);
type t_XAMtype is (
A32_2eVME,
A64_2eVME,
A32_2eSST,
A64_2eSST,
A32_2eSSTb,
A64_2eSSTb,
XAM_error
);
type t_2eType is (
TWOe_VME,
TWOe_SST
);
------------------------------------------------------------------------------
-- Components
------------------------------------------------------------------------------
......
......@@ -218,7 +218,7 @@ architecture behaviour of top_tb is
signal user_csr_we_o : std_logic;
signal user_cr_addr_o : std_logic_vector(18 downto 2);
signal user_cr_data_i : std_logic_vector( 7 downto 0) := (others => '0');
signal function_o : std_logic_vector( 2 downto 0);
signal function_o : std_logic_vector( 3 downto 0);
signal f0_faf_ader_i : std_logic_vector(31 downto 0) := (others => '0');
signal f1_faf_ader_i : std_logic_vector(31 downto 0) := (others => '0');
signal f2_faf_ader_i : std_logic_vector(31 downto 0) := (others => '0');
......
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