Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
V
VME64x core
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
VME64x core
Commits
abcf3e01
Commit
abcf3e01
authored
Sep 14, 2017
by
Tristan Gingold
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
vme_bus: simplify code, move enumeration type declaration to the arch.
parent
a80b3d14
Expand all
Hide whitespace changes
Inline
Side-by-side
Showing
3 changed files
with
117 additions
and
234 deletions
+117
-234
VME_bus.vhd
hdl/vme64x-core/rtl/VME_bus.vhd
+116
-184
vme64x_pack.vhd
hdl/vme64x-core/rtl/vme64x_pack.vhd
+0
-49
top_tb.vhd
hdl/vme64x-core/sim/simple_tb/top_tb.vhd
+1
-1
No files found.
hdl/vme64x-core/rtl/VME_bus.vhd
View file @
abcf3e01
This diff is collapsed.
Click to expand it.
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @
abcf3e01
...
...
@@ -113,55 +113,6 @@ package vme64x_pack is
type
t_xamcap_array
is
array
(
integer
range
<>
)
of
std_logic_vector
(
255
downto
0
);
type
t_dawpr_array
is
array
(
integer
range
<>
)
of
std_logic_vector
(
7
downto
0
);
type
t_typeOfDataTransfer
is
(
D08_0
,
D08_1
,
D08_2
,
D08_3
,
D16_01
,
D16_23
,
D32
,
D64
,
TypeError
);
type
t_addressingType
is
(
A24
,
A24_BLT
,
A24_MBLT
,
CR_CSR
,
A16
,
A32
,
A32_BLT
,
A32_MBLT
,
A64
,
A64_BLT
,
A64_MBLT
,
AM_Error
);
type
t_transferType
is
(
SINGLE
,
BLT
,
MBLT
,
error
);
type
t_XAMtype
is
(
A32_2eVME
,
A64_2eVME
,
A32_2eSST
,
A64_2eSST
,
A32_2eSSTb
,
A64_2eSSTb
,
XAM_error
);
type
t_2eType
is
(
TWOe_VME
,
TWOe_SST
);
------------------------------------------------------------------------------
-- Components
------------------------------------------------------------------------------
...
...
hdl/vme64x-core/sim/simple_tb/top_tb.vhd
View file @
abcf3e01
...
...
@@ -218,7 +218,7 @@ architecture behaviour of top_tb is
signal
user_csr_we_o
:
std_logic
;
signal
user_cr_addr_o
:
std_logic_vector
(
18
downto
2
);
signal
user_cr_data_i
:
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
signal
function_o
:
std_logic_vector
(
2
downto
0
);
signal
function_o
:
std_logic_vector
(
3
downto
0
);
signal
f0_faf_ader_i
:
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
signal
f1_faf_ader_i
:
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
signal
f2_faf_ader_i
:
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment