Commit aa37242a authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

xvme64x_core: made ADEMs for A32 and A24 configurable through generic (WR node…

xvme64x_core: made ADEMs for A32 and A24 configurable through generic (WR node needs more than 0.5 MB window)
parent 199c8e94
...@@ -104,26 +104,29 @@ use work.VME_CR_pack.all; ...@@ -104,26 +104,29 @@ use work.VME_CR_pack.all;
entity VME64xCore_Top is entity VME64xCore_Top is
generic( generic(
-- clock period (ns) -- clock period (ns)
g_clock : integer := c_clk_period; -- 100 MHz g_clock : integer := c_clk_period; -- 100 MHz
--WB data width: --WB data width:
g_wb_data_width : integer := c_width; -- must be 32 or 64 g_wb_data_width : integer := c_width; -- must be 32 or 64
--WB address width: --WB address width:
g_wb_addr_width : integer := c_addr_width; -- 64 or less g_wb_addr_width : integer := c_addr_width; -- 64 or less
-- CRAM -- CRAM
g_cram_size : integer := c_CRAM_SIZE; g_cram_size : integer := c_CRAM_SIZE;
-- Board ID; each board shall have an unique ID. eg: SVEC_ID = 408. -- Board ID; each board shall have an unique ID. eg: SVEC_ID = 408.
-- loc: 0x33, 0x37, 0x3B, 0x3F CR space -- loc: 0x33, 0x37, 0x3B, 0x3F CR space
g_BoardID : integer := c_SVEC_ID; -- 4 bytes: 0x00000198 g_BoardID : integer := c_SVEC_ID; -- 4 bytes: 0x00000198
-- Manufacturer ID: eg the CERN ID is 0x080030 -- Manufacturer ID: eg the CERN ID is 0x080030
-- loc: 0x27, 0x2B, 0x2F CR space -- loc: 0x27, 0x2B, 0x2F CR space
g_ManufacturerID : integer := c_CERN_ID; -- 3 bytes: 0x080030 g_ManufacturerID : integer := c_CERN_ID; -- 3 bytes: 0x080030
-- Revision ID -- Revision ID
-- loc: 0x43, 0x47, 0x4B, 0x4F CR space -- loc: 0x43, 0x47, 0x4B, 0x4F CR space
g_RevisionID : integer := c_RevisionID; -- 4 bytes: 0x00000001 g_RevisionID : integer := c_RevisionID; -- 4 bytes: 0x00000001
-- Program ID: this is the firmware ID -- Program ID: this is the firmware ID
-- loc: 0x7f CR space -- loc: 0x7f CR space
g_ProgramID : integer := 90 -- 1 byte : 0x5a g_ProgramID : integer := 90; -- 1 byte : 0x5a
-- The default values can be found in the vme64x_pack -- The default values can be found in the vme64x_pack;
g_adem_a24 : std_logic_vector(31 downto 0) := x"ff800000";
g_adem_a32 : std_logic_vector(31 downto 0) := x"ff000000"
); );
port( port(
clk_i : in std_logic; clk_i : in std_logic;
...@@ -190,7 +193,22 @@ end VME64xCore_Top; ...@@ -190,7 +193,22 @@ end VME64xCore_Top;
--=========================================================================== --===========================================================================
architecture RTL of VME64xCore_Top is architecture RTL of VME64xCore_Top is
impure function f_setup_window_sizes(cr : t_cr_array) return t_cr_array is
variable tmp : t_cr_array(2**12 downto 0);
begin
tmp := cr;
tmp(16#188#) := g_adem_a32(31 downto 24);
tmp(16#189#) := g_adem_a32(23 downto 16);
tmp(16#18A#) := g_adem_a32(15 downto 8);
tmp(16#18B#) := g_adem_a32(7 downto 0);
tmp(16#18c#) := g_adem_a24(31 downto 24);
tmp(16#18d#) := g_adem_a24(23 downto 16);
tmp(16#18e#) := g_adem_a24(15 downto 8);
tmp(16#18f#) := g_adem_a24(7 downto 0);
return tmp;
end function;
signal s_CRAMdataOut : std_logic_vector(7 downto 0); signal s_CRAMdataOut : std_logic_vector(7 downto 0);
signal s_CRAMaddr : std_logic_vector(f_log2_size(g_cram_size)-1 downto 0); signal s_CRAMaddr : std_logic_vector(f_log2_size(g_cram_size)-1 downto 0);
signal s_CRAMdataIn : std_logic_vector(7 downto 0); signal s_CRAMdataIn : std_logic_vector(7 downto 0);
...@@ -326,9 +344,9 @@ begin ...@@ -326,9 +344,9 @@ begin
g_cram_size => g_cram_size g_cram_size => g_cram_size
) )
port map( port map(
clk_i => clk_i, clk_i => clk_i,
rst_n_i => rst_n_i, rst_n_i => rst_n_i,
reset_o => s_reset, -- asserted when '1' reset_o => s_reset, -- asserted when '1'
-- VME -- VME
VME_RST_n_i => VME_RST_n_oversampled, VME_RST_n_i => VME_RST_n_oversampled,
...@@ -415,7 +433,7 @@ begin ...@@ -415,7 +433,7 @@ begin
-- Interrupter -- Interrupter
Inst_VME_IRQ_Controller : VME_IRQ_Controller Inst_VME_IRQ_Controller : VME_IRQ_Controller
generic map ( generic map (
g_retry_timeout => 62500 -- 1ms timeout g_retry_timeout => 62500 -- 1ms timeout
) )
port map( port map(
clk_i => clk_i, clk_i => clk_i,
...@@ -425,7 +443,7 @@ begin ...@@ -425,7 +443,7 @@ begin
VME_DS_n_i => VME_DS_n_oversampled, VME_DS_n_i => VME_DS_n_oversampled,
VME_ADDR_123_i => VME_ADDR_i(3 downto 1), VME_ADDR_123_i => VME_ADDR_i(3 downto 1),
INT_Level_i => s_INT_Level, INT_Level_i => s_INT_Level,
INT_Vector_i => s_INT_Vector , INT_Vector_i => s_INT_Vector,
INT_Req_i => irq_i, INT_Req_i => irq_i,
VME_IRQ_n_o => s_VME_IRQ_n_o, VME_IRQ_n_o => s_VME_IRQ_n_o,
VME_IACKOUT_n_o => VME_IACKOUT_n_o, VME_IACKOUT_n_o => VME_IACKOUT_n_o,
...@@ -442,7 +460,7 @@ begin ...@@ -442,7 +460,7 @@ begin
generic map( generic map(
g_cram_size => g_cram_size, g_cram_size => g_cram_size,
g_wb_data_width => g_wb_data_width, g_wb_data_width => g_wb_data_width,
g_CRspace => c_cr_array, g_CRspace => f_setup_window_sizes(c_cr_array),
g_BoardID => g_BoardID, g_BoardID => g_BoardID,
g_ManufacturerID => g_ManufacturerID, g_ManufacturerID => g_ManufacturerID,
g_RevisionID => g_RevisionID, g_RevisionID => g_RevisionID,
......
...@@ -40,6 +40,10 @@ use WORK.wishbone_pkg.all; ...@@ -40,6 +40,10 @@ use WORK.wishbone_pkg.all;
use work.vme64x_pack.all; use work.vme64x_pack.all;
entity xvme64x_core is entity xvme64x_core is
generic (
g_adem_a24 : std_logic_vector(31 downto 0) := x"fff80000";
g_adem_a32 : std_logic_vector(31 downto 0) := x"ff000000"
);
port ( port (
clk_i : in std_logic; clk_i : in std_logic;
rst_n_i : in std_logic; rst_n_i : in std_logic;
...@@ -85,7 +89,10 @@ architecture wrapper of xvme64x_core is ...@@ -85,7 +89,10 @@ architecture wrapper of xvme64x_core is
generic ( generic (
g_wb_data_width : integer := 32; g_wb_data_width : integer := 32;
g_wb_addr_width : integer := 64; g_wb_addr_width : integer := 64;
g_CRAM_SIZE : integer := 1024); g_CRAM_SIZE : integer := 1024;
g_adem_a24 : std_logic_vector(31 downto 0);
g_adem_a32 : std_logic_vector(31 downto 0)
);
port ( port (
clk_i : in std_logic; clk_i : in std_logic;
rst_n_i : in std_logic; rst_n_i : in std_logic;
...@@ -136,6 +143,9 @@ architecture wrapper of xvme64x_core is ...@@ -136,6 +143,9 @@ architecture wrapper of xvme64x_core is
begin -- wrapper begin -- wrapper
U_Wrapped_VME : VME64xCore_Top U_Wrapped_VME : VME64xCore_Top
generic map (
g_adem_a32 => g_adem_a32,
g_adem_a24 => g_adem_a24)
port map ( port map (
clk_i => clk_i, clk_i => clk_i,
rst_n_i => rst_n_i, rst_n_i => rst_n_i,
......
...@@ -42,56 +42,109 @@ use WORK.wishbone_pkg.all; ...@@ -42,56 +42,109 @@ use WORK.wishbone_pkg.all;
package xvme64x_core_pkg is package xvme64x_core_pkg is
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Constants declaration -- Types declaration
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
type t_vme64x_in is record
as_n : std_logic;
rst_n : std_logic;
write_n : std_logic;
am : std_logic_vector(5 downto 0);
ds_n : std_logic_vector(1 downto 0);
ga : std_logic_vector(5 downto 0);
bbsy_n : std_logic;
iack_n : std_logic;
iackin_n : std_logic;
end record;
type t_vme64x_out is record
iackout_n : std_logic;
dtack_oe : std_logic;
dtack_n : std_logic;
data_dir : std_logic;
data_oe_n : std_logic;
addr_dir : std_logic;
addr_oe_n : std_logic;
retry_n : std_logic;
retry_oe : std_logic;
berr : std_logic;
irq_n : std_logic_vector(6 downto 0);
end record;
type t_vme64x_bidir is record
lword_n : std_logic;
addr : std_logic_vector(31 downto 1);
data : std_logic_vector(31 downto 0);
end record;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Components declaration -- Components declaration
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
component xvme64x_core component xvme64x_core
port ( generic (
clk_i : in std_logic; g_adem_a24 : std_logic_vector(31 downto 0) := x"ff800000";
rst_n_i : in std_logic; g_adem_a32 : std_logic_vector(31 downto 0) := x"ff000000"
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
VME_AS_n_i : in std_logic; VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic; VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic; VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0); VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0); VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0); VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic; VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic; VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic; VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic; VME_RETRY_OE_o : out std_logic;
VME_LWORD_n_b_i : in std_logic; VME_LWORD_n_b_i : in std_logic;
VME_LWORD_n_b_o : out std_logic; VME_LWORD_n_b_o : out std_logic;
VME_ADDR_b_i : in std_logic_vector(31 downto 1); VME_ADDR_b_i : in std_logic_vector(31 downto 1);
VME_ADDR_b_o : out std_logic_vector(31 downto 1); VME_ADDR_b_o : out std_logic_vector(31 downto 1);
VME_DATA_b_i : in std_logic_vector(31 downto 0); VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0); VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_IRQ_n_o : out std_logic_vector(6 downto 0); VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic; VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic; VME_IACK_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic; VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic; VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic; VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic; VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic; VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic; VME_ADDR_OE_N_o : out std_logic;
master_o : out t_wishbone_master_out; master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in; master_i : in t_wishbone_master_in;
irq_i : in std_logic; irq_i : in std_logic;
irq_ack_o : out std_logic irq_ack_o : out std_logic
); );
end component xvme64x_core; end component xvme64x_core;
component xvme64x_core_structs is
generic (
g_wb_data_width : integer := 32;
g_wb_addr_width : integer := 64;
g_cram_size : integer := 1024;
g_window_size_a24 : std_logic_vector(31 downto 0) := x"00080000";
g_window_size_a32 : std_logic_vector(31 downto 0) := x"00080000");
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
vme_i : in t_vme64x_in;
vme_o : out t_vme64x_out;
vme_b : inout t_vme64x_bidir;
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in;
irq_i : in std_logic;
irq_ack_o : out std_logic);
end component xvme64x_core_structs;
end xvme64x_core_pkg; end xvme64x_core_pkg;
package body xvme64x_core_pkg is package body xvme64x_core_pkg is
end xvme64x_core_pkg; end xvme64x_core_pkg;
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