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VME64x core
Commit a3b2fde3 authored by Tom Levens's avatar Tom Levens
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Normalise all constants and generics to uppercase 

Signed-off-by: Tom Levens's avatarTom Levens <tom.levens@cern.ch>
parent de63753d
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hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @ a3b2fde3
......@@ -111,21 +111,21 @@ use work.vme64x_pack.all;
entity VME64xCore_Top is
generic (
g_clock : integer := c_clk_period; -- Clock period (ns)
g_wb_data_width : integer := c_width; -- WB data width: must be 32 or 64
g_wb_addr_width : integer := c_addr_width; -- WB address width: 64 or less
g_user_csr_ext : boolean := false; -- Use external user CSR
g_CLOCK_PERIOD : integer := c_CLOCK_PERIOD; -- Clock period (ns)
g_WB_DATA_WIDTH : integer := c_DATA_WIDTH; -- WB data width: must be 32 or 64
g_WB_ADDR_WIDTH : integer := c_ADDR_WIDTH; -- WB addr width: 64 or less
g_USER_CSR_EXT : boolean := false; -- Use external user CSR
-- Manufacturer ID: IEEE OUID
-- e.g. CERN is 0x080030
g_manufacturer_id : std_logic_vector(23 downto 0) := c_cern_id;
g_MANUFACTURER_ID : std_logic_vector(23 downto 0) := c_CERN_ID;
-- Board ID: Per manufacturer, each board shall have an unique ID
-- e.g. SVEC = 408 (CERN IDs: http://cern.ch/boardid)
g_board_id : std_logic_vector(31 downto 0) := c_svec_id;
g_BOARD_ID : std_logic_vector(31 downto 0) := c_SVEC_ID;
-- Revision ID: user defined revision code
g_revision_id : std_logic_vector(31 downto 0) := c_revision_id;
g_REVISION_ID : std_logic_vector(31 downto 0) := c_REVISION_ID;
-- Program ID: Defined per AV1:
-- 0x00 = Not used
......@@ -135,71 +135,71 @@ entity VME64xCore_Top is
-- 0x80-0xEF = Reserved for future use
-- 0xF0-0xFE = Reserved for Boot Firmware (P1275)
-- 0xFF = Not to be used
g_program_id : std_logic_vector(7 downto 0) := c_program_id;
g_PROGRAM_ID : std_logic_vector(7 downto 0) := c_PROGRAM_ID;
-- Pointer to a user defined ASCII string
g_ascii_ptr : std_logic_vector(23 downto 0) := x"000000";
g_ASCII_PTR : std_logic_vector(23 downto 0) := x"000000";
-- User CR/CSR, CRAM & serial number pointers
g_beg_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_end_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_BEG_USER_CR : std_logic_vector(23 downto 0) := x"000000";
g_END_USER_CR : std_logic_vector(23 downto 0) := x"000000";
g_beg_cram : std_logic_vector(23 downto 0) := x"001003";
g_end_cram : std_logic_vector(23 downto 0) := x"0013ff";
g_BEG_CRAM : std_logic_vector(23 downto 0) := x"001003";
g_END_CRAM : std_logic_vector(23 downto 0) := x"0013ff";
g_beg_user_csr : std_logic_vector(23 downto 0) := x"07ff33";
g_end_user_csr : std_logic_vector(23 downto 0) := x"07ff5f";
g_BEG_USER_CSR : std_logic_vector(23 downto 0) := x"07ff33";
g_END_USER_CSR : std_logic_vector(23 downto 0) := x"07ff5f";
g_beg_sn : std_logic_vector(23 downto 0) := x"000000";
g_end_sn : std_logic_vector(23 downto 0) := x"000000";
g_BEG_SN : std_logic_vector(23 downto 0) := x"000000";
g_END_SN : std_logic_vector(23 downto 0) := x"000000";
-- Function 0
g_f0_adem : std_logic_vector( 31 downto 0) := x"ff000000";
g_f0_amcap : std_logic_vector( 63 downto 0) := x"00000000_0000bb00";
g_f0_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f0_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_F0_ADEM : std_logic_vector( 31 downto 0) := x"ff000000";
g_F0_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_0000bb00";
g_F0_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F0_DAWPR : std_logic_vector( 7 downto 0) := x"84";
-- Function 1
g_f1_adem : std_logic_vector( 31 downto 0) := x"fff80000";
g_f1_amcap : std_logic_vector( 63 downto 0) := x"bb000000_00000000";
g_f1_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f1_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_F1_ADEM : std_logic_vector( 31 downto 0) := x"fff80000";
g_F1_AMCAP : std_logic_vector( 63 downto 0) := x"bb000000_00000000";
g_F1_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F1_DAWPR : std_logic_vector( 7 downto 0) := x"84";
-- Function 2
g_f2_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f2_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f2_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f2_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_F2_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F2_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F2_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F2_DAWPR : std_logic_vector( 7 downto 0) := x"84";
-- Function 3
g_f3_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f3_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f3_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f3_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_F3_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F3_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F3_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F3_DAWPR : std_logic_vector( 7 downto 0) := x"84";
-- Function 4
g_f4_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f4_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f4_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f4_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_F4_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F4_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F4_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F4_DAWPR : std_logic_vector( 7 downto 0) := x"84";
-- Function 5
g_f5_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f5_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f5_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f5_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_F5_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F5_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F5_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F5_DAWPR : std_logic_vector( 7 downto 0) := x"84";
-- Function 6
g_f6_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f6_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f6_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f6_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_F6_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F6_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F6_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F6_DAWPR : std_logic_vector( 7 downto 0) := x"84";
-- Function 7
g_f7_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f7_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f7_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f7_dawpr : std_logic_vector( 7 downto 0) := x"84"
g_F7_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F7_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F7_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F7_DAWPR : std_logic_vector( 7 downto 0) := x"84"
);
port (
clk_i : in std_logic;
......@@ -240,20 +240,20 @@ entity VME64xCore_Top is
VME_RETRY_OE_o : out std_logic;
-- WishBone
DAT_i : in std_logic_vector(g_wb_data_width-1 downto 0);
DAT_o : out std_logic_vector(g_wb_data_width-1 downto 0);
ADR_o : out std_logic_vector(g_wb_addr_width-1 downto 0);
DAT_i : in std_logic_vector(g_WB_DATA_WIDTH-1 downto 0);
DAT_o : out std_logic_vector(g_WB_DATA_WIDTH-1 downto 0);
ADR_o : out std_logic_vector(g_WB_ADDR_WIDTH-1 downto 0);
CYC_o : out std_logic;
ERR_i : in std_logic;
RTY_i : in std_logic;
SEL_o : out std_logic_vector(g_wb_data_width/8-1 downto 0);
SEL_o : out std_logic_vector(g_WB_DATA_WIDTH/8-1 downto 0);
STB_o : out std_logic;
ACK_i : in std_logic;
WE_o : out std_logic;
STALL_i : in std_logic;
-- User CSR
-- The following signals are used when g_user_csr_ext = true
-- The following signals are used when g_USER_CSR_EXT = true
-- otherwise they are connected to the internal user CSR.
endian_i : in std_logic_vector( 2 downto 0) := (others => '0');
irq_level_i : in std_logic_vector( 7 downto 0) := (others => '0');
......@@ -376,39 +376,39 @@ begin
------------------------------------------------------------------------------
Inst_VME_bus : VME_bus
generic map (
g_clock => g_clock,
g_wb_data_width => g_wb_data_width,
g_wb_addr_width => g_wb_addr_width,
g_beg_user_cr => g_beg_user_cr,
g_end_user_cr => g_end_user_cr,
g_beg_cram => g_beg_cram,
g_end_cram => g_end_cram,
g_beg_user_csr => g_beg_user_csr,
g_end_user_csr => g_end_user_csr,
g_f0_adem => g_f0_adem,
g_f0_amcap => g_f0_amcap,
g_f0_xamcap => g_f0_xamcap,
g_f1_adem => g_f1_adem,
g_f1_amcap => g_f1_amcap,
g_f1_xamcap => g_f1_xamcap,
g_f2_adem => g_f2_adem,
g_f2_amcap => g_f2_amcap,
g_f2_xamcap => g_f2_xamcap,
g_f3_adem => g_f3_adem,
g_f3_amcap => g_f3_amcap,
g_f3_xamcap => g_f3_xamcap,
g_f4_adem => g_f4_adem,
g_f4_amcap => g_f4_amcap,
g_f4_xamcap => g_f4_xamcap,
g_f5_adem => g_f5_adem,
g_f5_amcap => g_f5_amcap,
g_f5_xamcap => g_f5_xamcap,
g_f6_adem => g_f6_adem,
g_f6_amcap => g_f6_amcap,
g_f6_xamcap => g_f6_xamcap,
g_f7_adem => g_f7_adem,
g_f7_amcap => g_f7_amcap,
g_f7_xamcap => g_f7_xamcap
g_CLOCK_PERIOD => g_CLOCK_PERIOD,
g_WB_DATA_WIDTH => g_WB_DATA_WIDTH,
g_WB_ADDR_WIDTH => g_WB_ADDR_WIDTH,
g_BEG_USER_CR => g_BEG_USER_CR,
g_END_USER_CR => g_END_USER_CR,
g_BEG_CRAM => g_BEG_CRAM,
g_END_CRAM => g_END_CRAM,
g_BEG_USER_CSR => g_BEG_USER_CSR,
g_END_USER_CSR => g_END_USER_CSR,
g_F0_ADEM => g_F0_ADEM,
g_F0_AMCAP => g_F0_AMCAP,
g_F0_XAMCAP => g_F0_XAMCAP,
g_F1_ADEM => g_F1_ADEM,
g_F1_AMCAP => g_F1_AMCAP,
g_F1_XAMCAP => g_F1_XAMCAP,
g_F2_ADEM => g_F2_ADEM,
g_F2_AMCAP => g_F2_AMCAP,
g_F2_XAMCAP => g_F2_XAMCAP,
g_F3_ADEM => g_F3_ADEM,
g_F3_AMCAP => g_F3_AMCAP,
g_F3_XAMCAP => g_F3_XAMCAP,
g_F4_ADEM => g_F4_ADEM,
g_F4_AMCAP => g_F4_AMCAP,
g_F4_XAMCAP => g_F4_XAMCAP,
g_F5_ADEM => g_F5_ADEM,
g_F5_AMCAP => g_F5_AMCAP,
g_F5_XAMCAP => g_F5_XAMCAP,
g_F6_ADEM => g_F6_ADEM,
g_F6_AMCAP => g_F6_AMCAP,
g_F6_XAMCAP => g_F6_XAMCAP,
g_F7_ADEM => g_F7_ADEM,
g_F7_AMCAP => g_F7_AMCAP,
g_F7_XAMCAP => g_F7_XAMCAP
)
port map (
clk_i => clk_i,
......@@ -504,11 +504,11 @@ begin
------------------------------------------------------------------------------
Inst_VME_IRQ_Controller : VME_IRQ_Controller
generic map (
g_retry_timeout => 1000000/g_clock -- 1ms timeout
g_RETRY_TIMEOUT => 1000000/g_CLOCK_PERIOD -- 1ms timeout
)
port map (
clk_i => clk_i,
reset_n_i => s_reset_n, -- asserted when low
reset_n_i => s_reset_n, -- asserted when low
VME_IACKIN_n_i => s_VME_IACKIN_n(2),
VME_AS_n_i => s_VME_AS_n(2),
VME_DS_n_i => s_VME_DS_n(5 downto 4),
......@@ -529,51 +529,51 @@ begin
------------------------------------------------------------------------------
Inst_VME_CR_CSR_Space : VME_CR_CSR_Space
generic map (
g_manufacturer_id => g_manufacturer_id,
g_board_id => g_board_id,
g_revision_id => g_revision_id,
g_program_id => g_program_id,
g_ascii_ptr => g_ascii_ptr,
g_beg_user_cr => g_beg_user_cr,
g_end_user_cr => g_end_user_cr,
g_beg_cram => g_beg_cram,
g_end_cram => g_end_cram,
g_beg_user_csr => g_beg_user_csr,
g_end_user_csr => g_end_user_csr,
g_beg_sn => g_beg_sn,
g_end_sn => g_end_sn,
g_f0_adem => g_f0_adem,
g_f0_amcap => g_f0_amcap,
g_f0_xamcap => g_f0_xamcap,
g_f0_dawpr => g_f0_dawpr,
g_f1_adem => g_f1_adem,
g_f1_amcap => g_f1_amcap,
g_f1_xamcap => g_f1_xamcap,
g_f1_dawpr => g_f1_dawpr,
g_f2_adem => g_f2_adem,
g_f2_amcap => g_f2_amcap,
g_f2_xamcap => g_f2_xamcap,
g_f2_dawpr => g_f2_dawpr,
g_f3_adem => g_f3_adem,
g_f3_amcap => g_f3_amcap,
g_f3_xamcap => g_f3_xamcap,
g_f3_dawpr => g_f3_dawpr,
g_f4_adem => g_f4_adem,
g_f4_amcap => g_f4_amcap,
g_f4_xamcap => g_f4_xamcap,
g_f4_dawpr => g_f4_dawpr,
g_f5_adem => g_f5_adem,
g_f5_amcap => g_f5_amcap,
g_f5_xamcap => g_f5_xamcap,
g_f5_dawpr => g_f5_dawpr,
g_f6_adem => g_f6_adem,
g_f6_amcap => g_f6_amcap,
g_f6_xamcap => g_f6_xamcap,
g_f6_dawpr => g_f6_dawpr,
g_f7_adem => g_f7_adem,
g_f7_amcap => g_f7_amcap,
g_f7_xamcap => g_f7_xamcap,
g_f7_dawpr => g_f7_dawpr
g_MANUFACTURER_ID => g_MANUFACTURER_ID,
g_BOARD_ID => g_BOARD_ID,
g_REVISION_ID => g_REVISION_ID,
g_PROGRAM_ID => g_PROGRAM_ID,
g_ASCII_PTR => g_ASCII_PTR,
g_BEG_USER_CR => g_BEG_USER_CR,
g_END_USER_CR => g_END_USER_CR,
g_BEG_CRAM => g_BEG_CRAM,
g_END_CRAM => g_END_CRAM,
g_BEG_USER_CSR => g_BEG_USER_CSR,
g_END_USER_CSR => g_END_USER_CSR,
g_BEG_SN => g_BEG_SN,
g_END_SN => g_END_SN,
g_F0_ADEM => g_F0_ADEM,
g_F0_AMCAP => g_F0_AMCAP,
g_F0_XAMCAP => g_F0_XAMCAP,
g_F0_DAWPR => g_F0_DAWPR,
g_F1_ADEM => g_F1_ADEM,
g_F1_AMCAP => g_F1_AMCAP,
g_F1_XAMCAP => g_F1_XAMCAP,
g_F1_DAWPR => g_F1_DAWPR,
g_F2_ADEM => g_F2_ADEM,
g_F2_AMCAP => g_F2_AMCAP,
g_F2_XAMCAP => g_F2_XAMCAP,
g_F2_DAWPR => g_F2_DAWPR,
g_F3_ADEM => g_F3_ADEM,
g_F3_AMCAP => g_F3_AMCAP,
g_F3_XAMCAP => g_F3_XAMCAP,
g_F3_DAWPR => g_F3_DAWPR,
g_F4_ADEM => g_F4_ADEM,
g_F4_AMCAP => g_F4_AMCAP,
g_F4_XAMCAP => g_F4_XAMCAP,
g_F4_DAWPR => g_F4_DAWPR,
g_F5_ADEM => g_F5_ADEM,
g_F5_AMCAP => g_F5_AMCAP,
g_F5_XAMCAP => g_F5_XAMCAP,
g_F5_DAWPR => g_F5_DAWPR,
g_F6_ADEM => g_F6_ADEM,
g_F6_AMCAP => g_F6_AMCAP,
g_F6_XAMCAP => g_F6_XAMCAP,
g_F6_DAWPR => g_F6_DAWPR,
g_F7_ADEM => g_F7_ADEM,
g_F7_AMCAP => g_F7_AMCAP,
g_F7_XAMCAP => g_F7_XAMCAP,
g_F7_DAWPR => g_F7_DAWPR
)
port map (
clk_i => clk_i,
......@@ -629,10 +629,10 @@ begin
);
-- User CSR space
gen_int_user_csr : if g_user_csr_ext = false generate
gen_int_user_csr : if g_USER_CSR_EXT = false generate
Inst_VME_User_CSR : VME_User_CSR
generic map (
g_wb_data_width => g_wb_data_width
g_WB_DATA_WIDTH => g_WB_DATA_WIDTH
)
port map (
clk_i => clk_i,
......@@ -648,7 +648,7 @@ begin
bytes_i => x"0000"
);
end generate;
gen_ext_user_csr : if g_user_csr_ext = true generate
gen_ext_user_csr : if g_USER_CSR_EXT = true generate
s_user_csr_data_i <= user_csr_data_i;
s_endian <= endian_i;
s_irq_vector <= irq_vector_i;
......
hdl/vme64x-core/rtl/VME_Access_Decode.vhd
View file @ a3b2fde3
......@@ -308,7 +308,7 @@ begin
-- Check if the CR/CSR space is addressed
Confaccess <= '1'
when unsigned(BAR_i) = unsigned(Addr(23 downto 19)) and Am = c_CR_CSR
when unsigned(BAR_i) = unsigned(Addr(23 downto 19)) and Am = c_AM_CR_CSR
else '0';
end Behavioral;
hdl/vme64x-core/rtl/VME_Am_Match.vhd
View file @ a3b2fde3
......@@ -136,7 +136,7 @@ begin
elsif decode = '1' then
for i in AmMatch'range loop
if DFS_i(i) = '1' then
if s_FUNC_ADER(i)(ADER_XAM_MODE) = '0' then
if s_FUNC_ADER(i)(c_ADER_XAM_MODE) = '0' then
if unsigned(s_FUNC_ADER(i)(7 downto 2)) = unsigned(Am) then
AmMatch(i) <= s_amcap_match(i);
else
......@@ -150,7 +150,7 @@ begin
end if;
end if;
else
if s_FUNC_ADER(i)(ADER_XAM_MODE) = '1' then
if s_FUNC_ADER(i)(c_ADER_XAM_MODE) = '1' then
AmMatch(i) <= s_xamcap_match(i) and s_amcap_match(i);
else
AmMatch(i) <= s_amcap_match(i);
......
hdl/vme64x-core/rtl/VME_CRAM.vhd
View file @ a3b2fde3
......@@ -38,8 +38,8 @@ use work.vme64x_pack.all;
entity VME_CRAM is
generic (
g_beg_cram : std_logic_vector(23 downto 0);
g_end_cram : std_logic_vector(23 downto 0)
g_BEG_CRAM : std_logic_vector(23 downto 0);
g_END_CRAM : std_logic_vector(23 downto 0)
);
port (
clk_i : in std_logic;
......@@ -52,7 +52,7 @@ end VME_CRAM;
architecture rtl of VME_CRAM is
type t_cram is array (f_size(g_beg_cram, g_end_cram)-1 downto 0)
type t_cram is array (f_size(g_BEG_CRAM, g_END_CRAM)-1 downto 0)
of std_logic_vector(7 downto 0);
signal s_cram : t_cram;
......
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
View file @ a3b2fde3
......@@ -109,51 +109,51 @@ use work.vme64x_pack.all;
entity VME_CR_CSR_Space is
generic (
g_manufacturer_id : std_logic_vector(23 downto 0);
g_board_id : std_logic_vector(31 downto 0);
g_revision_id : std_logic_vector(31 downto 0);
g_program_id : std_logic_vector(7 downto 0);
g_ascii_ptr : std_logic_vector(23 downto 0);
g_beg_user_cr : std_logic_vector(23 downto 0);
g_end_user_cr : std_logic_vector(23 downto 0);
g_beg_cram : std_logic_vector(23 downto 0);
g_end_cram : std_logic_vector(23 downto 0);
g_beg_user_csr : std_logic_vector(23 downto 0);
g_end_user_csr : std_logic_vector(23 downto 0);
g_beg_sn : std_logic_vector(23 downto 0);
g_end_sn : std_logic_vector(23 downto 0);
g_f0_adem : std_logic_vector( 31 downto 0);
g_f0_amcap : std_logic_vector( 63 downto 0);
g_f0_xamcap : std_logic_vector(255 downto 0);
g_f0_dawpr : std_logic_vector( 7 downto 0);
g_f1_adem : std_logic_vector( 31 downto 0);
g_f1_amcap : std_logic_vector( 63 downto 0);
g_f1_xamcap : std_logic_vector(255 downto 0);
g_f1_dawpr : std_logic_vector( 7 downto 0);
g_f2_adem : std_logic_vector( 31 downto 0);
g_f2_amcap : std_logic_vector( 63 downto 0);
g_f2_xamcap : std_logic_vector(255 downto 0);
g_f2_dawpr : std_logic_vector( 7 downto 0);
g_f3_adem : std_logic_vector( 31 downto 0);
g_f3_amcap : std_logic_vector( 63 downto 0);
g_f3_xamcap : std_logic_vector(255 downto 0);
g_f3_dawpr : std_logic_vector( 7 downto 0);
g_f4_adem : std_logic_vector( 31 downto 0);
g_f4_amcap : std_logic_vector( 63 downto 0);
g_f4_xamcap : std_logic_vector(255 downto 0);
g_f4_dawpr : std_logic_vector( 7 downto 0);
g_f5_adem : std_logic_vector( 31 downto 0);
g_f5_amcap : std_logic_vector( 63 downto 0);
g_f5_xamcap : std_logic_vector(255 downto 0);
g_f5_dawpr : std_logic_vector( 7 downto 0);
g_f6_adem : std_logic_vector( 31 downto 0);
g_f6_amcap : std_logic_vector( 63 downto 0);
g_f6_xamcap : std_logic_vector(255 downto 0);
g_f6_dawpr : std_logic_vector( 7 downto 0);
g_f7_adem : std_logic_vector( 31 downto 0);
g_f7_amcap : std_logic_vector( 63 downto 0);
g_f7_xamcap : std_logic_vector(255 downto 0);
g_f7_dawpr : std_logic_vector( 7 downto 0)
g_MANUFACTURER_ID : std_logic_vector(23 downto 0);
g_BOARD_ID : std_logic_vector(31 downto 0);
g_REVISION_ID : std_logic_vector(31 downto 0);
g_PROGRAM_ID : std_logic_vector(7 downto 0);
g_ASCII_PTR : std_logic_vector(23 downto 0);
g_BEG_USER_CR : std_logic_vector(23 downto 0);
g_END_USER_CR : std_logic_vector(23 downto 0);
g_BEG_CRAM : std_logic_vector(23 downto 0);
g_END_CRAM : std_logic_vector(23 downto 0);
g_BEG_USER_CSR : std_logic_vector(23 downto 0);
g_END_USER_CSR : std_logic_vector(23 downto 0);
g_BEG_SN : std_logic_vector(23 downto 0);
g_END_SN : std_logic_vector(23 downto 0);
g_F0_ADEM : std_logic_vector( 31 downto 0);
g_F0_AMCAP : std_logic_vector( 63 downto 0);
g_F0_XAMCAP : std_logic_vector(255 downto 0);
g_F0_DAWPR : std_logic_vector( 7 downto 0);
g_F1_ADEM : std_logic_vector( 31 downto 0);
g_F1_AMCAP : std_logic_vector( 63 downto 0);
g_F1_XAMCAP : std_logic_vector(255 downto 0);
g_F1_DAWPR : std_logic_vector( 7 downto 0);
g_F2_ADEM : std_logic_vector( 31 downto 0);
g_F2_AMCAP : std_logic_vector( 63 downto 0);
g_F2_XAMCAP : std_logic_vector(255 downto 0);
g_F2_DAWPR : std_logic_vector( 7 downto 0);
g_F3_ADEM : std_logic_vector( 31 downto 0);
g_F3_AMCAP : std_logic_vector( 63 downto 0);
g_F3_XAMCAP : std_logic_vector(255 downto 0);
g_F3_DAWPR : std_logic_vector( 7 downto 0);
g_F4_ADEM : std_logic_vector( 31 downto 0);
g_F4_AMCAP : std_logic_vector( 63 downto 0);
g_F4_XAMCAP : std_logic_vector(255 downto 0);
g_F4_DAWPR : std_logic_vector( 7 downto 0);
g_F5_ADEM : std_logic_vector( 31 downto 0);
g_F5_AMCAP : std_logic_vector( 63 downto 0);
g_F5_XAMCAP : std_logic_vector(255 downto 0);
g_F5_DAWPR : std_logic_vector( 7 downto 0);
g_F6_ADEM : std_logic_vector( 31 downto 0);
g_F6_AMCAP : std_logic_vector( 63 downto 0);
g_F6_XAMCAP : std_logic_vector(255 downto 0);
g_F6_DAWPR : std_logic_vector( 7 downto 0);
g_F7_ADEM : std_logic_vector( 31 downto 0);
g_F7_AMCAP : std_logic_vector( 63 downto 0);
g_F7_XAMCAP : std_logic_vector(255 downto 0);
g_F7_DAWPR : std_logic_vector( 7 downto 0)
);
port (
clk_i : in std_logic;
......@@ -240,27 +240,27 @@ architecture rtl of VME_CR_CSR_Space is
signal s_faf_ader : t_reg_array(0 to 7);
signal s_dfs_adem : t_reg_array(0 to 7);
constant c_adem : t_reg_array(-1 to 7) := (
constant c_ADEM : t_reg_array(-1 to 7) := (
x"00000000",
g_f0_adem, g_f1_adem, g_f2_adem, g_f3_adem,
g_f4_adem, g_f5_adem, g_f6_adem, g_f7_adem
g_F0_ADEM, g_F1_ADEM, g_F2_ADEM, g_F3_ADEM,
g_F4_ADEM, g_F5_ADEM, g_F6_ADEM, g_F7_ADEM
);
signal s_cr_rom : t_cr_array(1023 downto 0) := f_vme_cr_encode(
g_manufacturer_id, g_board_id, g_revision_id, g_program_id,
g_ascii_ptr,
g_beg_user_cr, g_end_user_cr,
g_beg_cram, g_end_cram,
g_beg_user_csr, g_end_user_csr,
g_beg_sn, g_end_sn,
g_f0_adem, g_f0_amcap, g_f0_xamcap, g_f0_dawpr,
g_f1_adem, g_f1_amcap, g_f1_xamcap, g_f1_dawpr,
g_f2_adem, g_f2_amcap, g_f2_xamcap, g_f2_dawpr,
g_f3_adem, g_f3_amcap, g_f3_xamcap, g_f3_dawpr,
g_f4_adem, g_f4_amcap, g_f4_xamcap, g_f4_dawpr,
g_f5_adem, g_f5_amcap, g_f5_xamcap, g_f5_dawpr,
g_f6_adem, g_f6_amcap, g_f6_xamcap, g_f6_dawpr,
g_f7_adem, g_f7_amcap, g_f7_xamcap, g_f7_dawpr
g_MANUFACTURER_ID, g_BOARD_ID, g_REVISION_ID, g_PROGRAM_ID,
g_ASCII_PTR,
g_BEG_USER_CR, g_END_USER_CR,
g_BEG_CRAM, g_END_CRAM,
g_BEG_USER_CSR, g_END_USER_CSR,
g_BEG_SN, g_END_SN,
g_F0_ADEM, g_F0_AMCAP, g_F0_XAMCAP, g_F0_DAWPR,
g_F1_ADEM, g_F1_AMCAP, g_F1_XAMCAP, g_F1_DAWPR,
g_F2_ADEM, g_F2_AMCAP, g_F2_XAMCAP, g_F2_DAWPR,
g_F3_ADEM, g_F3_AMCAP, g_F3_XAMCAP, g_F3_DAWPR,
g_F4_ADEM, g_F4_AMCAP, g_F4_XAMCAP, g_F4_DAWPR,
g_F5_ADEM, g_F5_AMCAP, g_F5_XAMCAP, g_F5_DAWPR,
g_F6_ADEM, g_F6_AMCAP, g_F6_XAMCAP, g_F6_DAWPR,
g_F7_ADEM, g_F7_AMCAP, g_F7_XAMCAP, g_F7_DAWPR
);
begin
......@@ -270,8 +270,8 @@ begin
------------------------------------------------------------------------------
-- Defined CR
------------------------------------------------------------------------------
s_cr_access <= '1' when s_addr >= c_beg_cr(18 downto 2) and
s_addr <= c_end_cr(18 downto 2)
s_cr_access <= '1' when s_addr >= c_BEG_CR(18 downto 2) and
s_addr <= c_END_CR(18 downto 2)
else '0';
process (clk_i)
......@@ -284,8 +284,8 @@ begin
------------------------------------------------------------------------------
-- Defined CSR
------------------------------------------------------------------------------
s_csr_access <= '1' when s_addr >= c_beg_csr(18 downto 2) and
s_addr <= c_end_csr(18 downto 2)
s_csr_access <= '1' when s_addr >= c_BEG_CSR(18 downto 2) and
s_addr <= c_END_CSR(18 downto 2)
else '0';
-- If the crate is not driving the GA lines or the parity is even the BAR
......@@ -310,15 +310,15 @@ begin
else
if we_i = '1' and s_csr_access = '1' then
case s_addr is
when c_addr_bar(18 downto 2) =>
when c_ADDR_BAR(18 downto 2) =>
s_reg_bar <= data_i;
when c_addr_bit_set_reg(18 downto 2) =>
when c_ADDR_BIT_SET_REG(18 downto 2) =>
for i in 0 to 7 loop
s_reg_bit_reg(i) <= s_reg_bit_reg(i) or data_i(i);
end loop;
when c_addr_bit_clr_reg(18 downto 2) =>
when c_ADDR_BIT_CLR_REG(18 downto 2) =>
for i in 0 to 7 loop
s_reg_bit_reg(i) <= s_reg_bit_reg(i) and (not data_i(i));
end loop;
......@@ -326,54 +326,54 @@ begin
s_reg_cram_owner <= x"00";
end if;
when c_addr_cram_owner(18 downto 2) =>
when c_ADDR_CRAM_OWNER(18 downto 2) =>
if s_reg_cram_owner = x"00" then
s_reg_cram_owner <= data_i;
s_reg_bit_reg(2) <= '1';
end if;
when c_addr_usr_set_reg(18 downto 2) =>
when c_ADDR_USR_SET_REG(18 downto 2) =>
for i in 0 to 7 loop
s_reg_usr_bit_reg(i) <= s_reg_usr_bit_reg(i) or data_i(i);
end loop;
when c_addr_usr_clr_reg(18 downto 2) =>
when c_ADDR_USR_CLR_REG(18 downto 2) =>
for i in 0 to 7 loop
s_reg_usr_bit_reg(i) <= s_reg_usr_bit_reg(i) and (not data_i(i));
end loop;
when c_addr_f7_ader_0(18 downto 2) => s_reg_ader(7)( 7 downto 0) <= data_i;
when c_addr_f7_ader_1(18 downto 2) => s_reg_ader(7)(15 downto 8) <= data_i;
when c_addr_f7_ader_2(18 downto 2) => s_reg_ader(7)(23 downto 16) <= data_i;
when c_addr_f7_ader_3(18 downto 2) => s_reg_ader(7)(31 downto 24) <= data_i;
when c_addr_f6_ader_0(18 downto 2) => s_reg_ader(6)( 7 downto 0) <= data_i;
when c_addr_f6_ader_1(18 downto 2) => s_reg_ader(6)(15 downto 8) <= data_i;
when c_addr_f6_ader_2(18 downto 2) => s_reg_ader(6)(23 downto 16) <= data_i;
when c_addr_f6_ader_3(18 downto 2) => s_reg_ader(6)(31 downto 24) <= data_i;
when c_addr_f5_ader_0(18 downto 2) => s_reg_ader(5)( 7 downto 0) <= data_i;
when c_addr_f5_ader_1(18 downto 2) => s_reg_ader(5)(15 downto 8) <= data_i;
when c_addr_f5_ader_2(18 downto 2) => s_reg_ader(5)(23 downto 16) <= data_i;
when c_addr_f5_ader_3(18 downto 2) => s_reg_ader(5)(31 downto 24) <= data_i;
when c_addr_f4_ader_0(18 downto 2) => s_reg_ader(4)( 7 downto 0) <= data_i;
when c_addr_f4_ader_1(18 downto 2) => s_reg_ader(4)(15 downto 8) <= data_i;
when c_addr_f4_ader_2(18 downto 2) => s_reg_ader(4)(23 downto 16) <= data_i;
when c_addr_f4_ader_3(18 downto 2) => s_reg_ader(4)(31 downto 24) <= data_i;
when c_addr_f3_ader_0(18 downto 2) => s_reg_ader(3)( 7 downto 0) <= data_i;
when c_addr_f3_ader_1(18 downto 2) => s_reg_ader(3)(15 downto 8) <= data_i;
when c_addr_f3_ader_2(18 downto 2) => s_reg_ader(3)(23 downto 16) <= data_i;
when c_addr_f3_ader_3(18 downto 2) => s_reg_ader(3)(31 downto 24) <= data_i;
when c_addr_f2_ader_0(18 downto 2) => s_reg_ader(2)( 7 downto 0) <= data_i;
when c_addr_f2_ader_1(18 downto 2) => s_reg_ader(2)(15 downto 8) <= data_i;
when c_addr_f2_ader_2(18 downto 2) => s_reg_ader(2)(23 downto 16) <= data_i;
when c_addr_f2_ader_3(18 downto 2) => s_reg_ader(2)(31 downto 24) <= data_i;
when c_addr_f1_ader_0(18 downto 2) => s_reg_ader(1)( 7 downto 0) <= data_i;
when c_addr_f1_ader_1(18 downto 2) => s_reg_ader(1)(15 downto 8) <= data_i;
when c_addr_f1_ader_2(18 downto 2) => s_reg_ader(1)(23 downto 16) <= data_i;
when c_addr_f1_ader_3(18 downto 2) => s_reg_ader(1)(31 downto 24) <= data_i;
when c_addr_f0_ader_0(18 downto 2) => s_reg_ader(0)( 7 downto 0) <= data_i;
when c_addr_f0_ader_1(18 downto 2) => s_reg_ader(0)(15 downto 8) <= data_i;
when c_addr_f0_ader_2(18 downto 2) => s_reg_ader(0)(23 downto 16) <= data_i;
when c_addr_f0_ader_3(18 downto 2) => s_reg_ader(0)(31 downto 24) <= data_i;
when c_ADDR_F7_ADER_0(18 downto 2) => s_reg_ader(7)( 7 downto 0) <= data_i;
when c_ADDR_F7_ADER_1(18 downto 2) => s_reg_ader(7)(15 downto 8) <= data_i;
when c_ADDR_F7_ADER_2(18 downto 2) => s_reg_ader(7)(23 downto 16) <= data_i;
when c_ADDR_F7_ADER_3(18 downto 2) => s_reg_ader(7)(31 downto 24) <= data_i;
when c_ADDR_F6_ADER_0(18 downto 2) => s_reg_ader(6)( 7 downto 0) <= data_i;
when c_ADDR_F6_ADER_1(18 downto 2) => s_reg_ader(6)(15 downto 8) <= data_i;
when c_ADDR_F6_ADER_2(18 downto 2) => s_reg_ader(6)(23 downto 16) <= data_i;
when c_ADDR_F6_ADER_3(18 downto 2) => s_reg_ader(6)(31 downto 24) <= data_i;
when c_ADDR_F5_ADER_0(18 downto 2) => s_reg_ader(5)( 7 downto 0) <= data_i;
when c_ADDR_F5_ADER_1(18 downto 2) => s_reg_ader(5)(15 downto 8) <= data_i;
when c_ADDR_F5_ADER_2(18 downto 2) => s_reg_ader(5)(23 downto 16) <= data_i;
when c_ADDR_F5_ADER_3(18 downto 2) => s_reg_ader(5)(31 downto 24) <= data_i;
when c_ADDR_F4_ADER_0(18 downto 2) => s_reg_ader(4)( 7 downto 0) <= data_i;
when c_ADDR_F4_ADER_1(18 downto 2) => s_reg_ader(4)(15 downto 8) <= data_i;
when c_ADDR_F4_ADER_2(18 downto 2) => s_reg_ader(4)(23 downto 16) <= data_i;
when c_ADDR_F4_ADER_3(18 downto 2) => s_reg_ader(4)(31 downto 24) <= data_i;
when c_ADDR_F3_ADER_0(18 downto 2) => s_reg_ader(3)( 7 downto 0) <= data_i;
when c_ADDR_F3_ADER_1(18 downto 2) => s_reg_ader(3)(15 downto 8) <= data_i;
when c_ADDR_F3_ADER_2(18 downto 2) => s_reg_ader(3)(23 downto 16) <= data_i;
when c_ADDR_F3_ADER_3(18 downto 2) => s_reg_ader(3)(31 downto 24) <= data_i;
when c_ADDR_F2_ADER_0(18 downto 2) => s_reg_ader(2)( 7 downto 0) <= data_i;
when c_ADDR_F2_ADER_1(18 downto 2) => s_reg_ader(2)(15 downto 8) <= data_i;
when c_ADDR_F2_ADER_2(18 downto 2) => s_reg_ader(2)(23 downto 16) <= data_i;
when c_ADDR_F2_ADER_3(18 downto 2) => s_reg_ader(2)(31 downto 24) <= data_i;
when c_ADDR_F1_ADER_0(18 downto 2) => s_reg_ader(1)( 7 downto 0) <= data_i;
when c_ADDR_F1_ADER_1(18 downto 2) => s_reg_ader(1)(15 downto 8) <= data_i;
when c_ADDR_F1_ADER_2(18 downto 2) => s_reg_ader(1)(23 downto 16) <= data_i;
when c_ADDR_F1_ADER_3(18 downto 2) => s_reg_ader(1)(31 downto 24) <= data_i;
when c_ADDR_F0_ADER_0(18 downto 2) => s_reg_ader(0)( 7 downto 0) <= data_i;
when c_ADDR_F0_ADER_1(18 downto 2) => s_reg_ader(0)(15 downto 8) <= data_i;
when c_ADDR_F0_ADER_2(18 downto 2) => s_reg_ader(0)(23 downto 16) <= data_i;
when c_ADDR_F0_ADER_3(18 downto 2) => s_reg_ader(0)(31 downto 24) <= data_i;
when others => null;
end case;
......@@ -391,14 +391,14 @@ begin
end process;
bar_o <= s_reg_bar(7 downto 3);
f0_ader_o <= s_ader(0) when s_ader(0)(ADER_DFSR) = '0' else (others => '0');
f1_ader_o <= s_ader(1) when s_ader(1)(ADER_DFSR) = '0' else (others => '0');
f2_ader_o <= s_ader(2) when s_ader(2)(ADER_DFSR) = '0' else (others => '0');
f3_ader_o <= s_ader(3) when s_ader(3)(ADER_DFSR) = '0' else (others => '0');
f4_ader_o <= s_ader(4) when s_ader(4)(ADER_DFSR) = '0' else (others => '0');
f5_ader_o <= s_ader(5) when s_ader(5)(ADER_DFSR) = '0' else (others => '0');
f6_ader_o <= s_ader(6) when s_ader(6)(ADER_DFSR) = '0' else (others => '0');
f7_ader_o <= s_ader(7) when s_ader(7)(ADER_DFSR) = '0' else (others => '0');
f0_ader_o <= s_ader(0) when s_ader(0)(c_ADER_DFSR) = '0' else (others => '0');
f1_ader_o <= s_ader(1) when s_ader(1)(c_ADER_DFSR) = '0' else (others => '0');
f2_ader_o <= s_ader(2) when s_ader(2)(c_ADER_DFSR) = '0' else (others => '0');
f3_ader_o <= s_ader(3) when s_ader(3)(c_ADER_DFSR) = '0' else (others => '0');
f4_ader_o <= s_ader(4) when s_ader(4)(c_ADER_DFSR) = '0' else (others => '0');
f5_ader_o <= s_ader(5) when s_ader(5)(c_ADER_DFSR) = '0' else (others => '0');
f6_ader_o <= s_ader(6) when s_ader(6)(c_ADER_DFSR) = '0' else (others => '0');
f7_ader_o <= s_ader(7) when s_ader(7)(c_ADER_DFSR) = '0' else (others => '0');
module_enable_o <= s_reg_bit_reg(4);
vme_sysfail_ena_o <= s_reg_bit_reg(6);
module_reset_o <= s_reg_bit_reg(7);
......@@ -413,13 +413,13 @@ begin
process (s_reg_ader, s_faf_ader, s_dfs_adem)
begin
for i in 0 to 7 loop
if (c_adem(i-1)(ADEM_EFM) = '1' and c_adem(i-1)(ADEM_FAF) = '1') or
(c_adem(i-1)(ADEM_EFM) = '0' and c_adem(i)(ADEM_FAF) = '1')
if (c_ADEM(i-1)(c_ADEM_EFM) = '1' and c_ADEM(i-1)(c_ADEM_FAF) = '1') or
(c_ADEM(i-1)(c_ADEM_EFM) = '0' and c_ADEM(i)(c_ADEM_FAF) = '1')
then
s_ader(i) <= s_faf_ader(i);
elsif (c_adem(i-1)(ADEM_EFM) = '1' and c_adem(i-1)(ADEM_DFS) = '1' and s_reg_ader(i-1)(ADER_DFSR) = '1') then
elsif (c_ADEM(i-1)(c_ADEM_EFM) = '1' and c_ADEM(i-1)(c_ADEM_DFS) = '1' and s_reg_ader(i-1)(c_ADER_DFSR) = '1') then
s_ader(i) <= s_dfs_adem(i);
elsif (c_adem(i-1)(ADEM_EFM) = '0' and c_adem(i)(ADEM_DFS) = '1' and s_reg_ader(i)(ADER_DFSR) = '1') then
elsif (c_ADEM(i-1)(c_ADEM_EFM) = '0' and c_ADEM(i)(c_ADEM_DFS) = '1' and s_reg_ader(i)(c_ADER_DFSR) = '1') then
s_ader(i) <= s_dfs_adem(i)(31 downto 8) & s_reg_ader(i)(7 downto 0);
else
s_ader(i) <= s_reg_ader(i);
......@@ -435,44 +435,44 @@ begin
s_csr_data <= x"ff";
else
case s_addr is
when c_addr_bar(18 downto 2) => s_csr_data <= s_reg_bar;
when c_addr_bit_set_reg(18 downto 2) => s_csr_data <= s_reg_bit_reg;
when c_addr_bit_clr_reg(18 downto 2) => s_csr_data <= s_reg_bit_reg;
when c_addr_cram_owner(18 downto 2) => s_csr_data <= s_reg_cram_owner;
when c_addr_usr_set_reg(18 downto 2) => s_csr_data <= s_reg_usr_bit_reg;
when c_addr_usr_clr_reg(18 downto 2) => s_csr_data <= s_reg_usr_bit_reg;
when c_addr_f7_ader_0(18 downto 2) => s_csr_data <= s_ader(7)( 7 downto 0);
when c_addr_f7_ader_1(18 downto 2) => s_csr_data <= s_ader(7)(15 downto 8);
when c_addr_f7_ader_2(18 downto 2) => s_csr_data <= s_ader(7)(23 downto 16);
when c_addr_f7_ader_3(18 downto 2) => s_csr_data <= s_ader(7)(31 downto 24);
when c_addr_f6_ader_0(18 downto 2) => s_csr_data <= s_ader(6)( 7 downto 0);
when c_addr_f6_ader_1(18 downto 2) => s_csr_data <= s_ader(6)(15 downto 8);
when c_addr_f6_ader_2(18 downto 2) => s_csr_data <= s_ader(6)(23 downto 16);
when c_addr_f6_ader_3(18 downto 2) => s_csr_data <= s_ader(6)(31 downto 24);
when c_addr_f5_ader_0(18 downto 2) => s_csr_data <= s_ader(5)( 7 downto 0);
when c_addr_f5_ader_1(18 downto 2) => s_csr_data <= s_ader(5)(15 downto 8);
when c_addr_f5_ader_2(18 downto 2) => s_csr_data <= s_ader(5)(23 downto 16);
when c_addr_f5_ader_3(18 downto 2) => s_csr_data <= s_ader(5)(31 downto 24);
when c_addr_f4_ader_0(18 downto 2) => s_csr_data <= s_ader(4)( 7 downto 0);
when c_addr_f4_ader_1(18 downto 2) => s_csr_data <= s_ader(4)(15 downto 8);
when c_addr_f4_ader_2(18 downto 2) => s_csr_data <= s_ader(4)(23 downto 16);
when c_addr_f4_ader_3(18 downto 2) => s_csr_data <= s_ader(4)(31 downto 24);
when c_addr_f3_ader_0(18 downto 2) => s_csr_data <= s_ader(3)( 7 downto 0);
when c_addr_f3_ader_1(18 downto 2) => s_csr_data <= s_ader(3)(15 downto 8);
when c_addr_f3_ader_2(18 downto 2) => s_csr_data <= s_ader(3)(23 downto 16);
when c_addr_f3_ader_3(18 downto 2) => s_csr_data <= s_ader(3)(31 downto 24);
when c_addr_f2_ader_0(18 downto 2) => s_csr_data <= s_ader(2)( 7 downto 0);
when c_addr_f2_ader_1(18 downto 2) => s_csr_data <= s_ader(2)(15 downto 8);
when c_addr_f2_ader_2(18 downto 2) => s_csr_data <= s_ader(2)(23 downto 16);
when c_addr_f2_ader_3(18 downto 2) => s_csr_data <= s_ader(2)(31 downto 24);
when c_addr_f1_ader_0(18 downto 2) => s_csr_data <= s_ader(1)( 7 downto 0);
when c_addr_f1_ader_1(18 downto 2) => s_csr_data <= s_ader(1)(15 downto 8);
when c_addr_f1_ader_2(18 downto 2) => s_csr_data <= s_ader(1)(23 downto 16);
when c_addr_f1_ader_3(18 downto 2) => s_csr_data <= s_ader(1)(31 downto 24);
when c_addr_f0_ader_0(18 downto 2) => s_csr_data <= s_ader(0)( 7 downto 0);
when c_addr_f0_ader_1(18 downto 2) => s_csr_data <= s_ader(0)(15 downto 8);
when c_addr_f0_ader_2(18 downto 2) => s_csr_data <= s_ader(0)(23 downto 16);
when c_addr_f0_ader_3(18 downto 2) => s_csr_data <= s_ader(0)(31 downto 24);
when c_ADDR_BAR(18 downto 2) => s_csr_data <= s_reg_bar;
when c_ADDR_BIT_SET_REG(18 downto 2) => s_csr_data <= s_reg_bit_reg;
when c_ADDR_BIT_CLR_REG(18 downto 2) => s_csr_data <= s_reg_bit_reg;
when c_ADDR_CRAM_OWNER(18 downto 2) => s_csr_data <= s_reg_cram_owner;
when c_ADDR_USR_SET_REG(18 downto 2) => s_csr_data <= s_reg_usr_bit_reg;
when c_ADDR_USR_CLR_REG(18 downto 2) => s_csr_data <= s_reg_usr_bit_reg;
when c_ADDR_F7_ADER_0(18 downto 2) => s_csr_data <= s_ader(7)( 7 downto 0);
when c_ADDR_F7_ADER_1(18 downto 2) => s_csr_data <= s_ader(7)(15 downto 8);
when c_ADDR_F7_ADER_2(18 downto 2) => s_csr_data <= s_ader(7)(23 downto 16);
when c_ADDR_F7_ADER_3(18 downto 2) => s_csr_data <= s_ader(7)(31 downto 24);
when c_ADDR_F6_ADER_0(18 downto 2) => s_csr_data <= s_ader(6)( 7 downto 0);
when c_ADDR_F6_ADER_1(18 downto 2) => s_csr_data <= s_ader(6)(15 downto 8);
when c_ADDR_F6_ADER_2(18 downto 2) => s_csr_data <= s_ader(6)(23 downto 16);
when c_ADDR_F6_ADER_3(18 downto 2) => s_csr_data <= s_ader(6)(31 downto 24);
when c_ADDR_F5_ADER_0(18 downto 2) => s_csr_data <= s_ader(5)( 7 downto 0);
when c_ADDR_F5_ADER_1(18 downto 2) => s_csr_data <= s_ader(5)(15 downto 8);
when c_ADDR_F5_ADER_2(18 downto 2) => s_csr_data <= s_ader(5)(23 downto 16);
when c_ADDR_F5_ADER_3(18 downto 2) => s_csr_data <= s_ader(5)(31 downto 24);
when c_ADDR_F4_ADER_0(18 downto 2) => s_csr_data <= s_ader(4)( 7 downto 0);
when c_ADDR_F4_ADER_1(18 downto 2) => s_csr_data <= s_ader(4)(15 downto 8);
when c_ADDR_F4_ADER_2(18 downto 2) => s_csr_data <= s_ader(4)(23 downto 16);
when c_ADDR_F4_ADER_3(18 downto 2) => s_csr_data <= s_ader(4)(31 downto 24);
when c_ADDR_F3_ADER_0(18 downto 2) => s_csr_data <= s_ader(3)( 7 downto 0);
when c_ADDR_F3_ADER_1(18 downto 2) => s_csr_data <= s_ader(3)(15 downto 8);
when c_ADDR_F3_ADER_2(18 downto 2) => s_csr_data <= s_ader(3)(23 downto 16);
when c_ADDR_F3_ADER_3(18 downto 2) => s_csr_data <= s_ader(3)(31 downto 24);
when c_ADDR_F2_ADER_0(18 downto 2) => s_csr_data <= s_ader(2)( 7 downto 0);
when c_ADDR_F2_ADER_1(18 downto 2) => s_csr_data <= s_ader(2)(15 downto 8);
when c_ADDR_F2_ADER_2(18 downto 2) => s_csr_data <= s_ader(2)(23 downto 16);
when c_ADDR_F2_ADER_3(18 downto 2) => s_csr_data <= s_ader(2)(31 downto 24);
when c_ADDR_F1_ADER_0(18 downto 2) => s_csr_data <= s_ader(1)( 7 downto 0);
when c_ADDR_F1_ADER_1(18 downto 2) => s_csr_data <= s_ader(1)(15 downto 8);
when c_ADDR_F1_ADER_2(18 downto 2) => s_csr_data <= s_ader(1)(23 downto 16);
when c_ADDR_F1_ADER_3(18 downto 2) => s_csr_data <= s_ader(1)(31 downto 24);
when c_ADDR_F0_ADER_0(18 downto 2) => s_csr_data <= s_ader(0)( 7 downto 0);
when c_ADDR_F0_ADER_1(18 downto 2) => s_csr_data <= s_ader(0)(15 downto 8);
when c_ADDR_F0_ADER_2(18 downto 2) => s_csr_data <= s_ader(0)(23 downto 16);
when c_ADDR_F0_ADER_3(18 downto 2) => s_csr_data <= s_ader(0)(31 downto 24);
when others => s_csr_data <= x"ff";
end case;
end if;
......@@ -482,18 +482,18 @@ begin
------------------------------------------------------------------------------
-- CRAM
------------------------------------------------------------------------------
gen_cram: if f_size(g_beg_cram, g_end_cram) > 1 generate
s_cram_access <= '1' when s_addr(18 downto 2) >= unsigned(g_beg_cram(18 downto 2)) and
s_addr(18 downto 2) <= unsigned(g_end_cram(18 downto 2))
gen_cram: if f_size(g_BEG_CRAM, g_END_CRAM) > 1 generate
s_cram_access <= '1' when s_addr(18 downto 2) >= unsigned(g_BEG_CRAM(18 downto 2)) and
s_addr(18 downto 2) <= unsigned(g_END_CRAM(18 downto 2))
else '0';
s_cram_addr <= std_logic_vector(s_addr - unsigned(g_beg_cram(18 downto 2)));
s_cram_addr <= std_logic_vector(s_addr - unsigned(g_BEG_CRAM(18 downto 2)));
s_cram_we <= we_i and s_cram_access;
cmp_cram: VME_CRAM
generic map (
g_beg_cram => g_beg_cram,
g_end_cram => g_end_cram
g_BEG_CRAM => g_BEG_CRAM,
g_END_CRAM => g_END_CRAM
)
port map (
clk_i => clk_i,
......@@ -503,7 +503,7 @@ begin
data_o => s_cram_data
);
end generate;
gen_no_cram: if f_size(g_beg_cram, g_end_cram) <= 1 generate
gen_no_cram: if f_size(g_BEG_CRAM, g_END_CRAM) <= 1 generate
s_cram_access <= '0';
s_cram_addr <= (others => '0');
s_cram_data <= x"00";
......@@ -512,26 +512,26 @@ begin
------------------------------------------------------------------------------
-- User CR/CSR
------------------------------------------------------------------------------
gen_user_cr: if f_size(g_beg_user_cr, g_end_user_cr) > 1 generate
s_user_cr_access <= '1' when s_addr >= unsigned(g_beg_user_cr(18 downto 2)) and
s_addr <= unsigned(g_end_user_cr(18 downto 2))
gen_user_cr: if f_size(g_BEG_USER_CR, g_END_USER_CR) > 1 generate
s_user_cr_access <= '1' when s_addr >= unsigned(g_BEG_USER_CR(18 downto 2)) and
s_addr <= unsigned(g_END_USER_CR(18 downto 2))
else '0';
user_cr_addr_o <= std_logic_vector(s_addr - unsigned(g_beg_user_cr(18 downto 2)));
user_cr_addr_o <= std_logic_vector(s_addr - unsigned(g_BEG_USER_CR(18 downto 2)));
end generate;
gen_no_user_cr: if f_size(g_beg_user_cr, g_end_user_cr) <= 1 generate
gen_no_user_cr: if f_size(g_BEG_USER_CR, g_END_USER_CR) <= 1 generate
s_user_cr_access <= '0';
user_cr_addr_o <= (others => '0');
end generate;
gen_user_csr: if f_size(g_beg_user_csr, g_end_user_csr) > 1 generate
s_user_csr_access <= '1' when s_addr >= unsigned(g_beg_user_csr(18 downto 2)) and
s_addr <= unsigned(g_end_user_csr(18 downto 2))
gen_user_csr: if f_size(g_BEG_USER_CSR, g_END_USER_CSR) > 1 generate
s_user_csr_access <= '1' when s_addr >= unsigned(g_BEG_USER_CSR(18 downto 2)) and
s_addr <= unsigned(g_END_USER_CSR(18 downto 2))
else '0';
user_csr_addr_o <= std_logic_vector(s_addr - unsigned(g_beg_user_csr(18 downto 2)));
user_csr_addr_o <= std_logic_vector(s_addr - unsigned(g_BEG_USER_CSR(18 downto 2)));
end generate;
gen_no_user_csr: if f_size(g_beg_user_csr, g_end_user_csr) <= 1 generate
gen_no_user_csr: if f_size(g_BEG_USER_CSR, g_END_USER_CSR) <= 1 generate
s_user_csr_access <= '0';
user_csr_addr_o <= (others => '0');
end generate;
......
hdl/vme64x-core/rtl/VME_Funct_Match.vhd
View file @ a3b2fde3
......@@ -318,7 +318,7 @@ begin
s_FUNC_ADEM(7) <= unsigned(Adem7);
GDFS : for i in 0 to 7 generate
DFS_o(i) <= s_FUNC_ADEM(i)(ADEM_DFS);
DFS_o(i) <= s_FUNC_ADEM(i)(c_ADEM_DFS);
end generate GDFS;
GADER_64 : for i in 0 to 6 generate
......
hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd
View file @ a3b2fde3
......@@ -129,7 +129,7 @@ use work.vme64x_pack.all;
entity VME_IRQ_Controller is
generic (
g_retry_timeout : integer range 1024 to 16777215
g_RETRY_TIMEOUT : integer range 1024 to 16777215
);
port (
clk_i : in std_logic;
......@@ -224,7 +224,7 @@ begin
retry_state <= WAIT_IRQ;
else
retry_count <= retry_count + 1;
if (retry_count = g_retry_timeout) then
if (retry_count = g_RETRY_TIMEOUT) then
retry_state <= WAIT_IRQ;
end if;
end if;
......
hdl/vme64x-core/rtl/VME_User_CSR.vhd
View file @ a3b2fde3
......@@ -17,14 +17,14 @@
-- To achieve the previous memory map layout, it is necessary to set the
-- following generics on the VME64xCore_Top:
--
-- g_beg_user_csr => x"07ff33",
-- g_end_user_csr => x"07ff5f",
-- g_BEG_USER_CSR => x"07ff33",
-- g_END_USER_CSR => x"07ff5f",
--
-- However, for new designs it would be better to choose somewhere outside
-- the reserved area (from x"7fc00" to x"7ff5f"). For example:
--
-- g_beg_user_csr => x"07fbd3",
-- g_end_user_csr => x"07fbff",
-- g_BEG_USER_CSR => x"07fbd3",
-- g_END_USER_CSR => x"07fbff",
--
-- The following registers are implemented:
-- _
......@@ -70,7 +70,7 @@ use work.vme64x_pack.all;
entity VME_User_CSR is
generic (
g_wb_data_width : integer
g_WB_DATA_WIDTH : integer
);
port (
clk_i : in std_logic;
......@@ -102,7 +102,7 @@ begin
s_addr <= unsigned(addr_i);
s_reg_wb32bits <= x"01" when g_wb_data_width = 32 else x"00";
s_reg_wb32bits <= x"01" when g_WB_DATA_WIDTH = 32 else x"00";
-- Write
process (clk_i)
......@@ -115,9 +115,9 @@ begin
else
if we_i = '1' then
case s_addr is
when c_addr_irq_vector(18 downto 2) => s_reg_irq_vector <= data_i;
when c_addr_irq_level(18 downto 2) => s_reg_irq_level <= data_i;
when c_addr_endian(18 downto 2) => s_reg_endian <= data_i;
when c_ADDR_IRQ_VECTOR(18 downto 2) => s_reg_irq_vector <= data_i;
when c_ADDR_IRQ_LEVEL(18 downto 2) => s_reg_irq_level <= data_i;
when c_ADDR_ENDIAN(18 downto 2) => s_reg_endian <= data_i;
when others => null;
end case;
end if;
......@@ -137,17 +137,17 @@ begin
data_o <= x"00";
else
case s_addr is
when c_addr_irq_vector(18 downto 2) => data_o <= s_reg_irq_vector;
when c_addr_irq_level(18 downto 2) => data_o <= s_reg_irq_level;
when c_addr_endian(18 downto 2) => data_o <= s_reg_endian;
when c_addr_time0_ns(18 downto 2) => data_o <= time_i( 7 downto 0);
when c_addr_time1_ns(18 downto 2) => data_o <= time_i(15 downto 8);
when c_addr_time2_ns(18 downto 2) => data_o <= time_i(23 downto 16);
when c_addr_time3_ns(18 downto 2) => data_o <= time_i(31 downto 24);
when c_addr_time4_ns(18 downto 2) => data_o <= time_i(39 downto 32);
when c_addr_bytes0(18 downto 2) => data_o <= bytes_i( 7 downto 0);
when c_addr_bytes1(18 downto 2) => data_o <= bytes_i(15 downto 8);
when c_addr_wb32bits(18 downto 2) => data_o <= s_reg_wb32bits;
when c_ADDR_IRQ_VECTOR(18 downto 2) => data_o <= s_reg_irq_vector;
when c_ADDR_IRQ_LEVEL(18 downto 2) => data_o <= s_reg_irq_level;
when c_ADDR_ENDIAN(18 downto 2) => data_o <= s_reg_endian;
when c_ADDR_TIME0_NS(18 downto 2) => data_o <= time_i( 7 downto 0);
when c_ADDR_TIME1_NS(18 downto 2) => data_o <= time_i(15 downto 8);
when c_ADDR_TIME2_NS(18 downto 2) => data_o <= time_i(23 downto 16);
when c_ADDR_TIME3_NS(18 downto 2) => data_o <= time_i(31 downto 24);
when c_ADDR_TIME4_NS(18 downto 2) => data_o <= time_i(39 downto 32);
when c_ADDR_BYTES0(18 downto 2) => data_o <= bytes_i( 7 downto 0);
when c_ADDR_BYTES1(18 downto 2) => data_o <= bytes_i(15 downto 8);
when c_ADDR_WB32BITS(18 downto 2) => data_o <= s_reg_wb32bits;
when others => data_o <= x"ff";
end case;
end if;
......
hdl/vme64x-core/rtl/VME_Wb_master.vhd
View file @ a3b2fde3
......@@ -73,8 +73,8 @@ use work.vme64x_pack.all;
entity VME_Wb_master is
generic (
g_wb_data_width : integer;
g_wb_addr_width : integer
g_WB_DATA_WIDTH : integer;
g_WB_ADDR_WIDTH : integer
);
port (
memReq_i : in std_logic;
......@@ -95,11 +95,11 @@ entity VME_Wb_master is
err_i : in std_logic;
cyc_o : out std_logic;
memReq_o : out std_logic;
WBdata_o : out std_logic_vector(g_wb_data_width-1 downto 0);
wbData_i : in std_logic_vector(g_wb_data_width-1 downto 0);
locAddr_o : out std_logic_vector(g_wb_addr_width-1 downto 0);
WBdata_o : out std_logic_vector(g_WB_DATA_WIDTH-1 downto 0);
wbData_i : in std_logic_vector(g_WB_DATA_WIDTH-1 downto 0);
locAddr_o : out std_logic_vector(g_WB_ADDR_WIDTH-1 downto 0);
memAckWB_i : in std_logic;
WbSel_o : out std_logic_vector(g_wb_data_width/8-1 downto 0);
WbSel_o : out std_logic_vector(g_WB_DATA_WIDTH/8-1 downto 0);
RW_o : out std_logic
);
end VME_Wb_master;
......@@ -111,7 +111,7 @@ architecture Behavioral of VME_Wb_master is
signal s_AckWithError : std_logic;
signal s_wbData_i : std_logic_vector(63 downto 0);
signal s_select : std_logic_vector(8 downto 0);
signal s_DATi_sample : std_logic_vector(g_wb_data_width-1 downto 0);
signal s_DATi_sample : std_logic_vector(g_WB_DATA_WIDTH-1 downto 0);
begin
......@@ -153,11 +153,11 @@ begin
end process;
-- shift data and address for WB data bus 64 bits
gen64: if (g_wb_data_width = 64) generate
gen64: if (g_WB_DATA_WIDTH = 64) generate
process (clk_i)
begin
if rising_edge(clk_i) then
locAddr_o <= std_logic_vector(resize(unsigned(rel_locAddr_i) srl 3,g_wb_addr_width));
locAddr_o <= std_logic_vector(resize(unsigned(rel_locAddr_i) srl 3,g_WB_ADDR_WIDTH));
end if;
end process;
......@@ -226,11 +226,11 @@ begin
end generate gen64;
-- shift data and address for WB data bus 32 bits
gen32: if (g_wb_data_width = 32) generate
gen32: if (g_WB_DATA_WIDTH = 32) generate
process (clk_i)
begin
if rising_edge(clk_i) then
locAddr_o <= std_logic_vector(resize(unsigned(rel_locAddr_i) srl 2, g_wb_addr_width));
locAddr_o <= std_logic_vector(resize(unsigned(rel_locAddr_i) srl 2, g_WB_ADDR_WIDTH));
end if;
end process;
......@@ -250,21 +250,21 @@ begin
begin
if rising_edge(clk_i) then
case sel_i is
when "10000000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 24, g_wb_data_width));
when "01000000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 16, g_wb_data_width));
when "00100000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 8, g_wb_data_width));
when "00010000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_wb_data_width));
when "00001000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 24, g_wb_data_width));
when "00000100" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 16, g_wb_data_width));
when "00000010" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 8, g_wb_data_width));
when "00000001" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_wb_data_width));
when "11000000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 16, g_wb_data_width));
when "00110000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_wb_data_width));
when "00001100" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 16, g_wb_data_width));
when "00000011" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_wb_data_width));
when "11110000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_wb_data_width));
when "00001111" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_wb_data_width));
when "11111111" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_wb_data_width));
when "10000000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 24, g_WB_DATA_WIDTH));
when "01000000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 16, g_WB_DATA_WIDTH));
when "00100000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 8, g_WB_DATA_WIDTH));
when "00010000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_WB_DATA_WIDTH));
when "00001000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 24, g_WB_DATA_WIDTH));
when "00000100" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 16, g_WB_DATA_WIDTH));
when "00000010" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 8, g_WB_DATA_WIDTH));
when "00000001" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_WB_DATA_WIDTH));
when "11000000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 16, g_WB_DATA_WIDTH));
when "00110000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_WB_DATA_WIDTH));
when "00001100" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 16, g_WB_DATA_WIDTH));
when "00000011" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_WB_DATA_WIDTH));
when "11110000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_WB_DATA_WIDTH));
when "00001111" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_WB_DATA_WIDTH));
when "11111111" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_WB_DATA_WIDTH));
when others => null;
end case;
......
hdl/vme64x-core/rtl/VME_bus.vhd
View file @ a3b2fde3
......@@ -69,39 +69,39 @@ use work.vme64x_pack.all;
entity VME_bus is
generic (
g_clock : integer;
g_wb_data_width : integer;
g_wb_addr_width : integer;
g_beg_user_cr : std_logic_vector( 23 downto 0);
g_end_user_cr : std_logic_vector( 23 downto 0);
g_beg_cram : std_logic_vector( 23 downto 0);
g_end_cram : std_logic_vector( 23 downto 0);
g_beg_user_csr : std_logic_vector( 23 downto 0);
g_end_user_csr : std_logic_vector( 23 downto 0);
g_f0_adem : std_logic_vector( 31 downto 0);
g_f0_amcap : std_logic_vector( 63 downto 0);
g_f0_xamcap : std_logic_vector(255 downto 0);
g_f1_adem : std_logic_vector( 31 downto 0);
g_f1_amcap : std_logic_vector( 63 downto 0);
g_f1_xamcap : std_logic_vector(255 downto 0);
g_f2_adem : std_logic_vector( 31 downto 0);
g_f2_amcap : std_logic_vector( 63 downto 0);
g_f2_xamcap : std_logic_vector(255 downto 0);
g_f3_adem : std_logic_vector( 31 downto 0);
g_f3_amcap : std_logic_vector( 63 downto 0);
g_f3_xamcap : std_logic_vector(255 downto 0);
g_f4_adem : std_logic_vector( 31 downto 0);
g_f4_amcap : std_logic_vector( 63 downto 0);
g_f4_xamcap : std_logic_vector(255 downto 0);
g_f5_adem : std_logic_vector( 31 downto 0);
g_f5_amcap : std_logic_vector( 63 downto 0);
g_f5_xamcap : std_logic_vector(255 downto 0);
g_f6_adem : std_logic_vector( 31 downto 0);
g_f6_amcap : std_logic_vector( 63 downto 0);
g_f6_xamcap : std_logic_vector(255 downto 0);
g_f7_adem : std_logic_vector( 31 downto 0);
g_f7_amcap : std_logic_vector( 63 downto 0);
g_f7_xamcap : std_logic_vector(255 downto 0)
g_CLOCK_PERIOD : integer;
g_WB_DATA_WIDTH : integer;
g_WB_ADDR_WIDTH : integer;
g_BEG_USER_CR : std_logic_vector( 23 downto 0);
g_END_USER_CR : std_logic_vector( 23 downto 0);
g_BEG_CRAM : std_logic_vector( 23 downto 0);
g_END_CRAM : std_logic_vector( 23 downto 0);
g_BEG_USER_CSR : std_logic_vector( 23 downto 0);
g_END_USER_CSR : std_logic_vector( 23 downto 0);
g_F0_ADEM : std_logic_vector( 31 downto 0);
g_F0_AMCAP : std_logic_vector( 63 downto 0);
g_F0_XAMCAP : std_logic_vector(255 downto 0);
g_F1_ADEM : std_logic_vector( 31 downto 0);
g_F1_AMCAP : std_logic_vector( 63 downto 0);
g_F1_XAMCAP : std_logic_vector(255 downto 0);
g_F2_ADEM : std_logic_vector( 31 downto 0);
g_F2_AMCAP : std_logic_vector( 63 downto 0);
g_F2_XAMCAP : std_logic_vector(255 downto 0);
g_F3_ADEM : std_logic_vector( 31 downto 0);
g_F3_AMCAP : std_logic_vector( 63 downto 0);
g_F3_XAMCAP : std_logic_vector(255 downto 0);
g_F4_ADEM : std_logic_vector( 31 downto 0);
g_F4_AMCAP : std_logic_vector( 63 downto 0);
g_F4_XAMCAP : std_logic_vector(255 downto 0);
g_F5_ADEM : std_logic_vector( 31 downto 0);
g_F5_AMCAP : std_logic_vector( 63 downto 0);
g_F5_XAMCAP : std_logic_vector(255 downto 0);
g_F6_ADEM : std_logic_vector( 31 downto 0);
g_F6_AMCAP : std_logic_vector( 63 downto 0);
g_F6_XAMCAP : std_logic_vector(255 downto 0);
g_F7_ADEM : std_logic_vector( 31 downto 0);
g_F7_AMCAP : std_logic_vector( 63 downto 0);
g_F7_XAMCAP : std_logic_vector(255 downto 0)
);
port (
clk_i : in std_logic;
......@@ -134,10 +134,10 @@ entity VME_bus is
-- WB signals
stb_o : out std_logic;
ack_i : in std_logic;
dat_o : out std_logic_vector(g_wb_data_width-1 downto 0);
dat_i : in std_logic_vector(g_wb_data_width-1 downto 0);
adr_o : out std_logic_vector(g_wb_addr_width-1 downto 0);
sel_o : out std_logic_vector(g_wb_data_width/8-1 downto 0);
dat_o : out std_logic_vector(g_WB_DATA_WIDTH-1 downto 0);
dat_i : in std_logic_vector(g_WB_DATA_WIDTH-1 downto 0);
adr_o : out std_logic_vector(g_WB_ADDR_WIDTH-1 downto 0);
sel_o : out std_logic_vector(g_WB_DATA_WIDTH/8-1 downto 0);
we_o : out std_logic;
cyc_o : out std_logic;
err_i : in std_logic;
......@@ -283,7 +283,7 @@ begin
-- Calculate the number of LATCH DS states necessary to match the timing
-- rule 2.39 page 113 VMEbus specification ANSI/IEEE STD1014-1987.
s_num_latchDS <= f_latchDS(g_clock);
s_num_latchDS <= f_latchDS(g_CLOCK_PERIOD);
-- Used to drive the VME_ADDR_DIR_o
s_is_d64 <= '1' when s_sel = "11111111" else '0';
......@@ -361,25 +361,25 @@ begin
s_addressingTypeSelect <= s_AMlatched;
with s_addressingTypeSelect select s_addressingType <=
A24 when c_A24_S_sup,
A24 when c_A24_S,
A24_BLT when c_A24_BLT,
A24_BLT when c_A24_BLT_sup,
A24_MBLT when c_A24_MBLT,
A24_MBLT when c_A24_MBLT_sup,
CR_CSR when c_CR_CSR,
A16 when c_A16,
A16 when c_A16_sup,
A32 when c_A32,
A32 when c_A32_sup,
A32_BLT when c_A32_BLT,
A32_BLT when c_A32_BLT_sup,
A32_MBLT when c_A32_MBLT,
A32_MBLT when c_A32_MBLT_sup,
A64 when c_A64,
A64_BLT when c_A64_BLT,
A64_MBLT when c_A64_MBLT,
TWOedge when c_TWOedge,
A24 when c_AM_A24_S_SUP,
A24 when c_AM_A24_S,
A24_BLT when c_AM_A24_BLT,
A24_BLT when c_AM_A24_BLT_SUP,
A24_MBLT when c_AM_A24_MBLT,
A24_MBLT when c_AM_A24_MBLT_SUP,
CR_CSR when c_AM_CR_CSR,
A16 when c_AM_A16,
A16 when c_AM_A16_SUP,
A32 when c_AM_A32,
A32 when c_AM_A32_SUP,
A32_BLT when c_AM_A32_BLT,
A32_BLT when c_AM_A32_BLT_SUP,
A32_MBLT when c_AM_A32_MBLT,
A32_MBLT when c_AM_A32_MBLT_SUP,
A64 when c_AM_A64,
A64_BLT when c_AM_A64_BLT,
A64_MBLT when c_AM_A64_MBLT,
TWOedge when c_AM_TWOEDGE,
AM_Error when others;
-- Transfer type decoder
......@@ -754,7 +754,7 @@ begin
(s_blockTransferLimit = '1') or
(s_transferType = BLT and (not(s_typeOfDataTransfer = D32 or s_typeOfDataTransfer = D64))) or
(s_transferType = MBLT and s_typeOfDataTransfer /= D64) or
(s_is_d64 = '1' and g_wb_data_width = 32)
(s_is_d64 = '1' and g_WB_DATA_WIDTH = 32)
then
s_BERRcondition <= '1';
else
......@@ -1072,8 +1072,8 @@ begin
Inst_Wb_master : VME_Wb_master
generic map (
g_wb_data_width => g_wb_data_width,
g_wb_addr_width => g_wb_addr_width
g_WB_DATA_WIDTH => g_WB_DATA_WIDTH,
g_WB_ADDR_WIDTH => g_WB_ADDR_WIDTH
)
port map (
memReq_i => s_memReq,
......@@ -1128,30 +1128,30 @@ begin
Ader5 => f5_ader_i,
Ader6 => f6_ader_i,
Ader7 => f7_ader_i,
Adem0 => g_f0_adem,
Adem1 => g_f1_adem,
Adem2 => g_f2_adem,
Adem3 => g_f3_adem,
Adem4 => g_f4_adem,
Adem5 => g_f5_adem,
Adem6 => g_f6_adem,
Adem7 => g_f7_adem,
AmCap0 => g_f0_amcap,
AmCap1 => g_f1_amcap,
AmCap2 => g_f2_amcap,
AmCap3 => g_f3_amcap,
AmCap4 => g_f4_amcap,
AmCap5 => g_f5_amcap,
AmCap6 => g_f6_amcap,
AmCap7 => g_f7_amcap,
XAmCap0 => g_f0_xamcap,
XAmCap1 => g_f1_xamcap,
XAmCap2 => g_f2_xamcap,
XAmCap3 => g_f3_xamcap,
XAmCap4 => g_f4_xamcap,
XAmCap5 => g_f5_xamcap,
XAmCap6 => g_f6_xamcap,
XAmCap7 => g_f7_xamcap,
Adem0 => g_F0_ADEM,
Adem1 => g_F1_ADEM,
Adem2 => g_F2_ADEM,
Adem3 => g_F3_ADEM,
Adem4 => g_F4_ADEM,
Adem5 => g_F5_ADEM,
Adem6 => g_F6_ADEM,
Adem7 => g_F7_ADEM,
AmCap0 => g_F0_AMCAP,
AmCap1 => g_F1_AMCAP,
AmCap2 => g_F2_AMCAP,
AmCap3 => g_F3_AMCAP,
AmCap4 => g_F4_AMCAP,
AmCap5 => g_F5_AMCAP,
AmCap6 => g_F6_AMCAP,
AmCap7 => g_F7_AMCAP,
XAmCap0 => g_F0_XAMCAP,
XAmCap1 => g_F1_XAMCAP,
XAmCap2 => g_F2_XAMCAP,
XAmCap3 => g_F3_XAMCAP,
XAmCap4 => g_F4_XAMCAP,
XAmCap5 => g_F5_XAMCAP,
XAmCap6 => g_F6_XAMCAP,
XAmCap7 => g_F7_XAMCAP,
Am => s_AMlatched,
XAm => std_logic_vector(s_XAM),
BAR_i => bar_i,
......
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @ a3b2fde3
......@@ -41,65 +41,61 @@ package vme64x_pack is
-- Constants
------------------------------------------------------------------------------
--WB data width:
constant c_width : integer := 64; -- must be 32 or 64!
constant c_CLOCK_PERIOD : integer := 10; -- Clock period (ns)
constant c_DATA_WIDTH : integer := 64; -- WB data width: must be 32 or 64
constant c_ADDR_WIDTH : integer := 9; -- WB addr width: 64 or less
-- WB addr width:
constant c_addr_width : integer := 9;
-- Tclk in ns used to calculate the data transfer rate
constant c_clk_period : integer := 10;
-- add here the default boards ID:
constant c_svec_id : std_logic_vector(31 downto 0) := x"00000198";
constant c_cern_id : std_logic_vector(23 downto 0) := x"080030";
constant c_revision_id : std_logic_vector(31 downto 0) := x"00000001";
constant c_program_id : std_logic_vector( 7 downto 0) := x"5a";
-- Default boards IDs
constant c_SVEC_ID : std_logic_vector(31 downto 0) := x"00000198";
constant c_CERN_ID : std_logic_vector(23 downto 0) := x"080030";
constant c_REVISION_ID : std_logic_vector(31 downto 0) := x"00000001";
constant c_PROGRAM_ID : std_logic_vector( 7 downto 0) := x"5a";
-- Bits in ADEM/ADER registers
constant ADEM_FAF : integer := 3;
constant ADEM_DFS : integer := 2;
constant ADEM_EFD : integer := 1;
constant ADEM_EFM : integer := 0;
constant c_ADEM_FAF : integer := 3;
constant c_ADEM_DFS : integer := 2;
constant c_ADEM_EFD : integer := 1;
constant c_ADEM_EFM : integer := 0;
constant ADER_DFSR : integer := 1;
constant ADER_XAM_MODE : integer := 0;
constant c_ADER_DFSR : integer := 1;
constant c_ADER_XAM_MODE : integer := 0;
-- AM table.
-- References:
-- Table 2-3 "Address Modifier Codes" pages 21/22 VME64std ANSI/VITA 1-1994
-- Table 2.4 "Extended Address Modifier Code" page 12 2eSST ANSI/VITA 1.5-2003(R2009)
constant c_A24_S_sup : std_logic_vector(5 downto 0) := "111101"; -- 0x3d
constant c_A24_S : std_logic_vector(5 downto 0) := "111001"; -- 0x39
constant c_A24_BLT : std_logic_vector(5 downto 0) := "111011"; -- 0x3b
constant c_A24_BLT_sup : std_logic_vector(5 downto 0) := "111111"; -- 0x3f
constant c_A24_MBLT : std_logic_vector(5 downto 0) := "111000"; -- 0x38
constant c_A24_MBLT_sup : std_logic_vector(5 downto 0) := "111100"; -- 0x3c
constant c_A24_LCK : std_logic_vector(5 downto 0) := "110010"; -- 0x32
constant c_CR_CSR : std_logic_vector(5 downto 0) := "101111"; -- 0x2f
constant c_A16 : std_logic_vector(5 downto 0) := "101001"; -- 0x29
constant c_A16_sup : std_logic_vector(5 downto 0) := "101101"; -- 0x2d
constant c_A16_LCK : std_logic_vector(5 downto 0) := "101100"; -- 0x2c
constant c_A32 : std_logic_vector(5 downto 0) := "001001"; -- 0x09
constant c_A32_sup : std_logic_vector(5 downto 0) := "001101"; -- 0x0d
constant c_A32_BLT : std_logic_vector(5 downto 0) := "001011"; -- 0x0b
constant c_A32_BLT_sup : std_logic_vector(5 downto 0) := "001111"; -- 0x0f
constant c_A32_MBLT : std_logic_vector(5 downto 0) := "001000"; -- 0x08
constant c_A32_MBLT_sup : std_logic_vector(5 downto 0) := "001100"; -- 0x0c
constant c_A32_LCK : std_logic_vector(5 downto 0) := "000101"; -- 0x05
constant c_A64 : std_logic_vector(5 downto 0) := "000001"; -- 0x01
constant c_A64_BLT : std_logic_vector(5 downto 0) := "000011"; -- 0x03
constant c_A64_MBLT : std_logic_vector(5 downto 0) := "000000"; -- 0x00
constant c_A64_LCK : std_logic_vector(5 downto 0) := "000100"; -- 0x04
constant c_TWOedge : std_logic_vector(5 downto 0) := "100000"; -- 0x20
constant c_A32_2eVME : std_logic_vector(7 downto 0) := "00000001"; -- 0x21
constant c_A64_2eVME : std_logic_vector(7 downto 0) := "00000010"; -- 0x22
constant c_A32_2eSST : std_logic_vector(7 downto 0) := "00010001"; -- 0x11
constant c_A64_2eSST : std_logic_vector(7 downto 0) := "00010010"; -- 0x12
constant c_AM_A24_S_SUP : std_logic_vector(5 downto 0) := "111101"; -- 0x3d
constant c_AM_A24_S : std_logic_vector(5 downto 0) := "111001"; -- 0x39
constant c_AM_A24_BLT : std_logic_vector(5 downto 0) := "111011"; -- 0x3b
constant c_AM_A24_BLT_SUP : std_logic_vector(5 downto 0) := "111111"; -- 0x3f
constant c_AM_A24_MBLT : std_logic_vector(5 downto 0) := "111000"; -- 0x38
constant c_AM_A24_MBLT_SUP : std_logic_vector(5 downto 0) := "111100"; -- 0x3c
constant c_AM_A24_LCK : std_logic_vector(5 downto 0) := "110010"; -- 0x32
constant c_AM_CR_CSR : std_logic_vector(5 downto 0) := "101111"; -- 0x2f
constant c_AM_A16 : std_logic_vector(5 downto 0) := "101001"; -- 0x29
constant c_AM_A16_SUP : std_logic_vector(5 downto 0) := "101101"; -- 0x2d
constant c_AM_A16_LCK : std_logic_vector(5 downto 0) := "101100"; -- 0x2c
constant c_AM_A32 : std_logic_vector(5 downto 0) := "001001"; -- 0x09
constant c_AM_A32_SUP : std_logic_vector(5 downto 0) := "001101"; -- 0x0d
constant c_AM_A32_BLT : std_logic_vector(5 downto 0) := "001011"; -- 0x0b
constant c_AM_A32_BLT_SUP : std_logic_vector(5 downto 0) := "001111"; -- 0x0f
constant c_AM_A32_MBLT : std_logic_vector(5 downto 0) := "001000"; -- 0x08
constant c_AM_A32_MBLT_SUP : std_logic_vector(5 downto 0) := "001100"; -- 0x0c
constant c_AM_A32_LCK : std_logic_vector(5 downto 0) := "000101"; -- 0x05
constant c_AM_A64 : std_logic_vector(5 downto 0) := "000001"; -- 0x01
constant c_AM_A64_BLT : std_logic_vector(5 downto 0) := "000011"; -- 0x03
constant c_AM_A64_MBLT : std_logic_vector(5 downto 0) := "000000"; -- 0x00
constant c_AM_A64_LCK : std_logic_vector(5 downto 0) := "000100"; -- 0x04
constant c_AM_TWOEDGE : std_logic_vector(5 downto 0) := "100000"; -- 0x20
constant c_AM_A32_2EVME : std_logic_vector(7 downto 0) := "00000001"; -- 0x01
constant c_AM_A64_2EVME : std_logic_vector(7 downto 0) := "00000010"; -- 0x02
constant c_AM_A32_2ESST : std_logic_vector(7 downto 0) := "00010001"; -- 0x11
constant c_AM_A64_2ESST : std_logic_vector(7 downto 0) := "00010010"; -- 0x12
-- Defined CR area
constant c_beg_cr : unsigned(19 downto 0) := x"00000";
constant c_end_cr : unsigned(19 downto 0) := x"00FFF";
constant c_BEG_CR : unsigned(19 downto 0) := x"00000";
constant c_END_CR : unsigned(19 downto 0) := x"00FFF";
-- Defined CSR area
-- NOTE: by the standard, the defined CSR area is from 7FC00..7FFFF and the
......@@ -108,61 +104,61 @@ package vme64x_pack is
-- Therefore, to allow compatibility with that version, the reserved
-- area is not decoded as part of the defined CSR. However, it is not
-- advisable to place any registers in this area in new designs.
constant c_beg_csr : unsigned(19 downto 0) := x"7FF60";
constant c_end_csr : unsigned(19 downto 0) := x"7FFFF";
constant c_BEG_CSR : unsigned(19 downto 0) := x"7FF60";
constant c_END_CSR : unsigned(19 downto 0) := x"7FFFF";
-- Defined CSR addresses
constant c_addr_bar : unsigned(19 downto 0) := x"7FFFF";
constant c_addr_bit_set_reg : unsigned(19 downto 0) := x"7FFFB";
constant c_addr_bit_clr_reg : unsigned(19 downto 0) := x"7FFF7";
constant c_addr_cram_owner : unsigned(19 downto 0) := x"7FFF3";
constant c_addr_usr_set_reg : unsigned(19 downto 0) := x"7FFEF";
constant c_addr_usr_clr_reg : unsigned(19 downto 0) := x"7FFEB";
constant c_addr_f7_ader_0 : unsigned(19 downto 0) := x"7FFDF";
constant c_addr_f7_ader_1 : unsigned(19 downto 0) := x"7FFDB";
constant c_addr_f7_ader_2 : unsigned(19 downto 0) := x"7FFD7";
constant c_addr_f7_ader_3 : unsigned(19 downto 0) := x"7FFD3";
constant c_addr_f6_ader_0 : unsigned(19 downto 0) := x"7FFCF";
constant c_addr_f6_ader_1 : unsigned(19 downto 0) := x"7FFCB";
constant c_addr_f6_ader_2 : unsigned(19 downto 0) := x"7FFC7";
constant c_addr_f6_ader_3 : unsigned(19 downto 0) := x"7FFC3";
constant c_addr_f5_ader_0 : unsigned(19 downto 0) := x"7FFBF";
constant c_addr_f5_ader_1 : unsigned(19 downto 0) := x"7FFBB";
constant c_addr_f5_ader_2 : unsigned(19 downto 0) := x"7FFB7";
constant c_addr_f5_ader_3 : unsigned(19 downto 0) := x"7FFB3";
constant c_addr_f4_ader_0 : unsigned(19 downto 0) := x"7FFAF";
constant c_addr_f4_ader_1 : unsigned(19 downto 0) := x"7FFAB";
constant c_addr_f4_ader_2 : unsigned(19 downto 0) := x"7FFA7";
constant c_addr_f4_ader_3 : unsigned(19 downto 0) := x"7FFA3";
constant c_addr_f3_ader_0 : unsigned(19 downto 0) := x"7FF9F";
constant c_addr_f3_ader_1 : unsigned(19 downto 0) := x"7FF9B";
constant c_addr_f3_ader_2 : unsigned(19 downto 0) := x"7FF97";
constant c_addr_f3_ader_3 : unsigned(19 downto 0) := x"7FF93";
constant c_addr_f2_ader_0 : unsigned(19 downto 0) := x"7FF8F";
constant c_addr_f2_ader_1 : unsigned(19 downto 0) := x"7FF8B";
constant c_addr_f2_ader_2 : unsigned(19 downto 0) := x"7FF87";
constant c_addr_f2_ader_3 : unsigned(19 downto 0) := x"7FF83";
constant c_addr_f1_ader_0 : unsigned(19 downto 0) := x"7FF7F";
constant c_addr_f1_ader_1 : unsigned(19 downto 0) := x"7FF7B";
constant c_addr_f1_ader_2 : unsigned(19 downto 0) := x"7FF77";
constant c_addr_f1_ader_3 : unsigned(19 downto 0) := x"7FF73";
constant c_addr_f0_ader_0 : unsigned(19 downto 0) := x"7FF6F";
constant c_addr_f0_ader_1 : unsigned(19 downto 0) := x"7FF6B";
constant c_addr_f0_ader_2 : unsigned(19 downto 0) := x"7FF67";
constant c_addr_f0_ader_3 : unsigned(19 downto 0) := x"7FF63";
constant c_ADDR_BAR : unsigned(19 downto 0) := x"7FFFF";
constant c_ADDR_BIT_SET_REG : unsigned(19 downto 0) := x"7FFFB";
constant c_ADDR_BIT_CLR_REG : unsigned(19 downto 0) := x"7FFF7";
constant c_ADDR_CRAM_OWNER : unsigned(19 downto 0) := x"7FFF3";
constant c_ADDR_USR_SET_REG : unsigned(19 downto 0) := x"7FFEF";
constant c_ADDR_USR_CLR_REG : unsigned(19 downto 0) := x"7FFEB";
constant c_ADDR_F7_ADER_0 : unsigned(19 downto 0) := x"7FFDF";
constant c_ADDR_F7_ADER_1 : unsigned(19 downto 0) := x"7FFDB";
constant c_ADDR_F7_ADER_2 : unsigned(19 downto 0) := x"7FFD7";
constant c_ADDR_F7_ADER_3 : unsigned(19 downto 0) := x"7FFD3";
constant c_ADDR_F6_ADER_0 : unsigned(19 downto 0) := x"7FFCF";
constant c_ADDR_F6_ADER_1 : unsigned(19 downto 0) := x"7FFCB";
constant c_ADDR_F6_ADER_2 : unsigned(19 downto 0) := x"7FFC7";
constant c_ADDR_F6_ADER_3 : unsigned(19 downto 0) := x"7FFC3";
constant c_ADDR_F5_ADER_0 : unsigned(19 downto 0) := x"7FFBF";
constant c_ADDR_F5_ADER_1 : unsigned(19 downto 0) := x"7FFBB";
constant c_ADDR_F5_ADER_2 : unsigned(19 downto 0) := x"7FFB7";
constant c_ADDR_F5_ADER_3 : unsigned(19 downto 0) := x"7FFB3";
constant c_ADDR_F4_ADER_0 : unsigned(19 downto 0) := x"7FFAF";
constant c_ADDR_F4_ADER_1 : unsigned(19 downto 0) := x"7FFAB";
constant c_ADDR_F4_ADER_2 : unsigned(19 downto 0) := x"7FFA7";
constant c_ADDR_F4_ADER_3 : unsigned(19 downto 0) := x"7FFA3";
constant c_ADDR_F3_ADER_0 : unsigned(19 downto 0) := x"7FF9F";
constant c_ADDR_F3_ADER_1 : unsigned(19 downto 0) := x"7FF9B";
constant c_ADDR_F3_ADER_2 : unsigned(19 downto 0) := x"7FF97";
constant c_ADDR_F3_ADER_3 : unsigned(19 downto 0) := x"7FF93";
constant c_ADDR_F2_ADER_0 : unsigned(19 downto 0) := x"7FF8F";
constant c_ADDR_F2_ADER_1 : unsigned(19 downto 0) := x"7FF8B";
constant c_ADDR_F2_ADER_2 : unsigned(19 downto 0) := x"7FF87";
constant c_ADDR_F2_ADER_3 : unsigned(19 downto 0) := x"7FF83";
constant c_ADDR_F1_ADER_0 : unsigned(19 downto 0) := x"7FF7F";
constant c_ADDR_F1_ADER_1 : unsigned(19 downto 0) := x"7FF7B";
constant c_ADDR_F1_ADER_2 : unsigned(19 downto 0) := x"7FF77";
constant c_ADDR_F1_ADER_3 : unsigned(19 downto 0) := x"7FF73";
constant c_ADDR_F0_ADER_0 : unsigned(19 downto 0) := x"7FF6F";
constant c_ADDR_F0_ADER_1 : unsigned(19 downto 0) := x"7FF6B";
constant c_ADDR_F0_ADER_2 : unsigned(19 downto 0) := x"7FF67";
constant c_ADDR_F0_ADER_3 : unsigned(19 downto 0) := x"7FF63";
-- User CSR addresses
constant c_addr_irq_vector : unsigned(19 downto 0) := x"0002F";
constant c_addr_irq_level : unsigned(19 downto 0) := x"0002B";
constant c_addr_endian : unsigned(19 downto 0) := x"00023";
constant c_addr_time0_ns : unsigned(19 downto 0) := x"0001F";
constant c_addr_time1_ns : unsigned(19 downto 0) := x"0001B";
constant c_addr_time2_ns : unsigned(19 downto 0) := x"00017";
constant c_addr_time3_ns : unsigned(19 downto 0) := x"00013";
constant c_addr_time4_ns : unsigned(19 downto 0) := x"0000F";
constant c_addr_bytes0 : unsigned(19 downto 0) := x"0000B";
constant c_addr_bytes1 : unsigned(19 downto 0) := x"00007";
constant c_addr_wb32bits : unsigned(19 downto 0) := x"00003";
constant c_ADDR_IRQ_VECTOR : unsigned(19 downto 0) := x"0002F";
constant c_ADDR_IRQ_LEVEL : unsigned(19 downto 0) := x"0002B";
constant c_ADDR_ENDIAN : unsigned(19 downto 0) := x"00023";
constant c_ADDR_TIME0_NS : unsigned(19 downto 0) := x"0001F";
constant c_ADDR_TIME1_NS : unsigned(19 downto 0) := x"0001B";
constant c_ADDR_TIME2_NS : unsigned(19 downto 0) := x"00017";
constant c_ADDR_TIME3_NS : unsigned(19 downto 0) := x"00013";
constant c_ADDR_TIME4_NS : unsigned(19 downto 0) := x"0000F";
constant c_ADDR_BYTES0 : unsigned(19 downto 0) := x"0000B";
constant c_ADDR_BYTES1 : unsigned(19 downto 0) := x"00007";
constant c_ADDR_WB32BITS : unsigned(19 downto 0) := x"00003";
------------------------------------------------------------------------------
-- Types
......@@ -340,55 +336,55 @@ package vme64x_pack is
component VME64xCore_Top
generic (
g_clock : integer := c_clk_period;
g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width;
g_user_csr_ext : boolean := false;
g_manufacturer_id : std_logic_vector(23 downto 0) := c_cern_id;
g_board_id : std_logic_vector(31 downto 0) := c_svec_id;
g_revision_id : std_logic_vector(31 downto 0) := c_revision_id;
g_program_id : std_logic_vector(7 downto 0) := c_program_id;
g_ascii_ptr : std_logic_vector(23 downto 0) := x"000000";
g_beg_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_end_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_beg_cram : std_logic_vector(23 downto 0) := x"001003";
g_end_cram : std_logic_vector(23 downto 0) := x"0013ff";
g_beg_user_csr : std_logic_vector(23 downto 0) := x"07ff33";
g_end_user_csr : std_logic_vector(23 downto 0) := x"07ff5f";
g_beg_sn : std_logic_vector(23 downto 0) := x"000000";
g_end_sn : std_logic_vector(23 downto 0) := x"000000";
g_f0_adem : std_logic_vector( 31 downto 0) := x"ff000000";
g_f0_amcap : std_logic_vector( 63 downto 0) := x"00000000_0000bb00";
g_f0_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f0_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f1_adem : std_logic_vector( 31 downto 0) := x"fff80000";
g_f1_amcap : std_logic_vector( 63 downto 0) := x"bb000000_00000000";
g_f1_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f1_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f2_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f2_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f2_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f2_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f3_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f3_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f3_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f3_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f4_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f4_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f4_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f4_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f5_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f5_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f5_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f5_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f6_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f6_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f6_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f6_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f7_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f7_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f7_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f7_dawpr : std_logic_vector( 7 downto 0) := x"84"
g_CLOCK_PERIOD : integer := c_CLOCK_PERIOD;
g_WB_DATA_WIDTH : integer := c_DATA_WIDTH;
g_WB_ADDR_WIDTH : integer := c_ADDR_WIDTH;
g_USER_CSR_EXT : boolean := false;
g_MANUFACTURER_ID : std_logic_vector(23 downto 0) := c_CERN_ID;
g_BOARD_ID : std_logic_vector(31 downto 0) := c_SVEC_ID;
g_REVISION_ID : std_logic_vector(31 downto 0) := c_REVISION_ID;
g_PROGRAM_ID : std_logic_vector(7 downto 0) := c_PROGRAM_ID;
g_ASCII_PTR : std_logic_vector(23 downto 0) := x"000000";
g_BEG_USER_CR : std_logic_vector(23 downto 0) := x"000000";
g_END_USER_CR : std_logic_vector(23 downto 0) := x"000000";
g_BEG_CRAM : std_logic_vector(23 downto 0) := x"001003";
g_END_CRAM : std_logic_vector(23 downto 0) := x"0013ff";
g_BEG_USER_CSR : std_logic_vector(23 downto 0) := x"07ff33";
g_END_USER_CSR : std_logic_vector(23 downto 0) := x"07ff5f";
g_BEG_SN : std_logic_vector(23 downto 0) := x"000000";
g_END_SN : std_logic_vector(23 downto 0) := x"000000";
g_F0_ADEM : std_logic_vector( 31 downto 0) := x"ff000000";
g_F0_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_0000bb00";
g_F0_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F0_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F1_ADEM : std_logic_vector( 31 downto 0) := x"fff80000";
g_F1_AMCAP : std_logic_vector( 63 downto 0) := x"bb000000_00000000";
g_F1_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F1_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F2_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F2_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F2_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F2_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F3_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F3_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F3_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F3_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F4_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F4_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F4_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F4_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F5_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F5_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F5_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F5_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F6_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F6_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F6_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F6_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F7_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F7_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F7_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F7_DAWPR : std_logic_vector( 7 downto 0) := x"84"
);
port (
clk_i : in std_logic;
......@@ -419,13 +415,13 @@ package vme64x_pack is
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
DAT_i : in std_logic_vector(g_wb_data_width-1 downto 0);
DAT_o : out std_logic_vector(g_wb_data_width-1 downto 0);
ADR_o : out std_logic_vector(g_wb_addr_width-1 downto 0);
DAT_i : in std_logic_vector(g_WB_DATA_WIDTH-1 downto 0);
DAT_o : out std_logic_vector(g_WB_DATA_WIDTH-1 downto 0);
ADR_o : out std_logic_vector(g_WB_ADDR_WIDTH-1 downto 0);
CYC_o : out std_logic;
ERR_i : in std_logic;
RTY_i : in std_logic;
SEL_o : out std_logic_vector(g_wb_data_width/8-1 downto 0);
SEL_o : out std_logic_vector(g_WB_DATA_WIDTH/8-1 downto 0);
STB_o : out std_logic;
ACK_i : in std_logic;
WE_o : out std_logic;
......@@ -462,39 +458,39 @@ package vme64x_pack is
component VME_bus is
generic (
g_clock : integer;
g_wb_data_width : integer;
g_wb_addr_width : integer;
g_beg_user_cr : std_logic_vector( 23 downto 0);
g_end_user_cr : std_logic_vector( 23 downto 0);
g_beg_cram : std_logic_vector( 23 downto 0);
g_end_cram : std_logic_vector( 23 downto 0);
g_beg_user_csr : std_logic_vector( 23 downto 0);
g_end_user_csr : std_logic_vector( 23 downto 0);
g_f0_adem : std_logic_vector( 31 downto 0);
g_f0_amcap : std_logic_vector( 63 downto 0);
g_f0_xamcap : std_logic_vector(255 downto 0);
g_f1_adem : std_logic_vector( 31 downto 0);
g_f1_amcap : std_logic_vector( 63 downto 0);
g_f1_xamcap : std_logic_vector(255 downto 0);
g_f2_adem : std_logic_vector( 31 downto 0);
g_f2_amcap : std_logic_vector( 63 downto 0);
g_f2_xamcap : std_logic_vector(255 downto 0);
g_f3_adem : std_logic_vector( 31 downto 0);
g_f3_amcap : std_logic_vector( 63 downto 0);
g_f3_xamcap : std_logic_vector(255 downto 0);
g_f4_adem : std_logic_vector( 31 downto 0);
g_f4_amcap : std_logic_vector( 63 downto 0);
g_f4_xamcap : std_logic_vector(255 downto 0);
g_f5_adem : std_logic_vector( 31 downto 0);
g_f5_amcap : std_logic_vector( 63 downto 0);
g_f5_xamcap : std_logic_vector(255 downto 0);
g_f6_adem : std_logic_vector( 31 downto 0);
g_f6_amcap : std_logic_vector( 63 downto 0);
g_f6_xamcap : std_logic_vector(255 downto 0);
g_f7_adem : std_logic_vector( 31 downto 0);
g_f7_amcap : std_logic_vector( 63 downto 0);
g_f7_xamcap : std_logic_vector(255 downto 0)
g_CLOCK_PERIOD : integer;
g_WB_DATA_WIDTH : integer;
g_WB_ADDR_WIDTH : integer;
g_BEG_USER_CR : std_logic_vector( 23 downto 0);
g_END_USER_CR : std_logic_vector( 23 downto 0);
g_BEG_CRAM : std_logic_vector( 23 downto 0);
g_END_CRAM : std_logic_vector( 23 downto 0);
g_BEG_USER_CSR : std_logic_vector( 23 downto 0);
g_END_USER_CSR : std_logic_vector( 23 downto 0);
g_F0_ADEM : std_logic_vector( 31 downto 0);
g_F0_AMCAP : std_logic_vector( 63 downto 0);
g_F0_XAMCAP : std_logic_vector(255 downto 0);
g_F1_ADEM : std_logic_vector( 31 downto 0);
g_F1_AMCAP : std_logic_vector( 63 downto 0);
g_F1_XAMCAP : std_logic_vector(255 downto 0);
g_F2_ADEM : std_logic_vector( 31 downto 0);
g_F2_AMCAP : std_logic_vector( 63 downto 0);
g_F2_XAMCAP : std_logic_vector(255 downto 0);
g_F3_ADEM : std_logic_vector( 31 downto 0);
g_F3_AMCAP : std_logic_vector( 63 downto 0);
g_F3_XAMCAP : std_logic_vector(255 downto 0);
g_F4_ADEM : std_logic_vector( 31 downto 0);
g_F4_AMCAP : std_logic_vector( 63 downto 0);
g_F4_XAMCAP : std_logic_vector(255 downto 0);
g_F5_ADEM : std_logic_vector( 31 downto 0);
g_F5_AMCAP : std_logic_vector( 63 downto 0);
g_F5_XAMCAP : std_logic_vector(255 downto 0);
g_F6_ADEM : std_logic_vector( 31 downto 0);
g_F6_AMCAP : std_logic_vector( 63 downto 0);
g_F6_XAMCAP : std_logic_vector(255 downto 0);
g_F7_ADEM : std_logic_vector( 31 downto 0);
g_F7_AMCAP : std_logic_vector( 63 downto 0);
g_F7_XAMCAP : std_logic_vector(255 downto 0)
);
port (
clk_i : in std_logic;
......@@ -522,10 +518,10 @@ package vme64x_pack is
VME_IACK_n_i : in std_logic;
stb_o : out std_logic;
ack_i : in std_logic;
dat_o : out std_logic_vector(g_wb_data_width-1 downto 0);
dat_i : in std_logic_vector(g_wb_data_width-1 downto 0);
adr_o : out std_logic_vector(g_wb_addr_width-1 downto 0);
sel_o : out std_logic_vector(g_wb_data_width/8-1 downto 0);
dat_o : out std_logic_vector(g_WB_DATA_WIDTH-1 downto 0);
dat_i : in std_logic_vector(g_WB_DATA_WIDTH-1 downto 0);
adr_o : out std_logic_vector(g_WB_ADDR_WIDTH-1 downto 0);
sel_o : out std_logic_vector(g_WB_DATA_WIDTH/8-1 downto 0);
we_o : out std_logic;
cyc_o : out std_logic;
err_i : in std_logic;
......@@ -632,51 +628,51 @@ package vme64x_pack is
component VME_CR_CSR_Space is
generic (
g_manufacturer_id : std_logic_vector(23 downto 0);
g_board_id : std_logic_vector(31 downto 0);
g_revision_id : std_logic_vector(31 downto 0);
g_program_id : std_logic_vector(7 downto 0);
g_ascii_ptr : std_logic_vector(23 downto 0);
g_beg_user_cr : std_logic_vector(23 downto 0);
g_end_user_cr : std_logic_vector(23 downto 0);
g_beg_cram : std_logic_vector(23 downto 0);
g_end_cram : std_logic_vector(23 downto 0);
g_beg_user_csr : std_logic_vector(23 downto 0);
g_end_user_csr : std_logic_vector(23 downto 0);
g_beg_sn : std_logic_vector(23 downto 0);
g_end_sn : std_logic_vector(23 downto 0);
g_f0_adem : std_logic_vector( 31 downto 0);
g_f0_amcap : std_logic_vector( 63 downto 0);
g_f0_xamcap : std_logic_vector(255 downto 0);
g_f0_dawpr : std_logic_vector( 7 downto 0);
g_f1_adem : std_logic_vector( 31 downto 0);
g_f1_amcap : std_logic_vector( 63 downto 0);
g_f1_xamcap : std_logic_vector(255 downto 0);
g_f1_dawpr : std_logic_vector( 7 downto 0);
g_f2_adem : std_logic_vector( 31 downto 0);
g_f2_amcap : std_logic_vector( 63 downto 0);
g_f2_xamcap : std_logic_vector(255 downto 0);
g_f2_dawpr : std_logic_vector( 7 downto 0);
g_f3_adem : std_logic_vector( 31 downto 0);
g_f3_amcap : std_logic_vector( 63 downto 0);
g_f3_xamcap : std_logic_vector(255 downto 0);
g_f3_dawpr : std_logic_vector( 7 downto 0);
g_f4_adem : std_logic_vector( 31 downto 0);
g_f4_amcap : std_logic_vector( 63 downto 0);
g_f4_xamcap : std_logic_vector(255 downto 0);
g_f4_dawpr : std_logic_vector( 7 downto 0);
g_f5_adem : std_logic_vector( 31 downto 0);
g_f5_amcap : std_logic_vector( 63 downto 0);
g_f5_xamcap : std_logic_vector(255 downto 0);
g_f5_dawpr : std_logic_vector( 7 downto 0);
g_f6_adem : std_logic_vector( 31 downto 0);
g_f6_amcap : std_logic_vector( 63 downto 0);
g_f6_xamcap : std_logic_vector(255 downto 0);
g_f6_dawpr : std_logic_vector( 7 downto 0);
g_f7_adem : std_logic_vector( 31 downto 0);
g_f7_amcap : std_logic_vector( 63 downto 0);
g_f7_xamcap : std_logic_vector(255 downto 0);
g_f7_dawpr : std_logic_vector( 7 downto 0)
g_MANUFACTURER_ID : std_logic_vector(23 downto 0);
g_BOARD_ID : std_logic_vector(31 downto 0);
g_REVISION_ID : std_logic_vector(31 downto 0);
g_PROGRAM_ID : std_logic_vector(7 downto 0);
g_ASCII_PTR : std_logic_vector(23 downto 0);
g_BEG_USER_CR : std_logic_vector(23 downto 0);
g_END_USER_CR : std_logic_vector(23 downto 0);
g_BEG_CRAM : std_logic_vector(23 downto 0);
g_END_CRAM : std_logic_vector(23 downto 0);
g_BEG_USER_CSR : std_logic_vector(23 downto 0);
g_END_USER_CSR : std_logic_vector(23 downto 0);
g_BEG_SN : std_logic_vector(23 downto 0);
g_END_SN : std_logic_vector(23 downto 0);
g_F0_ADEM : std_logic_vector( 31 downto 0);
g_F0_AMCAP : std_logic_vector( 63 downto 0);
g_F0_XAMCAP : std_logic_vector(255 downto 0);
g_F0_DAWPR : std_logic_vector( 7 downto 0);
g_F1_ADEM : std_logic_vector( 31 downto 0);
g_F1_AMCAP : std_logic_vector( 63 downto 0);
g_F1_XAMCAP : std_logic_vector(255 downto 0);
g_F1_DAWPR : std_logic_vector( 7 downto 0);
g_F2_ADEM : std_logic_vector( 31 downto 0);
g_F2_AMCAP : std_logic_vector( 63 downto 0);
g_F2_XAMCAP : std_logic_vector(255 downto 0);
g_F2_DAWPR : std_logic_vector( 7 downto 0);
g_F3_ADEM : std_logic_vector( 31 downto 0);
g_F3_AMCAP : std_logic_vector( 63 downto 0);
g_F3_XAMCAP : std_logic_vector(255 downto 0);
g_F3_DAWPR : std_logic_vector( 7 downto 0);
g_F4_ADEM : std_logic_vector( 31 downto 0);
g_F4_AMCAP : std_logic_vector( 63 downto 0);
g_F4_XAMCAP : std_logic_vector(255 downto 0);
g_F4_DAWPR : std_logic_vector( 7 downto 0);
g_F5_ADEM : std_logic_vector( 31 downto 0);
g_F5_AMCAP : std_logic_vector( 63 downto 0);
g_F5_XAMCAP : std_logic_vector(255 downto 0);
g_F5_DAWPR : std_logic_vector( 7 downto 0);
g_F6_ADEM : std_logic_vector( 31 downto 0);
g_F6_AMCAP : std_logic_vector( 63 downto 0);
g_F6_XAMCAP : std_logic_vector(255 downto 0);
g_F6_DAWPR : std_logic_vector( 7 downto 0);
g_F7_ADEM : std_logic_vector( 31 downto 0);
g_F7_AMCAP : std_logic_vector( 63 downto 0);
g_F7_XAMCAP : std_logic_vector(255 downto 0);
g_F7_DAWPR : std_logic_vector( 7 downto 0)
);
port (
clk_i : in std_logic;
......@@ -764,7 +760,7 @@ package vme64x_pack is
component VME_User_CSR is
generic (
g_wb_data_width : integer
g_WB_DATA_WIDTH : integer
);
port (
clk_i : in std_logic;
......@@ -783,8 +779,8 @@ package vme64x_pack is
component VME_Wb_master is
generic (
g_wb_data_width : integer;
g_wb_addr_width : integer
g_WB_DATA_WIDTH : integer;
g_WB_ADDR_WIDTH : integer
);
port (
memReq_i : in std_logic;
......@@ -799,7 +795,7 @@ package vme64x_pack is
stall_i : in std_logic;
rty_i : in std_logic;
err_i : in std_logic;
wbData_i : in std_logic_vector(g_wb_data_width-1 downto 0);
wbData_i : in std_logic_vector(g_WB_DATA_WIDTH-1 downto 0);
memAckWB_i : in std_logic;
locDataOut_o : out std_logic_vector(63 downto 0);
memAckWb_o : out std_logic;
......@@ -807,9 +803,9 @@ package vme64x_pack is
rty_o : out std_logic;
cyc_o : out std_logic;
memReq_o : out std_logic;
WBdata_o : out std_logic_vector(g_wb_data_width-1 downto 0);
locAddr_o : out std_logic_vector(g_wb_addr_width-1 downto 0);
WbSel_o : out std_logic_vector(g_wb_data_width/8-1 downto 0);
WBdata_o : out std_logic_vector(g_WB_DATA_WIDTH-1 downto 0);
locAddr_o : out std_logic_vector(g_WB_ADDR_WIDTH-1 downto 0);
WbSel_o : out std_logic_vector(g_WB_DATA_WIDTH/8-1 downto 0);
RW_o : out std_logic
);
end component VME_Wb_master;
......@@ -824,7 +820,7 @@ package vme64x_pack is
component VME_IRQ_Controller
generic (
g_retry_timeout : integer range 1024 to 16777215
g_RETRY_TIMEOUT : integer range 1024 to 16777215
);
port (
clk_i : in std_logic;
......@@ -847,8 +843,8 @@ package vme64x_pack is
component VME_CRAM is
generic (
g_beg_cram : std_logic_vector(23 downto 0);
g_end_cram : std_logic_vector(23 downto 0)
g_BEG_CRAM : std_logic_vector(23 downto 0);
g_END_CRAM : std_logic_vector(23 downto 0)
);
port (
clk_i : in std_logic;
......
hdl/vme64x-core/rtl/xvme64x_core.vhd
View file @ a3b2fde3
......@@ -37,70 +37,70 @@ use work.vme64x_pack.all;
entity xvme64x_core is
generic (
g_clock_period : integer := c_clk_period;
g_wb_data_width : integer := c_wishbone_data_width;
g_wb_addr_width : integer := c_wishbone_address_width;
g_user_csr_ext : boolean := false;
g_CLOCK_PERIOD : integer := c_CLOCK_PERIOD;
g_WB_DATA_WIDTH : integer := c_wishbone_data_width;
g_WB_ADDR_WIDTH : integer := c_wishbone_address_width;
g_USER_CSR_EXT : boolean := false;
-- CR/CSR
g_manufacturer_id : std_logic_vector(23 downto 0) := c_cern_id;
g_board_id : std_logic_vector(31 downto 0) := c_svec_id;
g_revision_id : std_logic_vector(31 downto 0) := c_revision_id;
g_program_id : std_logic_vector(7 downto 0) := c_program_id;
g_ascii_ptr : std_logic_vector(23 downto 0) := x"000000";
g_beg_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_end_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_beg_cram : std_logic_vector(23 downto 0) := x"001003";
g_end_cram : std_logic_vector(23 downto 0) := x"0013ff";
g_beg_user_csr : std_logic_vector(23 downto 0) := x"07ff33";
g_end_user_csr : std_logic_vector(23 downto 0) := x"07ff5f";
g_beg_sn : std_logic_vector(23 downto 0) := x"000000";
g_end_sn : std_logic_vector(23 downto 0) := x"000000";
g_f0_adem : std_logic_vector( 31 downto 0) := x"ff000000";
g_f0_amcap : std_logic_vector( 63 downto 0) := x"00000000_0000bb00";
g_f0_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f0_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f1_adem : std_logic_vector( 31 downto 0) := x"fff80000";
g_f1_amcap : std_logic_vector( 63 downto 0) := x"bb000000_00000000";
g_f1_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f1_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f2_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f2_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f2_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f2_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f3_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f3_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f3_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f3_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f4_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f4_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f4_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f4_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f5_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f5_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f5_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f5_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f6_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f6_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f6_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f6_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f7_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f7_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f7_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f7_dawpr : std_logic_vector( 7 downto 0) := x"84"
g_MANUFACTURER_ID : std_logic_vector(23 downto 0) := c_CERN_ID;
g_BOARD_ID : std_logic_vector(31 downto 0) := c_SVEC_ID;
g_REVISION_ID : std_logic_vector(31 downto 0) := c_REVISION_ID;
g_PROGRAM_ID : std_logic_vector(7 downto 0) := c_PROGRAM_ID;
g_ASCII_PTR : std_logic_vector(23 downto 0) := x"000000";
g_BEG_USER_CR : std_logic_vector(23 downto 0) := x"000000";
g_END_USER_CR : std_logic_vector(23 downto 0) := x"000000";
g_BEG_CRAM : std_logic_vector(23 downto 0) := x"001003";
g_END_CRAM : std_logic_vector(23 downto 0) := x"0013ff";
g_BEG_USER_CSR : std_logic_vector(23 downto 0) := x"07ff33";
g_END_USER_CSR : std_logic_vector(23 downto 0) := x"07ff5f";
g_BEG_SN : std_logic_vector(23 downto 0) := x"000000";
g_END_SN : std_logic_vector(23 downto 0) := x"000000";
g_F0_ADEM : std_logic_vector( 31 downto 0) := x"ff000000";
g_F0_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_0000bb00";
g_F0_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F0_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F1_ADEM : std_logic_vector( 31 downto 0) := x"fff80000";
g_F1_AMCAP : std_logic_vector( 63 downto 0) := x"bb000000_00000000";
g_F1_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F1_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F2_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F2_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F2_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F2_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F3_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F3_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F3_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F3_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F4_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F4_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F4_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F4_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F5_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F5_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F5_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F5_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F6_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F6_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F6_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F6_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F7_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F7_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F7_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F7_DAWPR : std_logic_vector( 7 downto 0) := x"84"
);
port (
clk_i : in std_logic;
......@@ -182,54 +182,54 @@ begin -- wrapper
U_Wrapped_VME : VME64xCore_Top
generic map (
g_clock => g_clock_period,
g_wb_data_width => g_wb_data_width,
g_wb_addr_width => g_wb_addr_width,
g_manufacturer_id => g_manufacturer_id,
g_board_id => g_board_id,
g_revision_id => g_revision_id,
g_program_id => g_program_id,
g_ascii_ptr => g_ascii_ptr,
g_beg_user_cr => g_beg_user_cr,
g_end_user_cr => g_end_user_cr,
g_beg_cram => g_beg_cram,
g_end_cram => g_end_cram,
g_beg_user_csr => g_beg_user_csr,
g_end_user_csr => g_end_user_csr,
g_beg_sn => g_beg_sn,
g_end_sn => g_end_sn,
g_f0_adem => g_f0_adem,
g_f0_amcap => g_f0_amcap,
g_f0_xamcap => g_f0_xamcap,
g_f0_dawpr => g_f0_dawpr,
g_f1_adem => g_f1_adem,
g_f1_amcap => g_f1_amcap,
g_f1_xamcap => g_f1_xamcap,
g_f1_dawpr => g_f1_dawpr,
g_f2_adem => g_f2_adem,
g_f2_amcap => g_f2_amcap,
g_f2_xamcap => g_f2_xamcap,
g_f2_dawpr => g_f2_dawpr,
g_f3_adem => g_f3_adem,
g_f3_amcap => g_f3_amcap,
g_f3_xamcap => g_f3_xamcap,
g_f3_dawpr => g_f3_dawpr,
g_f4_adem => g_f4_adem,
g_f4_amcap => g_f4_amcap,
g_f4_xamcap => g_f4_xamcap,
g_f4_dawpr => g_f4_dawpr,
g_f5_adem => g_f5_adem,
g_f5_amcap => g_f5_amcap,
g_f5_xamcap => g_f5_xamcap,
g_f5_dawpr => g_f5_dawpr,
g_f6_adem => g_f6_adem,
g_f6_amcap => g_f6_amcap,
g_f6_xamcap => g_f6_xamcap,
g_f6_dawpr => g_f6_dawpr,
g_f7_adem => g_f7_adem,
g_f7_amcap => g_f7_amcap,
g_f7_xamcap => g_f7_xamcap,
g_f7_dawpr => g_f7_dawpr
g_CLOCK => g_CLOCK_PERIOD,
g_WB_DATA_WIDTH => g_WB_DATA_WIDTH,
g_WB_ADDR_WIDTH => g_WB_ADDR_WIDTH,
g_MANUFACTURER_ID => g_MANUFACTURER_ID,
g_BOARD_ID => g_BOARD_ID,
g_REVISION_ID => g_REVISION_ID,
g_PROGRAM_ID => g_PROGRAM_ID,
g_ASCII_PTR => g_ASCII_PTR,
g_BEG_USER_CR => g_BEG_USER_CR,
g_END_USER_CR => g_END_USER_CR,
g_BEG_CRAM => g_BEG_CRAM,
g_END_CRAM => g_END_CRAM,
g_BEG_USER_CSR => g_BEG_USER_CSR,
g_END_USER_CSR => g_END_USER_CSR,
g_BEG_SN => g_BEG_SN,
g_END_SN => g_END_SN,
g_F0_ADEM => g_F0_ADEM,
g_F0_AMCAP => g_F0_AMCAP,
g_F0_XAMCAP => g_F0_XAMCAP,
g_F0_DAWPR => g_F0_DAWPR,
g_F1_ADEM => g_F1_ADEM,
g_F1_AMCAP => g_F1_AMCAP,
g_F1_XAMCAP => g_F1_XAMCAP,
g_F1_DAWPR => g_F1_DAWPR,
g_F2_ADEM => g_F2_ADEM,
g_F2_AMCAP => g_F2_AMCAP,
g_F2_XAMCAP => g_F2_XAMCAP,
g_F2_DAWPR => g_F2_DAWPR,
g_F3_ADEM => g_F3_ADEM,
g_F3_AMCAP => g_F3_AMCAP,
g_F3_XAMCAP => g_F3_XAMCAP,
g_F3_DAWPR => g_F3_DAWPR,
g_F4_ADEM => g_F4_ADEM,
g_F4_AMCAP => g_F4_AMCAP,
g_F4_XAMCAP => g_F4_XAMCAP,
g_F4_DAWPR => g_F4_DAWPR,
g_F5_ADEM => g_F5_ADEM,
g_F5_AMCAP => g_F5_AMCAP,
g_F5_XAMCAP => g_F5_XAMCAP,
g_F5_DAWPR => g_F5_DAWPR,
g_F6_ADEM => g_F6_ADEM,
g_F6_AMCAP => g_F6_AMCAP,
g_F6_XAMCAP => g_F6_XAMCAP,
g_F6_DAWPR => g_F6_DAWPR,
g_F7_ADEM => g_F7_ADEM,
g_F7_AMCAP => g_F7_AMCAP,
g_F7_XAMCAP => g_F7_XAMCAP,
g_F7_DAWPR => g_F7_DAWPR
)
port map (
clk_i => clk_i,
......
hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd
View file @ a3b2fde3
......@@ -78,55 +78,55 @@ package xvme64x_core_pkg is
------------------------------------------------------------------------------
component xvme64x_core
generic (
g_clock_period : integer := c_clk_period;
g_wb_data_width : integer := c_wishbone_data_width;
g_wb_addr_width : integer := c_wishbone_address_width;
g_user_csr_ext : boolean := false;
g_manufacturer_id : std_logic_vector(23 downto 0) := c_cern_id;
g_board_id : std_logic_vector(31 downto 0) := c_svec_id;
g_revision_id : std_logic_vector(31 downto 0) := c_revision_id;
g_program_id : std_logic_vector(7 downto 0) := c_program_id;
g_ascii_ptr : std_logic_vector(23 downto 0) := x"000000";
g_beg_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_end_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_beg_cram : std_logic_vector(23 downto 0) := x"001003";
g_end_cram : std_logic_vector(23 downto 0) := x"0013ff";
g_beg_user_csr : std_logic_vector(23 downto 0) := x"07ff33";
g_end_user_csr : std_logic_vector(23 downto 0) := x"07ff5f";
g_beg_sn : std_logic_vector(23 downto 0) := x"000000";
g_end_sn : std_logic_vector(23 downto 0) := x"000000";
g_f0_adem : std_logic_vector( 31 downto 0) := x"ff000000";
g_f0_amcap : std_logic_vector( 63 downto 0) := x"00000000_0000bb00";
g_f0_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f0_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f1_adem : std_logic_vector( 31 downto 0) := x"fff80000";
g_f1_amcap : std_logic_vector( 63 downto 0) := x"bb000000_00000000";
g_f1_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f1_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f2_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f2_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f2_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f2_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f3_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f3_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f3_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f3_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f4_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f4_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f4_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f4_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f5_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f5_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f5_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f5_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f6_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f6_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f6_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f6_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f7_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f7_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f7_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f7_dawpr : std_logic_vector( 7 downto 0) := x"84"
g_CLOCK_PERIOD : integer := c_CLOCK_PERIOD;
g_WB_DATA_WIDTH : integer := c_wishbone_data_width;
g_WB_ADDR_WIDTH : integer := c_wishbone_address_width;
g_USER_CSR_EXT : boolean := false;
g_MANUFACTURER_ID : std_logic_vector(23 downto 0) := c_CERN_ID;
g_BOARD_ID : std_logic_vector(31 downto 0) := c_SVEC_ID;
g_REVISION_ID : std_logic_vector(31 downto 0) := c_REVISION_ID;
g_PROGRAM_ID : std_logic_vector(7 downto 0) := c_PROGRAM_ID;
g_ASCII_PTR : std_logic_vector(23 downto 0) := x"000000";
g_BEG_USER_CR : std_logic_vector(23 downto 0) := x"000000";
g_END_USER_CR : std_logic_vector(23 downto 0) := x"000000";
g_BEG_CRAM : std_logic_vector(23 downto 0) := x"001003";
g_END_CRAM : std_logic_vector(23 downto 0) := x"0013ff";
g_BEG_USER_CSR : std_logic_vector(23 downto 0) := x"07ff33";
g_END_USER_CSR : std_logic_vector(23 downto 0) := x"07ff5f";
g_BEG_SN : std_logic_vector(23 downto 0) := x"000000";
g_END_SN : std_logic_vector(23 downto 0) := x"000000";
g_F0_ADEM : std_logic_vector( 31 downto 0) := x"ff000000";
g_F0_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_0000bb00";
g_F0_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F0_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F1_ADEM : std_logic_vector( 31 downto 0) := x"fff80000";
g_F1_AMCAP : std_logic_vector( 63 downto 0) := x"bb000000_00000000";
g_F1_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F1_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F2_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F2_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F2_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F2_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F3_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F3_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F3_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F3_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F4_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F4_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F4_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F4_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F5_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F5_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F5_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F5_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F6_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F6_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F6_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F6_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F7_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F7_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F7_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F7_DAWPR : std_logic_vector( 7 downto 0) := x"84"
);
port (
clk_i : in std_logic;
......
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