Commit a1d483d8 authored by Tristan Gingold's avatar Tristan Gingold

Clean-up comments.

parent c0affb7f
......@@ -264,7 +264,9 @@ specification for details about these values:
specification for details. Note that the WB `rty` (retry) signal cannot
be used, as the VME BLT transactions can only be retried during the address
phase and this restriction is not exposed to the WB side. The WB err signal
is forwarded to the VME bus as BERR.
is forwarded to the VME bus as BERR. The address on the WB bus corresponds
to the lower bits of the address on the VME bus (bits used to decode the
address are cleared on the WB bus).
* `irq_ack_o` signal is asserted during one cycle when the VME64x Core
acknowledge the interrupt on the VME bus. This signal could be used by the
......@@ -342,10 +344,62 @@ A24 MBLT DMA
## Internals
### xvme64x_core.vhd
The top module `xvme64x_core` instantiates the sub-modules, and also
synchronize the asynchronous VME signals (that need to be) to avoid
metastability problems. This module also handles the `g_USER_CSR_EXT`
generic.
metastability problems.
This module also handles the `g_USER_CSR_EXT` generic and instantiate
a default user CSR if the generic is set to false.
### vme_bus.vhd
This is the main module. It implements an FSM to handle the VME protocol,
and acts as the interface between the VME bus and either the WB bus or the
CR/CSR memory.
The module also handles the interrupt acknowledge. If IACK is asserted on
a falling edge of AS, the cycle is considered as a acknowledge cycle. The FSM
then waits until IACKIN is asserted (or until AS is deasserted). If an
interrupt was pending at the right level when IACKIN is asserted, the VME64x
Core responds to the acknowledge cycle with the interrupt vector; otherwise
it asserts IACKOUT.
### vme_cr_csr_space.vhd
This module implements the CR and CSR spaces. It builds (during elaboration)
the CR memory from the generics value, handle accesses from the VME bus to
these memories, interfaces with CRAM (if present), user CR (if present)
and user CSR (if present).
### vme_func_match.vhd
This module checks if the VME address+AM has to be handled by this VME
slave according to ADER and decoder values. Gives back the
corresponding WB address.
### vme_user_csr.vhd
This module implements a default user CSR with the irq_level and irq_vector
registers.
### vme_irq_controller.vhd
This module implements the interrupt controller. The interrupt cycle is:
1. The wishbone slave generates an pulse on the `int` line when it has to
interrupts the master
2. If no interrupt is pending and the retry mechanism is not started, this
module asserts (to 0) the corresponding VME IRQ line (as defined by
`irq_level`).
3. When ack'ed, the interrupt is marked as not pending anymore.
4. If the interrupt request stays active for more than 1 cycle (therefore it
isn't a pulse), a retry mechanism is started. The interrupt will be
re-sent on the VME bus every 1ms as long as it is active.
## VME64 VITA-1 rules compliance
......
......@@ -4,45 +4,12 @@
-- http://www.ohwr.org/projects/vme64x-core
--------------------------------------------------------------------------------
--
-- unit name: VME_bus (VME_bus.vhd)
--
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch>
-- unit name: VME_bus
--
-- description:
--
-- This block acts as interface between the VMEbus and the CR/CSR space or
-- WBbus.
--
-- _________VME_bus__________
-- | __________________ |
-- | | | ___|
-- | | | | |
-- | | MAIN | | W |
-- V | | | | B | W
-- M | | FSM | | | B
-- E | | | | M |
-- | | | | A | B
-- B | |__________________| | S | U
-- U | __________________ | T | S
-- S | | | | E |
-- | | OTHER DATA & | | R |
-- | | ADDR PROCESS | |___|
-- | |__________________| |
-- |__________________________|
--
-- The Access decode component decodes the address to check if the board is
-- the responding Slave. This component is of fundamental importance, indeed
-- only one Slave can answer to the Master!
-- In the right side you can see the WB Master who implements the Wb Pipelined
-- single read/write protocol.
-- Each VME board plugged in a slot acts as a VME slave module and it has only
-- one CR/CSR space (conforming with the specification) so only one FPGA at
-- time must drive the output lines on the VME bus; only one FPGA at time can
-- carry the vme64x core or other similar VME slave core.
-- Inside each component is possible read a more detailed description.
--
-- dependencies:
-- WB bus.
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
......@@ -57,10 +24,6 @@
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
......@@ -412,9 +375,9 @@ begin
end if;
when DECODE_ACCESS =>
-- check if this slave board is addressed.
-- Check if this slave board is addressed.
-- Wait for DS in parallel.
-- Wait for DS in parallel.
if VME_DS_n_i /= "11" then
s_WRITElatched_n <= VME_WRITE_n_i;
if s_DS_latch_count /= 0 then
......
......@@ -82,8 +82,6 @@
-- The Master can clear these bits by writing '1' in the corresponding bits
-- to the Bit Clr Register (location 0x7fff7).
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
......@@ -97,10 +95,6 @@
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
......
......@@ -6,12 +6,11 @@
--
-- unit name: vme_funct_match
--
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch>
-- description:
--
--
-- VME function decoder. Check if the VME address+AM has to be handled by
-- this VME slave according to ADER and decoder values. Gives back the
-- corresponding WB address.
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
......@@ -26,10 +25,6 @@
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
......
......@@ -6,103 +6,11 @@
--
-- unit name: vme_irq_controller
--
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch>
-- description:
--
--
-- This block acts as Interrupter. Phases of an interrupt cycle:
--
-- 1) The Interrupt Controller receives an interrupt request by the WB bus;
-- this request is a pulse on the INT_Req input
-- 2) The Interrupt Controller asserts ('0') one of the 7 VME_IRQ lines;
-- --> request of a service.
-- The Interrupt priority is specificated by the Master writing the
-- INT_Level register in the CR/CSR space
-- 3) The Interrupter Controller waits for the falling edge on the VME_IACKIN
-- line.
-- 4) When detects VME_IACKIN_n_i = '0' and the Interrupt Handler initiates
-- the Interrupt cycle by asserting AS,the Interrupt Controller check if it
-- is the responding interrupter. Indeed before responding to an interrupt
-- acknowledge cycle the interrupter shall have an interrupt request
-- pending, shall check if the level of that request match the level
-- indicated on the address lines A1, A2 and A3,the data transfer width
-- during the interrupt acknowledge cycle should be equal or greater than
-- the size the it can respond with, and it shall receive a falling edge on
-- its IACKIN*.
-- 5) If it is the responding interrupter, it should send the source/ID on the
-- VME_DATA lines (in our case the source/ID is the INT_Vector that the
-- Master can write in the corresponding register in the CR/CSR space) and
-- it terminates the interrupt cycle with an acknowledge before releasing
-- the IRQ lines. If it isn't the responding interrupter, it should pass a
-- falling edge on down the daisy-chain so other interrupters can respond.
--
-- All the output signals are registered
--
-- To implement the above-mentioned 5 phases, the following FSM has been
-- implemented:
-- __________
-- |--| IACKOUT2 |<-|
-- | |__________| |
-- | |
-- | _________ | _________ _________ _________
-- |-->| IDLE |--->| IRQ |-->| WAIT_AS |-->| WAIT_DS |-------------->|
-- |_________| |_________| |_________| |_________| |
-- | | |
-- | | _________ _________ |
-- | |---------<------------| IACKOUT1| <--| CHECK |<--|
-- | |_________| |_________|
-- | __________ __________ |
-- |--<-----------------| DTACK |<--| DATA_OUT |---<----|
-- |__________| |__________|
--
-- The interrupter wait the IACKIN falling edge in the IRQ state, so if the
-- interrupter don't have interrupt pending for sure it will not respond
-- because it is in IDLE.
-- If the slave module does not have an interrupt pending (IDLE state) and it
-- receives a falling edge on the IACKIN, it shall pass the falling edge
-- through the daisy chain.
-- To obtain this the IACKOUT2 state has been added.
--
-- Time constraint:
--
-- Time constraint #35:
--
-- Clk ____ ____ ____ ____ ____ ____
-- _____| |____| |____| |____| |____| |____| |_____
--
-- VME_AS1_n_i __________________________________________________________
-- _______|
--
-- VME_AS_n_i ______________________________
-- ___________________________________|
--
-- s_AS_RisingEge _________
-- _____________________________________________| |__________
--
-- s_IACKOUT __________________________________________________________
-- _______|
--
-- VME_IACKOUT_ __________________________________________________________
-- _______|
--
-- _______________________________________________________ _________
-- IACKOUT 1/2 \/ IDLE/IRQ
-- _______________________________________________________/\_________
--
-- To respect the time constraint indicated with the number 35 fig. 55 pag. 183
-- in the "VMEbus Specification" ANSI/IEEE STD1014-1987, it is necessary to
-- generate the VME_AS1_n_i signal which is the AS signal that is not sampled,
-- and assign this signal to the s_IACKOUT signal when the fsm is in the IACKOUTx
-- state.
--
-- The LWORD* input is not used now, since this is a D08(O) Interrupter (see
-- Table 31 page 157 VMEbus specification).
--
-- Since this is a D08 interrupter we do not need to monitor the LWORD* and
-- DS1* lines and the Vector (1 byte) is outputted in the D00-D07 data lines.
--
-- This block implements the interrupt controller. It passes the interrupt
-- pulse from WB to the corresponding IRQ signal on the VME bus, until
-- the interrupt is acknowledged by the VME master.
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
......@@ -117,10 +25,6 @@
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
......
......@@ -6,35 +6,11 @@
--
-- unit name: vme_user_csr
--
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch>
-- description:
--
-- This module implements the user CSR registers that were added to the
-- reserved area of the defined CSR in previous versions of this core.
--
--
-- To achieve the previous memory map layout, it is necessary to set the
-- following generics on the vme64x_core:
--
-- g_BEG_USER_CSR => x"07ff33",
-- g_END_USER_CSR => x"07ff5f",
--
-- However, for new designs it would be better to choose somewhere outside
-- the reserved area (from x"7fc00" to x"7ff5f"). For example:
--
-- g_BEG_USER_CSR => x"07fbd3",
-- g_END_USER_CSR => x"07fbff",
--
-- The following registers are implemented:
-- _
-- IRQ_Vector --> 0x0002F |--> For the VME_IRQ_Controller
-- IRQ_level --> 0x0002B _|
--
-- WB32bits --> 0x00003 ----> If bit 0 is '1' the WB data bus is 32b
--
-- dependencies:
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
......@@ -48,10 +24,6 @@
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
......
......@@ -34,51 +34,13 @@
-- | |________________| |________| |___________________| |
-- |_________________________________________________________|
--
-- All the VMEbus's asynchronous signals must be sampled 2 or 3 times to avoid
-- metastability problem.
-- All the output signals on the WB bus are registered.
-- The Input signals from the WB bus aren't registered indeed the WB is a
-- synchronous protocol and some registers in the WB side will introduce a
-- delay that make impossible reproduce the WB PIPELINED protocol.
-- The WB Slave application must work with the same frequency as this vme64x
-- core.
-- The main component of this core is the VME_bus on the left in the block
-- diagram. Inside this component you can find the main finite state machine
-- that coordinates all the synchronisms.
-- The WB protocol is more faster than the VME protocol so to make independent
-- the two protocols a FIFO memory can be introduced.
-- The FIFO is necessary only during 2eSST access mode.
-- During the block transfer without FIFO the VME_bus accesses directly the Wb
-- bus in Single pipelined read/write mode. If this is the only Wb master this
-- solution is better than the solution with FIFO.
-- In this base version of the core the FIFO is not implemented indeed the 2e
-- access modes aren't supported yet.
-- A Configuration ROM/Control Status Register (CR/CSR) address space has been
-- introduced. The CR/CSR space can be accessed with the data transfer type
-- D08_3, D16_23, D32.
-- To access the CR/CSR space: AM = 0x2f --> this is A24 addressing type,
-- SINGLE transfer type. Base Address = Slot Number.
-- This interface is provided with an Interrupter. The IRQ Controller receives
-- from the Application (WB bus) an interrupt request and transfers this
-- interrupt request on the VMEbus. This component acts also during the
-- Interrupt acknowledge cycle, sending the status/ID to the Interrupt
-- handler.
-- Interrupt request; the IRQ Generator/your Wb application sends a pulse
-- to the IRQ Controller which asserts one of the IRQ line defined by
-- irq_level_i.
-- Inside each component, a detailed description is provided.
-- Access modes supported:
-- http://www.ohwr.org/projects/vme64x-core/repository/changes/trunk/
-- documentation/user_guides/VME_access_modes.pdf
--
-- standards:
--
-- * VMEbus ANSI/IEEE Std 1014-1987
-- * VME64 ANSI/VITA 1-1994
-- * VME64x Extensions ANSI/VITA 1.1-1997
-- * VME 2eSST ANSI/VITA 1.5-2003
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
......
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