Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
V
VME64x core
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
VME64x core
Commits
9d43711f
Commit
9d43711f
authored
Jan 28, 2020
by
Tristan Gingold
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
vme_bus: improve timing.
parent
0b0209c1
Show whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
53 additions
and
43 deletions
+53
-43
vme64x_pkg.vhd
hdl/rtl/vme64x_pkg.vhd
+12
-0
vme_bus.vhd
hdl/rtl/vme_bus.vhd
+41
-43
No files found.
hdl/rtl/vme64x_pkg.vhd
View file @
9d43711f
...
...
@@ -175,6 +175,16 @@ package vme64x_pkg is
dawpr
=>
x"84"
),
others
=>
c_vme64x_decoder_disabled
);
-- Default values that could be used when 2e is enabled.
constant
c_vme64x_decoders_2e_default
:
t_vme64x_decoder_arr
:
=
(
0
=>
(
adem
=>
x"ff000000"
,
amcap
=>
x"00000001_0000ff00"
,
dawpr
=>
x"84"
),
1
=>
(
adem
=>
x"fff80000"
,
amcap
=>
x"ff000001_00000000"
,
dawpr
=>
x"84"
),
others
=>
c_vme64x_decoder_disabled
);
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
...
...
@@ -186,6 +196,8 @@ package vme64x_pkg is
g_DECODE_AM
:
boolean
:
=
true
;
g_ENABLE_CR_CSR
:
boolean
:
=
true
;
g_USER_CSR_EXT
:
boolean
:
=
false
;
g_VME32
:
boolean
:
=
True
;
g_VME_2e
:
boolean
:
=
True
;
g_WB_GRANULARITY
:
t_wishbone_address_granularity
;
g_MANUFACTURER_ID
:
std_logic_vector
(
23
downto
0
);
...
...
hdl/rtl/vme_bus.vhd
View file @
9d43711f
...
...
@@ -158,19 +158,6 @@ architecture rtl of vme_bus is
-- Data register, owned by the WB fsm.
signal
data_reg
:
std_logic_vector
(
63
downto
0
);
type
t_addressingType
is
(
A24
,
A24_BLT
,
A24_MBLT
,
CR_CSR
,
A16
,
A32
,
A32_BLT
,
A32_MBLT
,
AM_VME2E
,
AM_ERROR
);
type
t_transferType
is
(
SINGLE
,
BLT
,
...
...
@@ -180,7 +167,6 @@ architecture rtl of vme_bus is
);
-- Addressing type (depending on vme_am_i)
signal
s_addressingType
:
t_addressingType
;
signal
s_transferType
:
t_transferType
;
type
t_mainFSMstates
is
(
...
...
@@ -307,28 +293,6 @@ begin
-- | | | | BYTE 0 | BYTE 1 | BYTE 2 | BYTE 3
-- BYTE 0 | BYTE 1 | BYTE 2 | BYTE 3 | BYTE 4 | BYTE 5 | BYTE 6 | BYTE 7
-- Address modifier decoder
-- Both the supervisor and the user access modes are supported
with
vme_idff_am
select
s_addressingType
<=
A24
when
c_AM_A24_SUP
|
c_AM_A24
,
A24_BLT
when
c_AM_A24_BLT
|
c_AM_A24_BLT_SUP
,
A24_MBLT
when
c_AM_A24_MBLT
|
c_AM_A24_MBLT_SUP
,
CR_CSR
when
c_AM_CR_CSR
,
A16
when
c_AM_A16
|
c_AM_A16_SUP
,
A32
when
c_AM_A32
|
c_AM_A32_SUP
,
A32_BLT
when
c_AM_A32_BLT
|
c_AM_A32_BLT_SUP
,
A32_MBLT
when
c_AM_A32_MBLT
|
c_AM_A32_MBLT_SUP
,
AM_VME2E
when
c_AM_2EVME_6U
,
AM_ERROR
when
others
;
-- Transfer type decoder
with
s_addressingType
select
s_transferType
<=
SINGLE
when
A24
|
CR_CSR
|
A16
|
A32
,
BLT
when
A24_BLT
|
A32_BLT
,
MBLT
when
A24_MBLT
|
A32_MBLT
,
VME2e
when
AM_VME2E
,
TFR_ERROR
when
others
;
------------------------------------------------------------------------------
-- MAIN FSM
------------------------------------------------------------------------------
...
...
@@ -367,6 +331,8 @@ begin
load_addr_reg_phase1
<=
'0'
;
load_addr_reg_phase2
<=
'0'
;
s_transferType
<=
TFR_ERROR
;
s_card_sel
<=
'0'
;
s_conf_sel
<=
'0'
;
s_irq_sel
<=
'0'
;
...
...
@@ -403,6 +369,8 @@ begin
vme_idff_lword_n
<=
vme_lword_n_i
;
vme_idff_am
<=
vme_am_i
;
s_transferType
<=
TFR_ERROR
;
-- Address will be put to addr_reg.
load_addr_reg_phase1
<=
'1'
;
...
...
@@ -421,6 +389,28 @@ begin
s_conf_sel
<=
'0'
;
s_irq_sel
<=
'0'
;
-- Address modifier decoder
case
vme_idff_am
is
when
c_AM_A24_BLT
|
c_AM_A24_BLT_SUP
=>
s_transferType
<=
BLT
;
when
c_AM_A24_MBLT
|
c_AM_A24_MBLT_SUP
=>
s_transferType
<=
MBLT
;
when
c_AM_CR_CSR
=>
s_transferType
<=
SINGLE
;
when
c_AM_A16
|
c_AM_A16_SUP
|
c_AM_A24_SUP
|
c_AM_A24
|
c_AM_A32
|
c_AM_A32_SUP
=>
s_transferType
<=
SINGLE
;
when
c_AM_A32_BLT
|
c_AM_A32_BLT_SUP
=>
s_transferType
<=
BLT
;
when
c_AM_A32_MBLT
|
c_AM_A32_MBLT_SUP
=>
s_transferType
<=
MBLT
;
when
c_AM_2EVME_6U
=>
s_transferType
<=
VME2E
;
when
others
=>
s_transferType
<=
TFR_ERROR
;
end
case
;
-- DS latch counter
s_DS_latch_count
<=
to_unsigned
(
c_num_latchDS
,
3
);
...
...
@@ -911,13 +901,21 @@ begin
-- Reformat address according to the mode (A16, A24, A32)
-- FIXME: not needed if ADEM are correctly reduced to not compare
-- MSBs of A16 or A24 addresses.
case
s_addressingType
is
when
A16
=>
case
vme_idff_am
is
when
c_AM_A16
|
c_AM_A16_SUP
=>
addr_reg
(
31
downto
16
)
<=
(
others
=>
'0'
);
-- A16
when
A24
|
A24_BLT
|
A24_MBLT
=>
when
c_AM_A24_SUP
|
c_AM_A24
|
c_AM_A24_BLT
|
c_AM_A24_BLT_SUP
|
c_AM_A24_MBLT
|
c_AM_A24_MBLT_SUP
=>
addr_reg
(
31
downto
24
)
<=
(
others
=>
'0'
);
-- A24
when
c_AM_CR_CSR
|
c_AM_A32
|
c_AM_A32_SUP
|
c_AM_A32_BLT
|
c_AM_A32_BLT_SUP
|
c_AM_A32_MBLT
|
c_AM_A32_MBLT_SUP
|
c_AM_2EVME_6U
=>
null
;
when
others
=>
null
;
-- A32
null
;
end
case
;
end
if
;
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment