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VME64x core
Commit 964dfa7e authored by dpedrett's avatar dpedrett
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vme64x core compatible with 32 bit WB Data Bus 

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@147 665b4545-5c6b-4c24-801b-41150b02b44b
parent f6b39ba8
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Showing with 166 additions and 71 deletions
hdl/boards/vfc/sim/testbench/VME64x_SIM_Package.vhd
View file @ 964dfa7e
......@@ -529,8 +529,8 @@ DataType : out std_logic_vector (3 downto 0)) is
exit;
else
v_dataToReceiveOut := VME64xBus_In.Vme64xDATA;
assert (v_dataToReceiveOut /= s_Buffer_BLT(n + 1))report "CORRECT DATA!!!" severity error;
assert (v_dataToReceiveOut = s_Buffer_BLT(n + 1))report "RECEIVED WRONG DATA!!!" severity failure;
assert (v_dataToReceiveOut /= s_Buffer_BLT(n))report "CORRECT DATA!!!" severity error;
assert (v_dataToReceiveOut = s_Buffer_BLT(n))report "RECEIVED WRONG DATA!!!" severity failure;
end if;
VME64xBus_Out.Vme64xDs0N <= '1';
VME64xBus_Out.Vme64xDs1N <= '1';
......
hdl/boards/vfc/sim/testbench/VME64x_TB.vhd
View file @ 964dfa7e
......@@ -1270,7 +1270,7 @@ test_VME64x : process
num => s_num, VME64xBus_In => VME64xBus_In, VME64xBus_Out => VME64xBus_Out);
wait for 10 ns;
s_address <= x"0000000000000014"; -- use n+1 inside the function if I start to read from the second D32 word written
s_address <= x"0000000000000010"; -- use n+1 inside the function if I start to read from the second D32 word written
s_num <= "000000100";
Blt_Read(v_address => s_address, s_Buffer_BLT => s_Buffer_BLT,
......@@ -1280,7 +1280,7 @@ test_VME64x : process
wait for 10 ns;
s_dataTransferType <= D08Byte3; --only D32 is possible with BLT transfer
s_AddressingType <= A32_BLT;
s_address <= x"0000000000000014";
s_address <= x"0000000000000010";
s_num <= "000000100";
Blt_Read(v_address => s_address, s_Buffer_BLT => s_Buffer_BLT,
......
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @ 964dfa7e
......@@ -193,6 +193,8 @@
signal s_BAR : std_logic_vector(4 downto 0);
signal s_time : std_logic_vector(39 downto 0);
signal s_bytes : std_logic_vector(12 downto 0);
signal s_W32 : std_logic;
-- Oversampled input signals
signal VME_RST_n_oversampled : std_logic;
signal VME_AS_n_oversampled : std_logic;
......@@ -381,6 +383,7 @@ begin
ModuleEnable => s_ModuleEnable,
MBLT_Endian_i => s_MBLT_Endian,
Sw_Reset => s_Sw_Reset,
W32 => s_W32,
BAR_i => s_BAR,
numBytes => s_bytes,
transfTime => s_time,
......@@ -455,6 +458,7 @@ begin
Ader7 => s_Ader7,
ModuleEnable => s_ModuleEnable,
Sw_Reset => s_Sw_Reset,
W32 => s_W32,
MBLT_Endian_o => s_MBLT_Endian,
BAR_o => s_BAR,
INT_Level => s_INT_Level,
......
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
View file @ 964dfa7e
......@@ -146,6 +146,7 @@ entity VME_CR_CSR_Space is
Ader7 : out std_logic_vector(31 downto 0);
ModuleEnable : out std_logic;
Sw_Reset : out std_logic;
W32 : out std_logic;
MBLT_Endian_o : out std_logic_vector(2 downto 0);
BAR_o : out std_logic_vector(4 downto 0);
-- IRQ_controller signals
......@@ -183,7 +184,7 @@ begin
if s_reset = '1' then
s_CSRarray(BAR) <= (others => '0');
s_bar_written <= '0';
for i in 254 downto BYTES1 loop -- Initialization of the CSR memory
for i in 254 downto WB32or64 loop -- Initialization of the CSR memory
s_CSRarray(i) <= c_csr_array(i);
end loop;
elsif s_bar_written = '0' then
......@@ -245,6 +246,10 @@ begin
when to_integer("00" & c_MBLT_Endian_addr(18 downto 2)) =>
s_CSRarray(MBLT_Endian) <= s_locDataIn(7 downto 0);
when to_integer("00" & c_WB32or64_addr(18 downto 2)) =>
s_CSRarray(WB32or64) <= s_locDataIn(7 downto 0);
when others => null;
end case;
......@@ -317,6 +322,7 @@ begin
when "00" & c_TIME4_ns_addr(18 downto 2) => s_CSRdata <= s_CSRarray(TIME4_ns);
when "00" & c_BYTES0_addr(18 downto 2) => s_CSRdata <= s_CSRarray(BYTES0);
when "00" & c_BYTES1_addr(18 downto 2) => s_CSRdata <= s_CSRarray(BYTES1);
when "00" & c_WB32or64_addr(18 downto 2) => s_CSRdata <= s_CSRarray(WB32or64);
when others => s_CSRdata <= (others => '0');
end case;
......@@ -344,6 +350,7 @@ begin
ModuleEnable <= s_CSRarray(BIT_SET_CLR_REG)(4);
MBLT_Endian_o <= std_logic_vector(s_CSRarray(MBLT_Endian)(2 downto 0));
Sw_Reset <= s_CSRarray(BIT_SET_CLR_REG)(7);
W32 <= s_CSRarray(WB32or64)(0);
BAR_o <= std_logic_vector(s_CSRarray(BAR)(7 downto 3));
---------------------------------------------------------------------------------------------------------------
-- CRAM:
......
hdl/vme64x-core/rtl/VME_CR_pack.vhd
View file @ 964dfa7e
......@@ -148,7 +148,7 @@ package VME_CR_pack is
16#15# => x"00",
16#16# => x"00",
--Program Id code
16#1F# => x"01",
16#1F# => x"02",
--Offset to BEG_USER_CR --Added by Davide
16#20# => x"00",
16#21# => x"00",
......
hdl/vme64x-core/rtl/VME_CSR_pack.vhd
View file @ 964dfa7e
......@@ -77,6 +77,7 @@ FUNC6_ADER_3 =>x"00",
IRQ_Vector =>x"00", --"00" because each Slot has a different IRQ Vector
-- and the VME Master should set this value
IRQ_level =>x"02",
WB32or64 =>x"00",
others => (others => '0'));
end VME_CSR_pack;
......
hdl/vme64x-core/rtl/VME_Wb_master.vhd
View file @ 964dfa7e
This diff is collapsed.
hdl/vme64x-core/rtl/VME_bus.vhd
View file @ 964dfa7e
......@@ -136,6 +136,7 @@ entity VME_bus is
ModuleEnable : in std_logic;
MBLT_Endian_i : in std_logic_vector(2 downto 0);
Sw_Reset : in std_logic;
W32 : in std_logic;
BAR_i : in std_logic_vector(4 downto 0);
numBytes : out std_logic_vector(12 downto 0);
transfTime : out std_logic_vector(39 downto 0);
......@@ -595,7 +596,7 @@ begin
when DTACK_LOW =>
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
s_FSM.s_dataDir <= VME_WRITE_n_i;
s_FSM.s_dataDir <= VME_WRITE_n_i;
s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_dataPhase <= s_dataPhase;
s_FSM.s_transferActive <= '1';
......@@ -614,7 +615,6 @@ begin
when DECIDE_NEXT_CYCLE =>
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
s_FSM.s_dataDir <= VME_WRITE_n_i;
s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_dataPhase <= s_dataPhase;
s_FSM.s_transferActive <= '1';
......@@ -633,7 +633,6 @@ begin
when INCREMENT_ADDR =>
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
s_FSM.s_dataDir <= VME_WRITE_n_i;
s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_dataPhase <= s_dataPhase;
s_FSM.s_transferActive <= '1';
......@@ -643,7 +642,6 @@ begin
when SET_DATA_PHASE =>
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
s_FSM.s_dataDir <= VME_WRITE_n_i;
s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_dataPhase <= '1';
s_FSM.s_transferActive <= '1';
......@@ -985,7 +983,7 @@ begin
(s_addressingType = AM_Error) or s_blockTransferLimit = '1' or
(s_transferType = BLT and (not(s_typeOfDataTransfer = D32 or
s_typeOfDataTransfer = D64))) or (s_transferType = MBLT and
s_typeOfDataTransfer /= D64) then
s_typeOfDataTransfer /= D64) or (s_is_d64 = '1' and W32 = '1') then
s_BERRcondition <= '1';
else
......@@ -1401,6 +1399,7 @@ end process;
stall_i => stall_i,
rty_i => rty_i,
err_i => err_i,
W32 => W32,
cyc_o => cyc_o,
memReq_o => memReq_o,
WBdata_o => wbData_o,
......
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @ 964dfa7e
......@@ -136,6 +136,7 @@ package vme64x_pack is
constant TIME4_ns : integer := FUNC0_ADER_3 -9;
constant BYTES0 : integer := FUNC0_ADER_3 -10;
constant BYTES1 : integer := FUNC0_ADER_3 -11;
constant WB32or64 : integer := FUNC0_ADER_3 -12;
constant MBLT_Endian : integer := FUNC0_ADER_3 -4;
-- Initialization CR:
......@@ -164,10 +165,15 @@ package vme64x_pack is
FUNC_ADEM => (add => 16#188#, len => 32));
-- Main Finite State machine signals defoult:
-- When the S_FPGA detects the magic sequency, it erases the A_FPGA so
-- I don't need to drive the s_dtackOE, s_dataOE, s_addrOE, s_addrDir, s_dataDir
-- to 'Z' in the default configuration.
-- If the S_FPGA will be provided to a core who drive these lines without erase the
-- A_FPGA the above mentioned lines should be changed to 'Z' !!!
constant c_FSM_default : t_FSM :=(
s_memReq => '0',
s_decode => '0',
s_dtackOE => '0',
s_dtackOE => '0',
s_mainDTACK => '1',
s_dataDir => '0',
s_dataOE => '0',
......@@ -233,6 +239,7 @@ package vme64x_pack is
constant c_TIME4_ns_addr : unsigned(19 downto 0) := x"7FF3f";
constant c_BYTES0_addr : unsigned(19 downto 0) := x"7FF3b";
constant c_BYTES1_addr : unsigned(19 downto 0) := x"7FF37";
constant c_WB32or64_addr : unsigned(19 downto 0) := x"7FF33";
constant c_MBLT_Endian_addr : unsigned(19 downto 0) := x"7FF53"; -- VME64x reserved CSR
--___________________________________________________________________________________________
......@@ -336,7 +343,7 @@ package vme64x_pack is
type t_FUNC_32b_array_std is array (0 to 7) of std_logic_vector(31 downto 0); -- ADER register array
type t_FUNC_64b_array_std is array (0 to 7) of std_logic_vector(63 downto 0); -- AMCAP register array
type t_FUNC_256b_array_std is array (0 to 7) of std_logic_vector(255 downto 0); -- XAMCAP register array
type t_CSRarray is array(BAR downto BYTES1) of unsigned(7 downto 0);
type t_CSRarray is array(BAR downto WB32or64) of unsigned(7 downto 0);
type t_cr_array is array (natural range <>) of std_logic_vector(7 downto 0);
--_____________________________________________________________________________________________________
......@@ -375,6 +382,7 @@ package vme64x_pack is
ModuleEnable : in std_logic;
MBLT_Endian_i : in std_logic_vector(2 downto 0);
Sw_Reset : in std_logic;
W32 : in std_logic;
BAR_i : in std_logic_vector(4 downto 0);
transfer_done_i : in std_logic;
reset_o : out std_logic;
......@@ -526,6 +534,7 @@ package vme64x_pack is
Ader7 : out std_logic_vector(31 downto 0);
ModuleEnable : out std_logic;
Sw_Reset : out std_logic;
W32 : out std_logic;
numBytes : in std_logic_vector(12 downto 0);
transfTime : in std_logic_vector(39 downto 0);
MBLT_Endian_o : out std_logic_vector(2 downto 0);
......@@ -594,6 +603,7 @@ package vme64x_pack is
s_AckWithError : out std_logic;
memAckWb : out std_logic;
err : out std_logic;
W32 : in std_logic;
rty : out std_logic;
psize_o : out std_logic_vector(8 downto 0);
cyc_o : out std_logic;
......
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