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VME64x core
Commits
9388296e
Commit
9388296e
authored
Jan 28, 2020
by
Tristan Gingold
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vme: preliminary support of 2eSST.
parent
e02c9e0f
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3 changed files
with
181 additions
and
11 deletions
+181
-11
vme64x_pkg.vhd
hdl/rtl/vme64x_pkg.vhd
+4
-4
vme_bus.vhd
hdl/rtl/vme_bus.vhd
+172
-7
xvme64x_core.vhd
hdl/rtl/xvme64x_core.vhd
+5
-0
No files found.
hdl/rtl/vme64x_pkg.vhd
View file @
9388296e
...
...
@@ -106,10 +106,10 @@ package vme64x_pkg is
-- Not used, but for completness.
subtype
t_xam_vec
is
std_logic_vector
(
7
downto
0
);
constant
c_AM_A32_2EVME
:
t_xam_vec
:
=
"00000001"
;
-- 0x01
constant
c_AM_A64_2EVME
:
t_xam_vec
:
=
"00000010"
;
-- 0x02
constant
c_AM_A32_2ESST
:
t_xam_vec
:
=
"00010001"
;
-- 0x11
constant
c_AM_A64_2ESST
:
t_xam_vec
:
=
"00010010"
;
-- 0x12
constant
c_
X
AM_A32_2EVME
:
t_xam_vec
:
=
"00000001"
;
-- 0x01
constant
c_
X
AM_A64_2EVME
:
t_xam_vec
:
=
"00000010"
;
-- 0x02
constant
c_
X
AM_A32_2ESST
:
t_xam_vec
:
=
"00010001"
;
-- 0x11
constant
c_
X
AM_A64_2ESST
:
t_xam_vec
:
=
"00010010"
;
-- 0x12
------------------------------------------------------------------------------
-- Types
...
...
hdl/rtl/vme_bus.vhd
View file @
9388296e
...
...
@@ -36,6 +36,7 @@ entity vme_bus is
generic
(
g_CLOCK_PERIOD
:
integer
;
g_VME32
:
boolean
;
g_VME_2E
:
boolean
;
g_WB_GRANULARITY
:
t_wishbone_address_granularity
;
g_WB_MODE
:
t_wishbone_interface_mode
);
...
...
@@ -136,6 +137,12 @@ architecture rtl of vme_bus is
signal
vme_odff_dtack_n
:
std_logic
;
signal
vme_odff_dtack_oe
:
std_logic
;
signal
vme_odff_retry_n
:
std_logic
;
signal
vme_odff_retry_oe
:
std_logic
;
signal
vme_xam
:
std_logic_vector
(
7
downto
0
);
signal
vme_cycles
:
unsigned
(
7
downto
0
);
-- If set, dtack is controled directly from ds.
-- Otherwise, it is controled by vme_odff_dtack_n.
signal
vme_dtack_async_ctrl
:
std_logic
;
...
...
@@ -144,8 +151,9 @@ architecture rtl of vme_bus is
-- by address decoder, and incremented during DMA.
signal
addr_reg
:
std_logic_vector
(
31
downto
0
);
-- Load addr_reg from vme idff (for address phase1).
-- Load addr_reg from vme idff (for address phase1
and 2
).
signal
load_addr_reg_phase1
:
std_logic
;
signal
load_addr_reg_phase2
:
std_logic
;
-- Data register, owned by the WB fsm.
signal
data_reg
:
std_logic_vector
(
63
downto
0
);
...
...
@@ -159,6 +167,7 @@ architecture rtl of vme_bus is
A32
,
A32_BLT
,
A32_MBLT
,
AM_VME2E
,
AM_ERROR
);
...
...
@@ -166,6 +175,7 @@ architecture rtl of vme_bus is
SINGLE
,
BLT
,
MBLT
,
VME2e
,
TFR_ERROR
);
...
...
@@ -198,6 +208,18 @@ architecture rtl of vme_bus is
-- Assert DTACK
DTACK_LOW
,
-- 2eVME address phase 2 and 3
APHASE_2
,
APHASE_3
,
VME_2E_TURN
,
-- 2eVME/2eSST DATA
VME_2E_DATA
,
VME_2E_SETUP
,
VME_2E_DTACK
,
VME_2E_DONE
,
-- Check if IACK is for this slave
IRQ_CHECK
,
...
...
@@ -213,6 +235,8 @@ architecture rtl of vme_bus is
signal
s_conf_req
:
std_logic
;
-- Global memory request
signal
s_MBLT_Data
:
std_logic
;
-- for MBLT: '1' in Addr
signal
s_2e_dtack
:
std_logic
;
-- Access decode signals
signal
s_conf_sel
:
std_logic
;
-- CR or CSR is addressed
signal
s_card_sel
:
std_logic
;
-- WB memory is addressed
...
...
@@ -294,6 +318,7 @@ begin
A32
when
c_AM_A32
|
c_AM_A32_SUP
,
A32_BLT
when
c_AM_A32_BLT
|
c_AM_A32_BLT_SUP
,
A32_MBLT
when
c_AM_A32_MBLT
|
c_AM_A32_MBLT_SUP
,
AM_VME2E
when
c_AM_2EVME_6U
,
AM_ERROR
when
others
;
-- Transfer type decoder
...
...
@@ -301,6 +326,7 @@ begin
SINGLE
when
A24
|
CR_CSR
|
A16
|
A32
,
BLT
when
A24_BLT
|
A32_BLT
,
MBLT
when
A24_MBLT
|
A32_MBLT
,
VME2e
when
AM_VME2E
,
TFR_ERROR
when
others
;
------------------------------------------------------------------------------
...
...
@@ -320,6 +346,8 @@ begin
vme_odff_dtack_oe
<=
'0'
;
vme_odff_dtack_n
<=
'1'
;
vme_dtack_async_ctrl
<=
'0'
;
vme_odff_retry_oe
<=
'0'
;
vme_odff_retry_n
<=
'1'
;
vme_odff_data_dir
<=
'0'
;
vme_odff_addr_dir
<=
'0'
;
vme_odff_lword_n
<=
'0'
;
...
...
@@ -337,6 +365,7 @@ begin
vme_odff_addr
<=
(
others
=>
'0'
);
load_addr_reg_phase1
<=
'0'
;
load_addr_reg_phase2
<=
'0'
;
s_card_sel
<=
'0'
;
s_conf_sel
<=
'0'
;
...
...
@@ -347,12 +376,15 @@ begin
decode_start_o
<=
'0'
;
vme_odff_dtack_oe
<=
'0'
;
vme_odff_dtack_n
<=
'1'
;
vme_odff_retry_oe
<=
'0'
;
vme_odff_retry_n
<=
'1'
;
vme_dtack_async_ctrl
<=
'0'
;
vme_berr_n_o
<=
'1'
;
vme_iackout_n_o
<=
'1'
;
irq_ack_o
<=
'0'
;
load_addr_reg_phase1
<=
'0'
;
load_addr_reg_phase2
<=
'0'
;
s_wb_start
<=
'0'
;
case
s_mainFSMstate
is
...
...
@@ -550,6 +582,16 @@ begin
-- because we need to know that this is a read access.
s_wb_start
<=
'1'
;
end
if
;
elsif
g_VME_2E
and
s_transferType
=
VME2e
then
if
vme_idff_write_n
=
'0'
then
-- Only read transfers are supported.
s_mainFSMstate
<=
WAIT_END
;
else
-- Assert /dtack
vme_odff_dtack_n
<=
'0'
;
s_mainFSMstate
<=
APHASE_2
;
end
if
;
else
s_mainFSMstate
<=
CHECK_TRANSFER_TYPE
;
-- For every single access or every access at MBLT WRITE
...
...
@@ -673,6 +715,126 @@ begin
s_mainFSMstate
<=
DTACK_LOW
;
end
if
;
when
APHASE_2
=>
-- Address phase 2; wait until DS0 is 1.
vme_odff_dtack_oe
<=
'1'
;
vme_odff_dtack_n
<=
'0'
;
vme_odff_data_dir
<=
'0'
;
vme_odff_addr_dir
<=
'0'
;
if
vme_ds_n_i
=
"11"
then
vme_idff_addr
<=
vme_addr_i
;
vme_idff_lword_n
<=
vme_lword_n_i
;
vme_xam
<=
addr_reg
(
7
downto
0
);
load_addr_reg_phase2
<=
'1'
;
s_wb_start
<=
'1'
;
vme_odff_dtack_n
<=
'1'
;
s_mainFSMstate
<=
APHASE_3
;
end
if
;
when
APHASE_3
=>
vme_odff_dtack_oe
<=
'1'
;
vme_odff_dtack_n
<=
'1'
;
vme_odff_data_dir
<=
'0'
;
vme_odff_addr_dir
<=
'0'
;
vme_cycles
<=
unsigned
(
vme_idff_addr
(
15
downto
8
));
if
vme_ds_n_i
=
"10"
and
s_wb_done
=
'1'
then
s_mainFSMstate
<=
VME_2E_TURN
;
end
if
;
when
VME_2E_TURN
=>
-- Wait until DS1 = 0
vme_odff_dtack_oe
<=
'1'
;
vme_odff_dtack_n
<=
'0'
;
vme_odff_data_dir
<=
'0'
;
vme_odff_addr_dir
<=
'0'
;
if
vme_ds_n_i
=
"00"
and
s_wb_done
=
'1'
then
vme_odff_dtack_n
<=
'0'
;
s_2e_dtack
<=
'0'
;
-- Load the setup counter.
s_setup
<=
unsigned
(
data_timing
(
7
downto
4
));
s_mainFSMstate
<=
VME_2E_DATA
;
end
if
;
when
VME_2E_DATA
|
VME_2E_SETUP
=>
vme_odff_dtack_oe
<=
'1'
;
vme_odff_dtack_n
<=
s_2e_dtack
;
vme_odff_data_dir
<=
'1'
;
vme_odff_addr_dir
<=
'1'
;
vme_odff_addr
<=
data_reg
(
63
downto
33
);
vme_odff_lword_n
<=
data_reg
(
32
);
vme_odff_data
<=
data_reg
(
31
downto
0
);
if
s_mainFSMstate
=
VME_2E_DATA
then
-- Prefetch
s_wb_start
<=
'1'
;
end
if
;
if
s_setup
=
0
then
s_mainFSMstate
<=
VME_2E_DTACK
;
-- Load the hold counter.
s_setup
<=
unsigned
(
data_timing
(
3
downto
0
));
s_2e_dtack
<=
not
s_2e_dtack
;
else
s_setup
<=
s_setup
-
1
;
s_mainFSMstate
<=
VME_2E_SETUP
;
end
if
;
when
VME_2E_DTACK
=>
vme_odff_dtack_oe
<=
'1'
;
vme_odff_dtack_n
<=
s_2e_dtack
;
vme_odff_data_dir
<=
'1'
;
vme_odff_addr_dir
<=
'1'
;
if
s_setup
=
0
then
if
s_2e_dtack
=
'0'
and
vme_cycles
=
1
then
vme_berr_n_o
<=
'0'
;
vme_odff_retry_n
<=
'0'
;
vme_odff_retry_oe
<=
'1'
;
s_mainFSMstate
<=
VME_2E_DONE
;
elsif
s_wb_done
=
'1'
then
s_mainFSMstate
<=
VME_2E_DATA
;
-- Load the setup counter.
s_setup
<=
unsigned
(
data_timing
(
7
downto
4
));
if
s_2e_dtack
=
'0'
then
vme_cycles
<=
vme_cycles
-
1
;
end
if
;
end
if
;
else
s_setup
<=
s_setup
-
1
;
s_mainFSMstate
<=
VME_2E_DTACK
;
end
if
;
when
VME_2E_DONE
=>
-- Release DATA and ADDR.
vme_odff_data_dir
<=
'0'
;
vme_odff_addr_dir
<=
'0'
;
-- Drive dtack
vme_odff_dtack_oe
<=
'1'
;
vme_odff_dtack_n
<=
s_2e_dtack
;
-- Assert BERR and RESP...
vme_berr_n_o
<=
'0'
;
vme_odff_retry_n
<=
'0'
;
vme_odff_retry_oe
<=
'1'
;
-- Until DS is released.
if
vme_ds_n_i
/=
"00"
then
vme_berr_n_o
<=
'1'
;
vme_odff_retry_n
<=
'1'
;
vme_odff_retry_oe
<=
'0'
;
s_mainFSMstate
<=
WAIT_END
;
end
if
;
when
IRQ_CHECK
=>
if
vme_iackin_n_i
=
'0'
then
if
vme_idff_addr
(
3
downto
1
)
=
int_level_i
...
...
@@ -759,6 +921,10 @@ begin
end
case
;
end
if
;
if
load_addr_reg_phase2
=
'1'
then
addr_reg
(
7
downto
0
)
<=
vme_idff_addr
(
7
downto
1
)
&
vme_idff_lword_n
;
end
if
;
if
decode_done_i
=
'1'
then
-- Keep only the local part of the address.
addr_reg
(
31
downto
1
)
<=
addr_decoder_i
;
...
...
@@ -794,7 +960,7 @@ begin
-- 16bit access on a 16bit bus.
wb_sel_o
(
3
downto
2
)
<=
"00"
;
wb_sel_o
(
1
downto
0
)
<=
not
vme_idff_ds_n
;
elsif
addr_reg
(
0
)
=
'0'
then
elsif
addr_reg
(
0
)
=
'0'
or
s_transferType
=
VME2E
then
-- 32bit access
wb_sel_o
<=
"1111"
;
else
...
...
@@ -810,7 +976,7 @@ begin
end
case
;
end
if
;
s_wb_dataphase
<=
f_to_std_logic
(
s_transferType
=
MBLT
);
s_wb_dataphase
<=
f_to_std_logic
(
s_transferType
=
MBLT
or
s_transferType
=
VME2E
);
s_stall
<=
'1'
;
-- Can stall
s_err
<=
'0'
;
...
...
@@ -934,10 +1100,6 @@ begin
end
if
;
end
process
;
-- Retry is not supported
vme_retry_n_o
<=
'1'
;
vme_retry_oe_o
<=
'0'
;
-- WB Master
g_wb_addr32
:
if
g_VME32
generate
...
...
@@ -969,6 +1131,9 @@ begin
vme_data_o
<=
vme_odff_data
;
vme_lword_n_o
<=
vme_odff_lword_n
;
vme_retry_n_o
<=
vme_odff_retry_n
;
vme_retry_oe_o
<=
vme_odff_retry_oe
;
vme_dtack_oe_o
<=
vme_odff_dtack_oe
;
process
(
vme_odff_dtack_n
,
vme_nsync_ds_n_i
,
vme_dtack_async_ctrl
)
...
...
hdl/rtl/xvme64x_core.vhd
View file @
9388296e
...
...
@@ -63,6 +63,9 @@ entity xvme64x_core is
-- As a consequence, it uses a 16bit data wishbone bus.
g_VME32
:
boolean
:
=
True
;
-- If True, supports 2eSST.
g_VME_2e
:
boolean
:
=
True
;
-- Address granularity on the WB bus. Value can be:
-- WORD: VME address bits 31:2 are translated to WB address bits 29:0,
-- the WB data represents bytes for VME address bits 1:0.
...
...
@@ -237,6 +240,7 @@ architecture rtl of xvme64x_core is
constant
c_AMCAP_ALLOWED
:
std_logic_vector
(
63
downto
0
)
:
=
(
16
#
38
#
to
16
#
3
f
#
=>
'1'
,
-- A24
16
#
2
d
#
|
16
#
29
#
=>
'1'
,
-- A16
16
#
20
#
=>
f_to_std_logic
(
g_VME32
and
g_VME_2e
),
16
#
08
#
to
16
#
0
f
#
=>
f_to_std_logic
(
g_VME32
),
-- A32
others
=>
'0'
);
begin
...
...
@@ -320,6 +324,7 @@ begin
generic
map
(
g_CLOCK_PERIOD
=>
g_CLOCK_PERIOD
,
g_VME32
=>
g_VME32
,
g_VME_2E
=>
g_VME_2E
,
g_WB_GRANULARITY
=>
g_WB_GRANULARITY
,
g_WB_MODE
=>
g_WB_MODE
)
port
map
(
...
...
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