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VME64x core
Commit 92f0bc34 authored by dpedrett's avatar dpedrett
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vme64x core after the review. Program ID: 0x5a. 

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@189 665b4545-5c6b-4c24-801b-41150b02b44b
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hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @ 92f0bc34
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hdl/vme64x-core/rtl/VME_Access_Decode.vhd
View file @ 92f0bc34
......@@ -5,7 +5,7 @@
--_________________________________________________________________________________
-- File: VME_Access_Decode.vhd
--_________________________________________________________________________________
-- Description: This component check if the board is addressed and if it is, allows
-- Description: This component checks if the board is addressed and if it is, allows
-- the access to CR/CSR space by asserting the Confaccess signal, or allows the access
-- to WB bus by asserting the CardSel signal.
--
......@@ -17,7 +17,7 @@
-- To Access the Wb bus we have 7 functions; only one at time can be selected. If one of
-- these functions is selected the CardSel signal is asserted (this is the responding Slave).
-- To access the Wb bus we need to decode the AM and the address lines; so as shown in
-- the block diagram the main component are two: VME_Funct_Match, VME_Am_Match.
-- the block diagram the main components are two: VME_Funct_Match, VME_Am_Match.
-- ___________________________________________
-- | VME_Access_Decode.vhd |
......@@ -63,12 +63,12 @@
-- This bit is '1' during A64 and 2e access.
-- DFS = Dynamic Function Decoder: a '1' here means this function can be used
-- to decode different address length (eg. A16 or A24 or A32) so the mask bits
-- should be all '1' !!!
-- should be all '1'.
--
-- AMCAP[63:0]
-- 6 AM lines --> 2**6 = 64 different configurations
-- This register is 64 bits wide and each bit rappresents one AM configuration.
-- If the bit is '1' it means that the corrisponding AM is supported by this function.
-- If the bit is '1' it means that the corresponding AM is supported by this function.
-- If the corresponding ADEM's DFS is 0, only the AMCAP's bits with the same address
-- width must be '1'.
-- If the corresponding ADEM's DFS is 1, one or more AMCAP's bits can be '1'
......@@ -80,17 +80,17 @@
-- XAMCAP[255:0]
-- 8 XAM lines --> 2**8 = 256 different configurations
-- This register is 256 bits wide and each bit rappresents one XAM configuration.
-- If the bit is '1' it means that the corrisponding XAM is supported
-- If the bit is '1' it means that the corresponding XAM is supported
-- by this function.
-- This register is used during the decode phase if the XAM bit is asserted (1).
-- Before accessing the board the VME Master must write the ADER registers. Of course for
-- writing properly the ADER the VME Master need to know the corrisponding ADEM and check if
-- writing properly the ADER the VME Master needs to know the corresponding ADEM and check if
-- EFM or DFS bits are asserted. The VME Master can read also
-- the AMCAP and XAMCAP and check the access mode supported by each function.
--
-- eg.1 lets imagine that we want be able to access different storage device; we can assign
-- eg.1 let's imagine that we want to access different storage device; we can assign
-- one base address and one function at each storage.
-- Now the VME Master has to write the base address of each storage in the corrisponding
-- Now the VME Master has to write the base address of each storage in the corresponding
-- ADER's compare bits and after this operation each function decodes the access to
-- the corresponding storage.
-- eg.2 this example is relative to our application; the vme64x interface has to transfer
......@@ -103,7 +103,7 @@
-- function3 and function4 --> A64, A64_BLT, A64_MBLT
-- function5 and function6 --> 2eVME and 2eSST modes
-- Note that if the address is 64 bits wide we need of two ADER and two ADEM to decode the
-- address so we need two functions. (see also EFM bit definition)
-- Of course you can mix these two example and set up one system with more storage devices
-- each with its base address and to assign each storage more than one function to access it
-- with all the access modes.
......@@ -118,8 +118,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--________________________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -286,7 +286,7 @@ begin
if s_func_sel(i) = '1' then
CardSel <= '1';
Base_Addr <= s_nx_base_addr;
exit;
-- exit; in this case the exit statement is useless
end if;
end loop;
end if;
......
hdl/vme64x-core/rtl/VME_Am_Match.vhd
View file @ 92f0bc34
......@@ -6,12 +6,13 @@
-- File: VME_Am_Match.vhd
--______________________________________________________________________________________
-- Description: this component checks if the AM match.
-- If it is the corrispondent AmMatch's bit is asserted. This condition is necessary but
-- If it is the correspondent AmMatch's bit is asserted. This condition is necessary but
-- not sufficient to select the function and access the board.
-- If DFS = '0' the function supports only access modes with the same address width;
-- 1 function --> only 1 address width;
-- with address width I mean A16, A24, A32 or A64.
-- is sufficient check the AMCAP; AmMatch(i) <= s_FUNC_AMCAP(i)(to_integer(unsigned(Am))).
-- If DFS = '1' the function supports access modes with different address wide so AmMatch(i)
-- If DFS = '1' the function supports access modes with different address widths so AmMatch(i)
-- is asserted only if ADER[7:2] = AM and s_FUNC_AMCAP(i)(to_integer(unsigned(Am)))='1'.
-- If ADER(i)'s XAM bit is asserted than AmMatch(i) is asserted only if AM = 0x20 and if the
-- XAMCAP(i)(to_integer(unsigned(XAm))) = '1' and if DFS = '1' also ADER[9:2] must be equal
......@@ -20,8 +21,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -89,7 +90,6 @@ architecture Behavioral of VME_Am_Match is
signal s_FUNC_XAMCAP : t_FUNC_256b_array;
signal s_amcap_match : std_logic_vector(7 downto 0);
signal s_xamcap_match : std_logic_vector(7 downto 0);
signal debugAm : integer;
--===========================================================================
-- Architecture begin
--===========================================================================
......@@ -127,32 +127,27 @@ begin
if rising_edge(clk_i) then
if mainFSMreset = '1' or reset = '1' then
AmMatch <= (others => '0');
debugAm <= 0;
elsif decode = '1' then
for i in AmMatch'range loop
if DFS_i(i) = '1' then
if s_FUNC_ADER(i)(XAM_MODE) = '0' then
if unsigned(s_FUNC_ADER(i)(7 downto 2)) = unsigned(Am) then
AmMatch(i) <= s_amcap_match(i);
debugAm <= 1;
AmMatch(i) <= s_amcap_match(i);
else
AmMatch(i) <= '0';
end if;
else
if (unsigned(XAm) = unsigned(s_FUNC_ADER(i)(9 downto 2))) then
AmMatch(i) <= s_xamcap_match(i) and s_amcap_match(i);
debugAm <= 2;
AmMatch(i) <= s_xamcap_match(i) and s_amcap_match(i);
else
AmMatch(i) <= '0';
end if;
end if;
else
if s_FUNC_ADER(i)(XAM_MODE) = '1' then
AmMatch(i) <= s_xamcap_match(i) and s_amcap_match(i);
debugAm <= 3;
AmMatch(i) <= s_xamcap_match(i) and s_amcap_match(i);
else
AmMatch(i) <= s_amcap_match(i);
debugAm <= 4;
AmMatch(i) <= s_amcap_match(i);
end if;
end if;
end loop;
......
hdl/vme64x-core/rtl/VME_CRAM.vhd
View file @ 92f0bc34
......@@ -10,8 +10,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
View file @ 92f0bc34
......@@ -6,9 +6,9 @@
-- File: VME_CR_CSR_Space.vhd
--________________________________________________________________________________________________
-- Description:
-- Please note that only every fourth location in the CR/CSR space is used so is possible write
-- Please note that only every fourth location in the CR/CSR space is used so it is possible write
-- the CSR/CRAM selecting the data transfer mode D08_Byte3, D16_Byte23, D32. If other data transfer
-- mode are selected the write operation will not be successful.
-- modes are selected the write operation will not be successful.
-- If the Master access the board for a reading operation with data transfer type different than
-- D08_Byte3, D16_Byte23, D32 the data that will be read is 0.
-- width = 1 byte
......@@ -44,14 +44,14 @@
-- |_________________________________| 0x00
--
-- If the size of the register is bigger than 1 byte, (eg: ADER is 4 bytes) these bytes are
-- storaged in the BIG_ENDIAN ORDER!!
-- stored in the BIG_ENDIAN ORDER.
-- User CR and User CSR are not implemented.
-- In addition to the registers of the table 10-13 in the CSR space you can find:
-- _
-- IRQ_Vector --> 0x7FF5F |--> for the Interrupter
-- IRQ_level --> 0x7FF5B _|
--
-- MBLT_Endian --> 0x7FF53 --> for the swapper
-- Endian --> 0x7FF53 --> for the swapper
--
-- WB32bits --> 0x7FF33 --> if the bit 0 is '1' it means that the WB data bus is 32 bit
-- _
......@@ -96,8 +96,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -123,15 +123,20 @@ use work.VME_CSR_pack.all;
--===========================================================================
entity VME_CR_CSR_Space is
generic(
g_CRAM_SIZE : integer := c_CRAM_SIZE;
g_width : integer := c_width
g_cram_size : integer := c_CRAM_SIZE;
g_wb_data_width : integer := c_width;
g_CRspace : t_cr_array := c_cr_array;
g_BoardID : integer := c_SVEC_ID;
g_ManufacturerID : integer := c_CERN_ID; -- 0x00080030
g_RevisionID : integer := c_RevisionID; -- 0x00000001
g_ProgramID : integer := 96 -- 0x00000060
);
Port ( -- VMEbus.vhd signals
clk_i : in std_logic;
reset : in std_logic;
CR_addr : in std_logic_vector (11 downto 0);
CR_data : out std_logic_vector (7 downto 0);
CRAM_addr : in std_logic_vector (f_log2_size(g_CRAM_SIZE)-1 downto 0);
CRAM_addr : in std_logic_vector (f_log2_size(g_cram_size)-1 downto 0);
CRAM_data_o : out std_logic_vector (7 downto 0);
CRAM_data_i : in std_logic_vector (7 downto 0);
CRAM_Wen : in std_logic;
......@@ -155,8 +160,7 @@ entity VME_CR_CSR_Space is
Ader7 : out std_logic_vector(31 downto 0);
ModuleEnable : out std_logic;
Sw_Reset : out std_logic;
W32 : out std_logic;
MBLT_Endian_o : out std_logic_vector(2 downto 0);
Endian_o : out std_logic_vector(2 downto 0);
BAR_o : out std_logic_vector(4 downto 0);
-- IRQ_controller signals
INT_Level : out std_logic_vector(7 downto 0);
......@@ -171,6 +175,7 @@ architecture Behavioral of VME_CR_CSR_Space is
signal s_bar_written : std_logic;
signal s_CSRdata : unsigned(7 downto 0);
signal s_FUNC_ADER : t_FUNC_32b_array;
signal s_CR_Space : t_cr_array(2**12 downto 0);
signal s_CrCsrOffsetAddr : unsigned(18 downto 0);
signal s_locDataIn : unsigned(7 downto 0);
signal s_CrCsrOffsetAderIndex : unsigned(18 downto 0);
......@@ -190,11 +195,12 @@ s_odd_parity <= VME_GA_oversampled(5) xor VME_GA_oversampled(4) xor
-- master accesses its CR/CSR space and we can see a time out error in the VME bus.
s_BARerror <= not(s_BAR_o(4) or s_BAR_o(3)or s_BAR_o(2) or s_BAR_o(1) or s_BAR_o(0));
--------------------------------------------------------------------------------
s_CR_Space <= f_set_CR_space(g_BoardID, g_CRspace, g_ManufacturerID, g_RevisionID, g_ProgramID);
-- CR
process(clk_i)
begin
if rising_edge(clk_i) then
CR_data <= c_cr_array(to_integer(unsigned(CR_addr)));
CR_data <= s_CR_Space(to_integer(unsigned(CR_addr))); -- c_cr_array(to_integer(unsigned(CR_addr)));
end if;
end process;
--------------------------------------------------------------------------------
......@@ -270,14 +276,14 @@ s_BARerror <= not(s_BAR_o(4) or s_BAR_o(3)or s_BAR_o(2) or s_BAR_o(1) or s_BAR_o
when to_integer("00" & c_IRQ_level_addr(18 downto 2)) =>
s_CSRarray(IRQ_level) <= s_locDataIn(7 downto 0);
when to_integer("00" & c_MBLT_Endian_addr(18 downto 2)) =>
s_CSRarray(MBLT_Endian) <= s_locDataIn(7 downto 0);
when to_integer("00" & c_Endian_addr(18 downto 2)) =>
s_CSRarray(Endian) <= s_locDataIn(7 downto 0);
when others => null;
end case;
else
if g_width = 32 then
if g_wb_data_width = 32 then
s_CSRarray(WB32bits) <= x"01";
else
s_CSRarray(WB32bits) <= x"00";
......@@ -342,7 +348,7 @@ s_BARerror <= not(s_BAR_o(4) or s_BAR_o(3)or s_BAR_o(2) or s_BAR_o(1) or s_BAR_o
when "00" & c_FUNC0_ADER_3_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC0_ADER_3);
when "00" & c_IRQ_Vector_addr (18 downto 2) => s_CSRdata <= s_CSRarray(IRQ_Vector);
when "00" & c_IRQ_level_addr(18 downto 2) => s_CSRdata <= s_CSRarray(IRQ_level);
when "00" & c_MBLT_Endian_addr(18 downto 2) => s_CSRdata <= s_CSRarray(MBLT_Endian);
when "00" & c_Endian_addr(18 downto 2) => s_CSRdata <= s_CSRarray(Endian);
when "00" & c_TIME0_ns_addr(18 downto 2) => s_CSRdata <= s_CSRarray(TIME0_ns);
when "00" & c_TIME1_ns_addr(18 downto 2) => s_CSRdata <= s_CSRarray(TIME1_ns);
when "00" & c_TIME2_ns_addr(18 downto 2) => s_CSRdata <= s_CSRarray(TIME2_ns);
......@@ -360,13 +366,13 @@ s_BARerror <= not(s_BAR_o(4) or s_BAR_o(3)or s_BAR_o(2) or s_BAR_o(1) or s_BAR_o
INT_Vector <= std_logic_vector(s_CSRarray(IRQ_Vector));
CSRdata <= std_logic_vector(s_CSRdata);
s_CrCsrOffsetAddr <= unsigned(CrCsrOffsetAddr);
-- Generate a vector of 8 array (unsigned 32 bits).
GADER_1 : for i in 0 to 7 generate
GADER_2 : for h in 0 to 3 generate
s_FUNC_ADER(i)(8*(4-h)-1 downto 8*(3-h)) <= s_CSRarray(FUNC0_ADER_3+(h+i*4));
end generate GADER_2;
end generate GADER_1;
-- to the decoder
Ader0 <= std_logic_vector(s_FUNC_ADER(0));
Ader1 <= std_logic_vector(s_FUNC_ADER(1));
Ader2 <= std_logic_vector(s_FUNC_ADER(2));
......@@ -376,16 +382,15 @@ s_BARerror <= not(s_BAR_o(4) or s_BAR_o(3)or s_BAR_o(2) or s_BAR_o(1) or s_BAR_o
Ader6 <= std_logic_vector(s_FUNC_ADER(6));
Ader7 <= std_logic_vector(s_FUNC_ADER(7));
ModuleEnable <= s_CSRarray(BIT_SET_CLR_REG)(4);
MBLT_Endian_o <= std_logic_vector(s_CSRarray(MBLT_Endian)(2 downto 0));
Endian_o <= std_logic_vector(s_CSRarray(Endian)(2 downto 0));
Sw_Reset <= s_CSRarray(BIT_SET_CLR_REG)(7);
W32 <= s_CSRarray(WB32bits)(0);
BAR_o <= s_BAR_o;
s_BAR_o <= std_logic_vector(s_CSRarray(BAR)(7 downto 3));
---------------------------------------------------------------------------------------------------------------
-- CRAM:
CRAM_1 : VME_CRAM
generic map(dl => 8,
al => f_log2_size(g_CRAM_SIZE)
al => f_log2_size(g_cram_size)
)
port map(clk => clk_i,
we => CRAM_Wen,
......
hdl/vme64x-core/rtl/VME_CR_pack.vhd
View file @ 92f0bc34
......@@ -33,7 +33,7 @@ use IEEE.numeric_std.all;
use work.vme64x_pack.all;
package VME_CR_pack is
-- type t_cr_array is array (natural range <>) of std_logic_vector(7 downto 0);
constant c_amcap : std_logic_vector(63 downto 0) :=
"1111111100000000001100100000000000000000000100001111111100001011";
constant c_amcap0 : std_logic_vector(63 downto 0) :=
......@@ -138,26 +138,26 @@ package VME_CR_pack is
16#07# => x"43",
--Ascii "R"
16#08# => x"52",
--Manufacturer's ID
16#09# => x"01",
16#0A# => x"02",
16#0B# => x"03",
--board id
--Manufacturer's ID -- for CERN: 0x080030
16#09# => x"08",
16#0A# => x"00",
16#0B# => x"30",
--board id -- eg: SVEC ID = 0x000198
16#0C# => x"03",
16#0D# => x"04",
16#0E# => x"04",
16#0F# => x"03",
--Rev id
16#10# => x"03",
16#11# => x"04",
16#12# => x"04",
16#13# => x"03",
16#10# => x"00",
16#11# => x"00",
16#12# => x"00",
16#13# => x"02",
--Point to ascii null terminatied
16#14# => x"00",
16#15# => x"00",
16#16# => x"00",
--Program Id code
16#1F# => x"59",
16#1F# => x"5a",
--Offset to BEG_USER_CR
16#20# => x"00",
16#21# => x"00",
......
hdl/vme64x-core/rtl/VME_Funct_Match.vhd
View file @ 92f0bc34
......@@ -6,11 +6,11 @@
-- File: VME_Funct_Match.vhd
--_________________________________________________________________________________________
-- Description: this component compares the Address with the ADER using the mask bits and
-- if the base address match it asserts the corrisponding bit in the FunctMatch vector and it
-- latches the base address that will be subtract to the Address before accessing the WB bus.
-- if the base address match it asserts the corresponding bit in the FunctMatch vector and it
-- latches the base address that will be subtracted to the Address before accessing the WB bus.
-- FunctMatch /= 0 is necessary but not sufficient to select one function and to access the board,
-- indeed also the AM has to be checked (VME_AM_Match.vhd component).
-- For better understanding how this component works here one example:
-- For better understanding how this component works here is one example:
-- base address = 0xc0
-- access mode: A32_S --> AM = 0x09
-- The Master writes the ADERi = 0xc0000024
......@@ -26,11 +26,11 @@
-- |_______|
-- No | |yes
-- FunctMatch(i) <= '0'_____| |______FunctMatch(i) <= '1'
-- Now with the same ADEMi the master access with A16 mode:
-- Now with the same ADEMi the master accesses with A16 mode:
-- base address = 0xc0
-- access mode: A16_S --> AM = 0x29
-- The Master write the ADERi = 0x0000c0a4
-- The Master want access at the location 0x08: Address= 0x0000c008
-- The Master writes the ADERi = 0x0000c0a4
-- The Master wants to access the location 0x08: Address= 0x0000c008
-- For i = 0 to 7 check:
-- Check if the ADEMi is compatible with the AM selected: ADEMi[15:8] /= 0
-- Address[31:8] and ADEMi[31:8] ADERi[31:8] and ADEMi[31:8]
......@@ -49,7 +49,7 @@
-- base address = 0xc0
-- access mode: A32_S --> AM = 0x09
-- The Master write the ADERi = 0xc0000024
-- The Master want access at the location 0x4008: Address= 0xc0004008
-- The Master wants to access the location 0x4008: Address= 0xc0004008
-- For i = 0 to 7 check:
-- Check if the ADEMi is compatible with the AM selected: ADEMi[31:8] /= 0
-- Address[31:8] and ADEMi[31:8] ADERi[31:8] and ADEMi[31:8]
......@@ -66,7 +66,7 @@
-- access mode: A32_S --> AM = 0x09
-- The Master write the ADERi = 0xc0000024
-- ADEMi = 0xff000000 --> DFS = '0'
-- The Master want access at the location 0x4008: Address= 0xc0004008
-- The Master wants to access the location 0x4008: Address= 0xc0004008
-- For i = 0 to 7 check:
-- Check if the ADEMi is compatible with the AM selected: ADEM[31:8] /= 0
-- Address[31:8] and ADEMi[31:8] ADERi[31:8] and ADEMi[31:8]
......@@ -80,9 +80,9 @@
-- The Master can access!
-- base address = 0xc0
-- access mode: A16_S --> AM = 0x29
-- The Master write the ADERi = 0x0000c0a4
-- The Master writes the ADERi = 0x0000c0a4
-- ADEMi = 0xff000000 --> DFS = '0' -- The Master can't change the CR space!!
-- The Master want access at the location 0x08: Address= 0x0000c008
-- The Master wants to access the location 0x08: Address= 0x0000c008
-- For i = 0 to 7 check:
-- Check if the ADEMi is compatible with the AM selected:
-- ADEM[15:8] = 0 --> FunctMatch(i) <= '0'
......@@ -97,7 +97,7 @@
-- A VME Master takes the ownership of the VMEbus for accessing another board:
-- base address = 0xc0
-- access mode: A32_S --> AM = 0x09
-- The Master want access at the location 0x0008: Address= 0xc0000008
-- The Master wants to access the location 0x0008: Address= 0xc0000008
-- For i = 0 to 7 check:
-- Check if the ADEMi is compatible with the AM selected: ADEMi[31:8] /= 0
-- Address[31:8] and ADEMi[31:8] ADERi[31:8] and ADEMi[31:8]
......@@ -144,8 +144,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.01
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -205,7 +205,6 @@ architecture Behavioral of VME_Funct_Match is
signal s_FUNC_ADER_64, s_FUNC_ADEM_64: t_FUNC_64b_array;
signal s_isprev_func64 : std_logic_vector(7 downto 0);
signal s_locAddr : unsigned(63 downto 0);
signal debugfunct : integer;
--===========================================================================
-- Architecture begin
--===========================================================================
......@@ -218,7 +217,6 @@ begin
if mainFSMreset = '1' or reset = '1' then
FunctMatch <= (others => '0');
Nx_Base_Addr <= (others => '0');
debugfunct <= 0;
elsif decode = '1' then
for i in FunctMatch'range loop
......@@ -228,8 +226,7 @@ begin
(s_FUNC_ADEM_64(i)(63 downto 10) /= 0) then
if (s_FUNC_ADER_64(i)(63 downto 10) and s_FUNC_ADEM_64(i)(63 downto 10)) =
((s_locAddr(63 downto 10)) and s_FUNC_ADEM_64(i)(63 downto 10)) then
debugfunct <= 1;
((s_locAddr(63 downto 10)) and s_FUNC_ADEM_64(i)(63 downto 10)) then
FunctMatch(i) <= '1';
Nx_Base_Addr(63 downto 10) <= std_logic_vector(s_FUNC_ADER_64(i)(63 downto 10));
Nx_Base_Addr(9 downto 0) <= (others => '0');
......@@ -244,8 +241,7 @@ begin
FunctMatch(i) <= '1';
Nx_Base_Addr(31 downto 8) <= std_logic_vector(s_FUNC_ADER(i)(31 downto 8));
Nx_Base_Addr(63 downto 32) <= (others => '0');
Nx_Base_Addr(7 downto 0) <= (others => '0');
debugfunct <= 2;
Nx_Base_Addr(7 downto 0) <= (others => '0');
end if;
end if;
......@@ -256,8 +252,7 @@ begin
FunctMatch(i) <= '1';
Nx_Base_Addr(23 downto 8) <= std_logic_vector(s_FUNC_ADER(i)(23 downto 8));
Nx_Base_Addr(63 downto 24) <= (others => '0');
Nx_Base_Addr(7 downto 0) <= (others => '0');
debugfunct <= 3;
Nx_Base_Addr(7 downto 0) <= (others => '0');
end if;
end if;
......@@ -268,8 +263,7 @@ begin
FunctMatch(i) <= '1';
Nx_Base_Addr(15 downto 8) <= std_logic_vector(s_FUNC_ADER(i)(15 downto 8));
Nx_Base_Addr(63 downto 16) <= (others => '0');
Nx_Base_Addr(7 downto 0) <= (others => '0');
debugfunct <= 4;
Nx_Base_Addr(7 downto 0) <= (others => '0');
end if;
end if;
......
hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd
View file @ 92f0bc34
This diff is collapsed.
hdl/vme64x-core/rtl/VME_Init.vhd
View file @ 92f0bc34
......@@ -11,8 +11,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--________________________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -37,42 +37,42 @@ use work.vme64x_pack.all;
-- Entity declaration
--===========================================================================
entity VME_Init is
Port ( clk_i : in std_logic;
RSTedge : inout std_logic;
CRAddr : in std_logic_vector (18 downto 0);
CRdata_i : in std_logic_vector (7 downto 0);
InitReadCount : out std_logic_vector (8 downto 0);
InitInProgress : out std_logic;
BEG_USR_CR_o : out std_logic_vector (23 downto 0);
END_USR_CR_o : out std_logic_vector (23 downto 0);
BEG_USR_CSR_o : out std_logic_vector (23 downto 0);
END_USR_CSR_o : out std_logic_vector (23 downto 0);
BEG_CRAM_o : out std_logic_vector (23 downto 0);
END_CRAM_o : out std_logic_vector (23 downto 0);
FUNC0_ADEM_o : out std_logic_vector (31 downto 0);
FUNC1_ADEM_o : out std_logic_vector (31 downto 0);
FUNC2_ADEM_o : out std_logic_vector (31 downto 0);
FUNC3_ADEM_o : out std_logic_vector (31 downto 0);
FUNC4_ADEM_o : out std_logic_vector (31 downto 0);
FUNC5_ADEM_o : out std_logic_vector (31 downto 0);
FUNC6_ADEM_o : out std_logic_vector (31 downto 0);
FUNC7_ADEM_o : out std_logic_vector (31 downto 0);
FUNC0_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC1_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC2_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC3_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC4_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC5_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC6_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC7_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC0_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC1_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC2_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC3_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC4_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC5_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC6_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC7_XAMCAP_o : out std_logic_vector (255 downto 0));
Port ( clk_i : in std_logic;
RSTedge_i : in std_logic;
CRAddr_i : in std_logic_vector (18 downto 0);
CRdata_i : in std_logic_vector (7 downto 0);
InitReadCount_o : out std_logic_vector (8 downto 0);
InitInProgress_o : out std_logic;
BEG_USR_CR_o : out std_logic_vector (23 downto 0);
END_USR_CR_o : out std_logic_vector (23 downto 0);
BEG_USR_CSR_o : out std_logic_vector (23 downto 0);
END_USR_CSR_o : out std_logic_vector (23 downto 0);
BEG_CRAM_o : out std_logic_vector (23 downto 0);
END_CRAM_o : out std_logic_vector (23 downto 0);
FUNC0_ADEM_o : out std_logic_vector (31 downto 0);
FUNC1_ADEM_o : out std_logic_vector (31 downto 0);
FUNC2_ADEM_o : out std_logic_vector (31 downto 0);
FUNC3_ADEM_o : out std_logic_vector (31 downto 0);
FUNC4_ADEM_o : out std_logic_vector (31 downto 0);
FUNC5_ADEM_o : out std_logic_vector (31 downto 0);
FUNC6_ADEM_o : out std_logic_vector (31 downto 0);
FUNC7_ADEM_o : out std_logic_vector (31 downto 0);
FUNC0_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC1_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC2_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC3_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC4_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC5_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC6_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC7_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC0_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC1_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC2_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC3_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC4_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC5_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC6_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC7_XAMCAP_o : out std_logic_vector (255 downto 0));
end VME_Init;
--===========================================================================
......@@ -103,13 +103,13 @@ architecture Behavioral of VME_Init is
-- Architecture begin
--===========================================================================
begin
InitReadCount <= std_logic_vector(s_initReadCounter);
s_CRaddr <= unsigned(CRAddr);
InitReadCount_o <= std_logic_vector(s_initReadCounter);
s_CRaddr <= unsigned(CRAddr_i);
p_coreInit : process(clk_i)
begin
if rising_edge(clk_i) then
if RSTedge = '1' then
if RSTedge_i = '1' then
s_initState <= IDLE;
s_initReadCounter <= to_unsigned(0, s_initReadCounter'length);
s_latchCRdata <= '0';
......@@ -151,7 +151,7 @@ begin
end process;
s_initInProgress <= '1' when (s_initReadCounter <= (424)) else '0';
InitInProgress <= s_initInProgress;
InitInProgress_o <= s_initInProgress;
s_CRadd_offset <= s_CRaddr - s_CRaddr_base;
process(s_latchCRdata, s_initReadCounter)
......
hdl/vme64x-core/rtl/VME_SharedComps.vhd
View file @ 92f0bc34
......@@ -11,8 +11,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--_______________________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......
hdl/vme64x-core/rtl/VME_Wb_master.vhd
View file @ 92f0bc34
This diff is collapsed.
hdl/vme64x-core/rtl/VME_bus.vhd
View file @ 92f0bc34
This diff is collapsed.
hdl/vme64x-core/rtl/VME_swapper.vhd
View file @ 92f0bc34
......@@ -13,8 +13,8 @@
--______________________________________________________________________________
-- Authors:
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @ 92f0bc34
This diff is collapsed.
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