Commit 91e43d01 authored by Tristan Gingold's avatar Tristan Gingold

top_tb: add a test for boundary crossing.

parent c810475b
......@@ -255,6 +255,8 @@ architecture behaviour of top_tb is
signal bus_timer : std_logic;
signal end_tb : boolean := false;
signal err_8000 : natural := 0;
begin
set_ga: block
begin
......@@ -422,9 +424,15 @@ begin
end process;
-- WB slave: a simple sram
-- 0-0xfff sram
-- 0x4000 counter
-- 0x4004 BERR
-- Note: WB is using word granularity for addresses.
-- VME WB
-- 0x0XXX 0x0XXX
-- 0-0xfff sram
-- 0x4XXX 0x1XXX
-- 0x4000 counter
-- 0x4004 BERR
-- 0x8XXX 0x2XXX
-- 0x8000 invalid (use to detect wrap-arounds on prefetch)
wb_p : process (clk_i)
constant sram_addr_wd : natural := 10;
type sram_array is array (0 to 2**sram_addr_wd - 1)
......@@ -449,6 +457,7 @@ begin
ACK_i <= '0';
int_cnt := 0;
err_8000 <= 0;
else
ACK_i <= '0';
ERR_i <= '0';
......@@ -466,6 +475,19 @@ begin
ACK_i <= '1';
case ADR_o(15 downto 12) is
when "0000" =>
idx := to_integer (unsigned (ADR_o (sram_addr_wd - 1 downto 0)));
if WE_o = '0' then
-- Read SRAM
DAT_i <= sram (idx);
else
-- Write SRAM
for i in 3 downto 0 loop
if SEL_o(i) = '1' then
sram(idx)(8*i + 7 downto 8*i) := DAT_o (8*i + 7 downto 8*i);
end if;
end loop;
end if;
when "0001" =>
if ADR_o (0) = '0' then
if WE_o = '0' then
......@@ -482,19 +504,12 @@ begin
ACK_i <= '0';
ERR_i <= '1';
end if;
when "0000" =>
idx := to_integer (unsigned (ADR_o (sram_addr_wd - 1 downto 0)));
if WE_o = '0' then
-- Read SRAM
DAT_i <= sram (idx);
else
-- Write SRAM
for i in 3 downto 0 loop
if SEL_o(i) = '1' then
sram(idx)(8*i + 7 downto 8*i) := DAT_o (8*i + 7 downto 8*i);
end if;
end loop;
when "0010" =>
report hex8(ADR_o);
if ADR_o (8 downto 0) = b"0_0000_0000" then
err_8000 <= err_8000 + 1;
end if;
DAT_i <= x"8000" & ADR_o(15 downto 0);
when others =>
DAT_i <= (others => '0');
end case;
......@@ -1374,6 +1389,22 @@ begin
x"fe_dc_ba_98_76_54_32_10")
report "incorrect MBLT data 64 r/w" severity error;
-- Check prefetching.
assert err_8000 = 0
report "no 0x8000 error expected" severity error;
read64_mblt (x"64_00_87_e0", c_AM_A32_MBLT, v64 (0 to 3));
report "at e0: " & hex8 (v64(0)(63 downto 32));
report "at e8: " & hex8 (v64(0)(31 downto 0));
report "at f0: " & hex8 (v64(1)(63 downto 32));
report "at f8: " & hex8 (v64(1)(31 downto 0));
assert v64 (0 to 3) = (x"80_00_21_f8_80_00_21_f9",
x"80_00_21_fa_80_00_21_fb",
x"80_00_21_fc_80_00_21_fd",
x"80_00_21_fe_80_00_21_ff")
report "incorrect MBLT data 64" severity error;
assert err_8000 = 0
report "no 0x8000 error expected" severity error;
when 7 =>
-- Delayed DS
......
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