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VME64x core
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VME64x core
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9076173e
Commit
9076173e
authored
Nov 13, 2017
by
Maciej Lipinski
Committed by
Tristan Gingold
Nov 13, 2017
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[desc] small corrections to the description in the VME64xCore_Top.vhd fiel
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VME64xCore_Top.vhd
hdl/rtl/VME64xCore_Top.vhd
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hdl/rtl/VME64xCore_Top.vhd
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9076173e
...
@@ -40,19 +40,20 @@
...
@@ -40,19 +40,20 @@
-- The base address is setted by the Geographical lines.
-- The base address is setted by the Geographical lines.
-- The base address can't be setted by hand with the switches on the board.
-- The base address can't be setted by hand with the switches on the board.
-- If the core is used in an old VME system without GA lines, the core should
-- If the core is used in an old VME system without GA lines, the core should
-- be provided of a logic that detects if GA = "11111" and if it is the base
-- be provided with a logic that detects if GA = "11111" and if it is the base
-- address of the module should be derived from the switches on the board.
-- address of the module, this logic should derive the GA from the switches on
-- the board.
-- All the VMEbus's asynchronous signals must be sampled 2 or 3 times to avoid
-- All the VMEbus's asynchronous signals must be sampled 2 or 3 times to avoid
-- metastability problem.
-- metastability problem.
-- All the output signals on the WB bus are registered.
-- All the output signals on the WB bus are registered.
-- The Input signals from the WB bus aren't registered indeed the WB is a
-- The Input signals from the WB bus aren't registered indeed the WB is a
-- synchronous protocol and some registers in the WB side will introduce a
-- synchronous protocol and some registers in the WB side will introduce a
-- delay that make impossible reproduce the WB PIPELINED protocol.
-- delay that make impossible reproduce the WB PIPELINED protocol.
-- The WB Slave application must work
at the same frequency of
this vme64x
-- The WB Slave application must work
with the same frequency as
this vme64x
-- core.
-- core.
-- The main component
is the VME_bus on the left of the block diagram. Inside
-- The main component
of this core is the VME_bus on the left in the block
--
this component you can find the main finite state machine that coordinates
--
diagram. Inside this component you can find the main finite state machine
-- all the synchronisms.
--
that coordinates
all the synchronisms.
-- The WB protocol is more faster than the VME protocol so to make independent
-- The WB protocol is more faster than the VME protocol so to make independent
-- the two protocols a FIFO memory can be introduced.
-- the two protocols a FIFO memory can be introduced.
-- The FIFO is necessary only during 2eSST access mode.
-- The FIFO is necessary only during 2eSST access mode.
...
@@ -71,7 +72,7 @@
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@@ -71,7 +72,7 @@
-- interrupt request on the VMEbus. This component acts also during the
-- interrupt request on the VMEbus. This component acts also during the
-- Interrupt acknowledge cycle, sending the status/ID to the Interrupt
-- Interrupt acknowledge cycle, sending the status/ID to the Interrupt
-- handler.
-- handler.
-- Inside each component
is possible to read a more detailed description
.
-- Inside each component
, a detailed description is provided
.
-- Access modes supported:
-- Access modes supported:
-- http://www.ohwr.org/projects/vme64x-core/repository/changes/trunk/
-- http://www.ohwr.org/projects/vme64x-core/repository/changes/trunk/
-- documentation/user_guides/VME_access_modes.pdf
-- documentation/user_guides/VME_access_modes.pdf
...
...
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