Commit 8f3d4b8f authored by Tristan Gingold's avatar Tristan Gingold

Ready to have vme_lword FF in IOBs.

parent 18f12bb4
...@@ -153,6 +153,7 @@ architecture RTL of VME_bus is ...@@ -153,6 +153,7 @@ architecture RTL of VME_bus is
-- first one can be placed in the IOBs. -- first one can be placed in the IOBs.
signal s_vme_addr_reg : std_logic_vector(31 downto 1); signal s_vme_addr_reg : std_logic_vector(31 downto 1);
signal s_vme_data_reg : std_logic_vector(31 downto 0); signal s_vme_data_reg : std_logic_vector(31 downto 0);
signal s_vme_lword_n_reg : std_logic;
type t_addressingType is ( type t_addressingType is (
A24, A24,
...@@ -332,7 +333,6 @@ begin ...@@ -332,7 +333,6 @@ begin
s_err <= '0'; s_err <= '0';
s_ADDRlatched <= (others => '0'); s_ADDRlatched <= (others => '0');
s_LWORDlatched_n <= '0';
s_AMlatched <= (others => '0'); s_AMlatched <= (others => '0');
s_vme_addr_reg <= (others => '0'); s_vme_addr_reg <= (others => '0');
...@@ -389,6 +389,8 @@ begin ...@@ -389,6 +389,8 @@ begin
null; -- A32 null; -- A32
end case; end case;
s_vme_lword_n_reg <= s_LWORDlatched_n;
-- Address is not yet decoded. -- Address is not yet decoded.
s_card_sel <= '0'; s_card_sel <= '0';
s_conf_sel <= '0'; s_conf_sel <= '0';
...@@ -499,7 +501,7 @@ begin ...@@ -499,7 +501,7 @@ begin
-- Read DATA (which are stable) -- Read DATA (which are stable)
s_locDataIn(63 downto 33) <= VME_ADDR_i; s_locDataIn(63 downto 33) <= VME_ADDR_i;
s_locDataIn(32) <= VME_LWORD_n_i; s_LWORDlatched_n <= VME_LWORD_n_i;
s_vme_data_reg <= VME_DATA_i; s_vme_data_reg <= VME_DATA_i;
else else
s_mainFSMstate <= LATCH_DS; s_mainFSMstate <= LATCH_DS;
...@@ -511,14 +513,15 @@ begin ...@@ -511,14 +513,15 @@ begin
VME_ADDR_DIR_o <= (s_is_d64) and s_WRITElatched_n; VME_ADDR_DIR_o <= (s_is_d64) and s_WRITElatched_n;
s_dataPhase <= s_dataPhase; s_dataPhase <= s_dataPhase;
s_locDataIn(32) <= s_LWORDlatched_n;
s_locDataIn(31 downto 0) <= s_vme_data_reg; s_locDataIn(31 downto 0) <= s_vme_data_reg;
if s_LWORDlatched_n = '1' and s_vme_addr_reg(1) = '0' then if s_vme_lword_n_reg = '1' and s_vme_addr_reg(1) = '0' then
-- Word/byte access with A1=0 -- Word/byte access with A1=0
s_locDataIn(31 downto 16) <= s_vme_data_reg(15 downto 0); s_locDataIn(31 downto 16) <= s_vme_data_reg(15 downto 0);
end if; end if;
-- Translate DS+LWORD+ADDR to WB byte selects -- Translate DS+LWORD+ADDR to WB byte selects
if s_LWORDlatched_n = '0' then if s_vme_lword_n_reg = '0' then
sel_o <= "1111"; sel_o <= "1111";
else else
sel_o <= "0000"; sel_o <= "0000";
...@@ -536,7 +539,7 @@ begin ...@@ -536,7 +539,7 @@ begin
-- A Slave MUST NOT respond with a falling edge on DTACK* during -- A Slave MUST NOT respond with a falling edge on DTACK* during
-- an unaligned transfer cycle, if it does not have UAT -- an unaligned transfer cycle, if it does not have UAT
-- capability. -- capability.
if s_LWORDlatched_n = '0' and s_DSlatched_n /= "00" then if s_vme_lword_n_reg = '0' and s_DSlatched_n /= "00" then
-- unaligned. -- unaligned.
s_mainFSMstate <= WAIT_END; s_mainFSMstate <= WAIT_END;
else else
...@@ -588,7 +591,7 @@ begin ...@@ -588,7 +591,7 @@ begin
s_locDataOut(63 downto 32) <= s_locDataOut(31 downto 0); s_locDataOut(63 downto 32) <= s_locDataOut(31 downto 0);
s_locDataOut(31 downto 0) <= (others => '0'); s_locDataOut(31 downto 0) <= (others => '0');
if s_card_sel = '1' then if s_card_sel = '1' then
if s_LWORDlatched_n = '1' and s_vme_addr_reg(1) = '0' then if s_vme_lword_n_reg = '1' and s_vme_addr_reg(1) = '0' then
-- Word/byte access with A1 = 0 -- Word/byte access with A1 = 0
s_locDataOut(15 downto 0) <= dat_i(31 downto 16); s_locDataOut(15 downto 0) <= dat_i(31 downto 16);
else else
...@@ -678,7 +681,7 @@ begin ...@@ -678,7 +681,7 @@ begin
VME_DTACK_OE_o <= '1'; VME_DTACK_OE_o <= '1';
VME_ADDR_DIR_o <= (s_is_d64) and s_WRITElatched_n; VME_ADDR_DIR_o <= (s_is_d64) and s_WRITElatched_n;
if s_LWORDlatched_n = '0' then if s_vme_lword_n_reg = '0' then
if s_transferType = MBLT then if s_transferType = MBLT then
-- 64 bit -- 64 bit
addr_word_incr := 4; addr_word_incr := 4;
......
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