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VME64x core
Commits
8e5d875f
Commit
8e5d875f
authored
Sep 29, 2017
by
Tristan Gingold
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vme_bus: latch DS and decode address in parallel. Add testcase.
parent
affa1990
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3 changed files
with
52 additions
and
7 deletions
+52
-7
VME64x_v2_specs.txt
documentation/specifications/VME64x_v2_specs.txt
+0
-1
VME_bus.vhd
hdl/vme64x-core/rtl/VME_bus.vhd
+23
-5
top_tb.vhd
hdl/vme64x-core/sim/simple_tb/top_tb.vhd
+29
-1
No files found.
documentation/specifications/VME64x_v2_specs.txt
View file @
8e5d875f
...
@@ -92,7 +92,6 @@ TODO:
...
@@ -92,7 +92,6 @@ TODO:
* Stick DFSR and XAM to 0
* Stick DFSR and XAM to 0
* Put FF in IOB for all VME lines
* Put FF in IOB for all VME lines
* Make decoding and DS in parallel
VITAL-1 rules
VITAL-1 rules
...
...
hdl/vme64x-core/rtl/VME_bus.vhd
View file @
8e5d875f
...
@@ -327,8 +327,6 @@ begin
...
@@ -327,8 +327,6 @@ begin
VME_ADDR_DIR_o
<=
'0'
;
VME_ADDR_DIR_o
<=
'0'
;
VME_BERR_n_o
<=
'1'
;
VME_BERR_n_o
<=
'1'
;
s_DS_latch_count
<=
"000"
;
case
s_mainFSMstate
is
case
s_mainFSMstate
is
when
IDLE
=>
when
IDLE
=>
...
@@ -369,6 +367,9 @@ begin
...
@@ -369,6 +367,9 @@ begin
s_card_sel
<=
'0'
;
s_card_sel
<=
'0'
;
s_conf_sel
<=
'0'
;
s_conf_sel
<=
'0'
;
-- DS latch counter
s_DS_latch_count
<=
to_unsigned
(
num_latchDS
,
3
);
-- VITA-1 Rule 2.6
-- VITA-1 Rule 2.6
-- A Slave MUST NOT respond with a falling edge on DTACK* during
-- A Slave MUST NOT respond with a falling edge on DTACK* during
-- an unaligned transfer cycle, if it does not have UAT
-- an unaligned transfer cycle, if it does not have UAT
...
@@ -392,13 +393,26 @@ begin
...
@@ -392,13 +393,26 @@ begin
when
DECODE_ACCESS
=>
when
DECODE_ACCESS
=>
-- check if this slave board is addressed.
-- check if this slave board is addressed.
-- Wait for DS in parallel.
if
VME_DS_n_i
/=
"11"
then
s_WRITElatched_n
<=
VME_WRITE_n_i
;
if
s_DS_latch_count
/=
0
then
s_DS_latch_count
<=
s_DS_latch_count
-
1
;
end
if
;
end
if
;
if
decode_done_i
=
'1'
then
if
decode_done_i
=
'1'
then
if
decode_sel_i
=
'1'
and
module_enable_i
=
'1'
then
if
decode_sel_i
=
'1'
and
module_enable_i
=
'1'
then
-- card_sel = '1' it means WB application addressed
-- card_sel = '1' it means WB application addressed
s_card_sel
<=
'1'
;
s_card_sel
<=
'1'
;
s_mainFSMstate
<=
WAIT_FOR_DS
;
-- Keep only the local part of the address
-- Keep only the local part of the address
s_ADDRlatched
<=
addr_decoder_i
(
31
downto
1
);
s_ADDRlatched
<=
addr_decoder_i
(
31
downto
1
);
if
VME_DS_n_i
=
"11"
then
s_mainFSMstate
<=
WAIT_FOR_DS
;
else
s_mainFSMstate
<=
LATCH_DS
;
end
if
;
else
else
-- another board will answer; wait here the rising edge on
-- another board will answer; wait here the rising edge on
-- VME_AS_i (done by top if).
-- VME_AS_i (done by top if).
...
@@ -411,11 +425,12 @@ begin
...
@@ -411,11 +425,12 @@ begin
when
WAIT_FOR_DS
=>
when
WAIT_FOR_DS
=>
-- wait until DS /= "11"
-- wait until DS /= "11"
-- Note: before entering this state, s_DS_latch_count must be set.
if
VME_DS_n_i
/=
"11"
then
if
VME_DS_n_i
/=
"11"
then
s_WRITElatched_n
<=
VME_WRITE_n_i
;
s_WRITElatched_n
<=
VME_WRITE_n_i
;
s_DS_latch_count
<=
s_DS_latch_count
-
1
;
s_mainFSMstate
<=
LATCH_DS
;
s_mainFSMstate
<=
LATCH_DS
;
s_DS_latch_count
<=
to_unsigned
(
num_latchDS
-
1
,
3
);
else
else
s_mainFSMstate
<=
WAIT_FOR_DS
;
s_mainFSMstate
<=
WAIT_FOR_DS
;
end
if
;
end
if
;
...
@@ -601,7 +616,10 @@ begin
...
@@ -601,7 +616,10 @@ begin
-- Rescind DTACK.
-- Rescind DTACK.
VME_DTACK_n_o
<=
'1'
;
VME_DTACK_n_o
<=
'1'
;
-- DS latch counter
s_DS_latch_count
<=
to_unsigned
(
num_latchDS
,
3
);
if
s_transferType
=
SINGLE
then
if
s_transferType
=
SINGLE
then
-- Cycle should be finished, but allow another access at
-- Cycle should be finished, but allow another access at
-- the same address (RMW).
-- the same address (RMW).
...
...
hdl/vme64x-core/sim/simple_tb/top_tb.vhd
View file @
8e5d875f
entity
top_tb
is
entity
top_tb
is
generic
(
scenario
:
natural
range
0
to
6
:
=
1
);
generic
(
scenario
:
natural
range
0
to
7
:
=
7
);
end
;
end
;
library
ieee
;
library
ieee
;
...
@@ -1230,6 +1230,34 @@ begin
...
@@ -1230,6 +1230,34 @@ begin
x"01_23_45_67_89_ab_cd_ef"
,
x"01_23_45_67_89_ab_cd_ef"
,
x"fe_dc_ba_98_76_54_32_10"
)
x"fe_dc_ba_98_76_54_32_10"
)
report
"incorrect MBLT data 64 r/w"
severity
error
;
report
"incorrect MBLT data 64 r/w"
severity
error
;
when
7
=>
-- Delayed DS
-- Set ADER
write8_conf
(
x"7_ff63"
,
x"67"
);
write8_conf
(
x"7_ff6f"
,
c_AM_A32
&
"00"
);
-- Enable card
write8_conf
(
x"7_fffb"
,
b"0001_0000"
);
-- Read 16 at 0x0100
VME_LWORD_n_i
<=
'1'
;
read_setup_addr
(
x"67_00_01_00"
,
c_AM_A32
);
wait
for
50
ns
;
VME_DS_n_i
<=
"0X"
;
wait
for
20
ns
;
-- Constraint 13.
VME_DS_n_i
<=
"00"
;
read_wait_dtack
;
if
bus_timer
=
'0'
then
d16
:
=
VME_DATA_o
(
15
downto
0
);
else
d16
:
=
(
others
=>
'X'
);
end
if
;
read_release
;
assert
d16
=
x"8765"
report
"bad read16 with delayed DS"
severity
error
;
end
case
;
end
case
;
wait
for
4
*
g_CLOCK_PERIOD
*
1
ns
;
wait
for
4
*
g_CLOCK_PERIOD
*
1
ns
;
...
...
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