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VME64x core
Commit 8a4cc17f authored by Tristan Gingold's avatar Tristan Gingold
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vme_bus: make dtack output explicitely latched.

parent 65121f5a
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hdl/rtl/vme_bus.vhd
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-- 1 Tclk saved @CTT -> REQ
-- 1 Tclk saved during WRITE when MEM_REQ -> DTACK LOW
-- This means that single access write, MBLT write should have intact speed (TEST!)
-- Next step is achieving read when MEM_REQ -> DTACK LOW with a saved TCLK which
-- should bring signle read to intact speed, and slightly boost MBLT (1st read only)
-- (Later might think of something similar for MBLT read )
-- 2 more cycles saved during MBLT added s1 and s2
-- Attempting to save 1 more TCLK between the data is prefetched and DTACK is driven down DONE
-- Attempting to save 1 tclk during single access read DONE ()
-- Attempting to start prefetch earlier than in v07
-- Spitting out data as early as possible on vme bus from different states depending on master read ack (DONE)
-- Rate: 34.424901 MB/sec
-- OK: DMA read
-- Rate: 26.073180 MB/sec
-- OK: DMA write
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- CERN (BE-CO-HT) -- CERN (BE-CO-HT)
-- VME64x Core -- VME64x Core
...@@ -148,6 +123,9 @@ architecture rtl of vme_bus is ...@@ -148,6 +123,9 @@ architecture rtl of vme_bus is
signal vme_odff_addr_dir : std_logic; signal vme_odff_addr_dir : std_logic;
signal vme_odff_data_dir : std_logic; signal vme_odff_data_dir : std_logic;
signal vme_odff_dtack_n : std_logic;
signal vme_odff_dtack_oe : std_logic;
-- Register containing the address. Initialized from VME, adjusted -- Register containing the address. Initialized from VME, adjusted
-- by address decoder, and incremented during DMA. -- by address decoder, and incremented during DMA.
signal addr_reg : std_logic_vector(31 downto 0); signal addr_reg : std_logic_vector(31 downto 0);
...@@ -323,8 +301,8 @@ begin ...@@ -323,8 +301,8 @@ begin
decode_start_o <= '0'; decode_start_o <= '0';
-- VME -- VME
vme_dtack_oe_o <= '0'; vme_odff_dtack_oe <= '0';
vme_dtack_n_o <= '1'; vme_odff_dtack_n <= '1';
vme_odff_data_dir <= '0'; vme_odff_data_dir <= '0';
vme_odff_addr_dir <= '0'; vme_odff_addr_dir <= '0';
vme_odff_lword_n <= '0'; vme_odff_lword_n <= '0';
...@@ -350,8 +328,8 @@ begin ...@@ -350,8 +328,8 @@ begin
else else
s_conf_req <= '0'; s_conf_req <= '0';
decode_start_o <= '0'; decode_start_o <= '0';
vme_dtack_oe_o <= '0'; vme_odff_dtack_oe <= '0';
vme_dtack_n_o <= '1'; vme_odff_dtack_n <= '1';
vme_berr_n_o <= '1'; vme_berr_n_o <= '1';
vme_iackout_n_o <= '1'; vme_iackout_n_o <= '1';
irq_ack_o <= '0'; irq_ack_o <= '0';
...@@ -454,8 +432,8 @@ begin ...@@ -454,8 +432,8 @@ begin
when WAIT_FOR_DS => when WAIT_FOR_DS =>
-- wait until DS /= "11" -- wait until DS /= "11"
-- Note: before entering this state, s_DS_latch_count must be set. -- Note: before entering this state, s_DS_latch_count must be set.
vme_dtack_oe_o <= '1'; vme_odff_dtack_oe <= '1';
vme_dtack_n_o <= '1'; vme_odff_dtack_n <= '1';
if s_transferType = MBLT if s_transferType = MBLT
and s_MBLT_Data = '1' and s_MBLT_Data = '1'
...@@ -498,8 +476,8 @@ begin ...@@ -498,8 +476,8 @@ begin
-- Already assert dtack (assume that data have been on the -- Already assert dtack (assume that data have been on the
-- vme bus for at least one cycle). -- vme bus for at least one cycle).
vme_dtack_oe_o <= '1'; vme_odff_dtack_oe <= '1';
vme_dtack_n_o <= s_err; vme_odff_dtack_n <= s_err;
s_mainFSMstate <= DTACK_LOW; s_mainFSMstate <= DTACK_LOW;
else else
...@@ -515,8 +493,8 @@ begin ...@@ -515,8 +493,8 @@ begin
when LATCH_DS => when LATCH_DS =>
-- This state is necessary indeed the VME master can assert the -- This state is necessary indeed the VME master can assert the
-- DS lines not at the same time. -- DS lines not at the same time.
vme_dtack_oe_o <= '1'; vme_odff_dtack_oe <= '1';
vme_dtack_n_o <= '1'; vme_odff_dtack_n <= '1';
-- ANSI/VITA 1-1994 Rule 2.53a -- ANSI/VITA 1-1994 Rule 2.53a
-- During all read cycles [...], the responding slave MUST NOT -- During all read cycles [...], the responding slave MUST NOT
...@@ -556,8 +534,8 @@ begin ...@@ -556,8 +534,8 @@ begin
end if; end if;
when CHECK_TRANSFER_TYPE => when CHECK_TRANSFER_TYPE =>
vme_dtack_oe_o <= '1'; vme_odff_dtack_oe <= '1';
vme_dtack_n_o <= '1'; vme_odff_dtack_n <= '1';
vme_odff_data_dir <= vme_idff_write_n; vme_odff_data_dir <= vme_idff_write_n;
-- vme_addr is an output during MBLT *read* data transfer. -- vme_addr is an output during MBLT *read* data transfer.
...@@ -581,8 +559,8 @@ begin ...@@ -581,8 +559,8 @@ begin
when DATA_TO_BUS => when DATA_TO_BUS =>
-- Update what WB FSM prepared -- Update what WB FSM prepared
vme_dtack_oe_o <= '1'; vme_odff_dtack_oe <= '1';
vme_dtack_n_o <= '1'; vme_odff_dtack_n <= '1';
if s_conf_sel = '1' or s_wb_done = '1' or s_irq_sel = '1' then if s_conf_sel = '1' or s_wb_done = '1' or s_irq_sel = '1' then
vme_odff_data_dir <= vme_idff_write_n; vme_odff_data_dir <= vme_idff_write_n;
...@@ -607,15 +585,15 @@ begin ...@@ -607,15 +585,15 @@ begin
when DTACK_LOW => when DTACK_LOW =>
-- Set /DTACK, wait until /DS[1:0] are released. -- Set /DTACK, wait until /DS[1:0] are released.
vme_dtack_oe_o <= '1'; vme_odff_dtack_oe <= '1';
vme_dtack_n_o <= '1'; vme_odff_dtack_n <= '1';
vme_odff_data_dir <= vme_idff_write_n; vme_odff_data_dir <= vme_idff_write_n;
-- Set DTACK (or retry or berr) -- Set DTACK (or retry or berr)
if s_card_sel = '1' and s_err = '1' then if s_card_sel = '1' and s_err = '1' then
vme_berr_n_o <= '0'; vme_berr_n_o <= '0';
else else
vme_dtack_n_o <= '0'; vme_odff_dtack_n <= '0';
end if; end if;
-- ANSI/VITA 1-1994 Rule 2.57 -- ANSI/VITA 1-1994 Rule 2.57
...@@ -626,7 +604,7 @@ begin ...@@ -626,7 +604,7 @@ begin
vme_berr_n_o <= '1'; vme_berr_n_o <= '1';
-- Rescind DTACK. -- Rescind DTACK.
vme_dtack_n_o <= '1'; vme_odff_dtack_n <= '1';
-- DS latch counter -- DS latch counter
s_DS_latch_count <= to_unsigned (c_num_latchDS, 3); s_DS_latch_count <= to_unsigned (c_num_latchDS, 3);
...@@ -713,6 +691,7 @@ begin ...@@ -713,6 +691,7 @@ begin
wb_stb_o <= '0'; wb_stb_o <= '0';
wb_sel_o <= "0000"; wb_sel_o <= "0000";
wb_we_o <= '0'; wb_we_o <= '0';
addr_reg <= (others => '0');
s_err <= '0'; s_err <= '0';
s_wb_done <= '0'; s_wb_done <= '0';
...@@ -950,4 +929,6 @@ begin ...@@ -950,4 +929,6 @@ begin
vme_data_o <= vme_odff_data; vme_data_o <= vme_odff_data;
vme_lword_n_o <= vme_odff_lword_n; vme_lword_n_o <= vme_odff_lword_n;
vme_dtack_n_o <= vme_odff_dtack_n;
vme_dtack_oe_o <= vme_odff_dtack_oe;
end rtl; end rtl;
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