rtl: add g_ASYNC_DTACK generic to disable asynchronous dtack.

Fix issue#18

rtl: add g_ASYNC_DTACK generic to disable asynchronous dtack.
Fix issue#18
8866c64a · Tristan Gingold · 0b143861 · 8866c64a · 8866c64a · 8866c64a
Commit 8866c64a authored Feb 03, 2021 by Tristan Gingold
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vme64x_core.vhd hdl/rtl/vme64x_core.vhd +2 -0

vme_bus.vhd hdl/rtl/vme_bus.vhd +2 -1

xvme64x_core.vhd hdl/rtl/xvme64x_core.vhd +9 -0

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--- a/hdl/rtl/vme64x_core.vhd
+++ b/hdl/rtl/vme64x_core.vhd
@@ -17,6 +17,7 @@ entity vme64x_core is
    g_USER_CSR_EXT    : boolean := false;
    g_VME32           : boolean := true;
    g_VME_2e          : boolean := False;
+    g_ASYNC_DTACK     : boolean := False;
    g_WB_GRANULARITY  : t_wishbone_address_granularity;
    g_MANUFACTURER_ID : std_logic_vector(23 downto 0);
    g_BOARD_ID        : std_logic_vector(31 downto 0);
@@ -119,6 +120,7 @@ begin
      g_WB_GRANULARITY   => g_WB_GRANULARITY,
      g_WB_MODE          => CLASSIC,
      g_VME_2e           => g_VME_2e,
+      g_ASYNC_DTACK      => g_ASYNC_DTACK,
      g_MANUFACTURER_ID  => g_MANUFACTURER_ID,
      g_BOARD_ID         => g_BOARD_ID,
      g_REVISION_ID      => g_REVISION_ID,

--- a/hdl/rtl/vme_bus.vhd
+++ b/hdl/rtl/vme_bus.vhd
@@ -37,6 +37,7 @@ entity vme_bus is
    g_CLOCK_PERIOD    : integer;
    g_VME32           : boolean;
    g_VME_2E          : boolean;
+    g_ASYNC_DTACK     : boolean;
    g_WB_GRANULARITY  : t_wishbone_address_granularity;
    g_WB_MODE         : t_wishbone_interface_mode
  );
@@ -1187,7 +1188,7 @@ begin

  process (vme_odff_dtack_n, vme_nsync_ds_n_i, vme_dtack_async_ctrl)
  begin
-    if vme_dtack_async_ctrl = '0' then
+    if vme_dtack_async_ctrl = '0' or not g_ASYNC_DTACK then
      vme_dtack_n_o <= vme_odff_dtack_n;
    else
      --  Asserted (to 0) as soon as one ds signal is asserted (to 0).

--- a/hdl/rtl/xvme64x_core.vhd
+++ b/hdl/rtl/xvme64x_core.vhd
@@ -67,6 +67,14 @@ entity xvme64x_core is
    --  Do not forget to assign g_DECODER if set to True.
    g_VME_2e          : boolean := False;

+    --  If True, allows to directly drives DTACK from DS inputs.
+    --  This improves performance as synchronizers and registers are skipped.
+    --  But it then requires a minimal frequency, otherwise the master may
+    --  change the bus before the slave latched the data.
+    --  No problems have been reported when the clock is faster than 62.5Mhz.
+    --  Problems have been repored for clock slower than 40Mhz.
+    g_ASYNC_DTACK     : boolean := False;
+
    -- Address granularity on the WB bus. Value can be:
    -- WORD: VME address bits 31:2 are translated to WB address bits 29:0,
    --       the WB data represents bytes for VME address bits 1:0.
@@ -326,6 +334,7 @@ begin
      g_CLOCK_PERIOD   => g_CLOCK_PERIOD,
      g_VME32          => g_VME32,
      g_VME_2E         => g_VME_2E,
+      g_ASYNC_DTACK    => g_ASYNC_DTACK,
      g_WB_GRANULARITY => g_WB_GRANULARITY,
      g_WB_MODE        => g_WB_MODE)
    port map (