Skip to content

V
VME64x core
Commit 845dd9b5 authored by Tristan Gingold's avatar Tristan Gingold
Browse files
Options

Fix function decoding, fix minor issues to get first simulation

parent 72eff0ad
Hide whitespace changes
Inline Side-by-side
Showing with 52 additions and 65 deletions
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @ 845dd9b5
...@@ -267,7 +267,7 @@ entity VME64xCore_Top is ...@@ -267,7 +267,7 @@ entity VME64xCore_Top is
user_cr_data_i : in std_logic_vector( 7 downto 0) := (others => '0'); user_cr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
-- Functions -- Functions
function_o : out std_logic_vector( 3 downto 0); function_o : out std_logic_vector( 2 downto 0);
f0_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0'); f0_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f1_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0'); f1_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
...@@ -339,7 +339,7 @@ architecture RTL of VME64xCore_Top is ...@@ -339,7 +339,7 @@ architecture RTL of VME64xCore_Top is
signal s_addr_decoder_o : std_logic_vector(63 downto 0); signal s_addr_decoder_o : std_logic_vector(63 downto 0);
signal s_decode : std_logic; signal s_decode : std_logic;
signal s_sel : std_logic; signal s_sel : std_logic;
signal s_function : std_logic_vector( 7 downto 0); signal s_function : std_logic_vector( 2 downto 0);
signal s_am : std_logic_vector( 5 downto 0); signal s_am : std_logic_vector( 5 downto 0);
signal s_xam : std_logic_vector( 7 downto 0); signal s_xam : std_logic_vector( 7 downto 0);
...@@ -457,7 +457,6 @@ begin ...@@ -457,7 +457,6 @@ begin
am_o => s_am, am_o => s_am,
xam_o => s_xam, xam_o => s_xam,
sel_i => s_sel, sel_i => s_sel,
function_i => s_function,
-- CR/CSR signals -- CR/CSR signals
cr_csr_addr_o => s_cr_csr_addr, cr_csr_addr_o => s_cr_csr_addr,
......
hdl/vme64x-core/rtl/VME_Funct_Match.vhd
View file @ 845dd9b5
...@@ -47,6 +47,7 @@ entity VME_Funct_Match is ...@@ -47,6 +47,7 @@ entity VME_Funct_Match is
rst_n_i : in std_logic; rst_n_i : in std_logic;
addr_i : in std_logic_vector(63 downto 0); addr_i : in std_logic_vector(63 downto 0);
-- Sub-address of the function (the part not masked by adem).
addr_o : out std_logic_vector(63 downto 0); addr_o : out std_logic_vector(63 downto 0);
decode_i : in std_logic; decode_i : in std_logic;
am_i : in std_logic_vector( 5 downto 0); am_i : in std_logic_vector( 5 downto 0);
...@@ -55,8 +56,10 @@ entity VME_Funct_Match is ...@@ -55,8 +56,10 @@ entity VME_Funct_Match is
ader_i : in t_ader_array(0 to 7); ader_i : in t_ader_array(0 to 7);
dfs_adem_i : in t_adem_array(0 to 7); dfs_adem_i : in t_adem_array(0 to 7);
-- Set when a function is selected (ie function_o is valid).
sel_o : out std_logic; sel_o : out std_logic;
function_o : out std_logic_vector( 3 downto 0) -- Selected function.
function_o : out std_logic_vector( 2 downto 0)
); );
end VME_Funct_Match; end VME_Funct_Match;
...@@ -129,12 +132,12 @@ architecture rtl of VME_Funct_Match is ...@@ -129,12 +132,12 @@ architecture rtl of VME_Funct_Match is
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Generate XAM enabled flag -- Generate XAM enabled flag
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- c_XAM_ENA is true when any XAMCAP > 0 to conditionally enable the -- c_XAM_ENA is true when any XAMCAP /= 0 to conditionally enable the
-- generation of the XAM lookup table. -- generation of the XAM lookup table.
function f_xam_ena return boolean is function f_xam_ena return boolean is
begin begin
for i in 0 to 7 loop for i in 0 to 7 loop
if unsigned(g_XAMCAP(i)) > 0 then if g_XAMCAP(i) /= (255 downto 0 => '0') then
return true; return true;
end if; end if;
end loop; end loop;
...@@ -146,19 +149,21 @@ architecture rtl of VME_Funct_Match is ...@@ -146,19 +149,21 @@ architecture rtl of VME_Funct_Match is
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Generate function enabled vector -- Generate function enabled vector
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- c_ENABLED is true when a function's AMCAP > 0 and the previous
-- function does not have the EFM bit set.
function f_function_ena return std_logic_vector is function f_function_ena return std_logic_vector is
variable ena : std_logic_vector(7 downto 0) := (others => '0'); variable ena : std_logic_vector(7 downto 0) := (others => '0');
begin begin
for i in 0 to 7 loop for i in 0 to 7 loop
if unsigned(g_AMCAP(i)) > 0 and g_ADEM(i-1)(c_ADEM_EFM) = '0' then if g_AMCAP(i) /= (63 downto 0 => '0')
and (i = 0 or g_ADEM(i-1)(c_ADEM_EFM) = '0')
then
ena(i) := '1'; ena(i) := '1';
end if; end if;
end loop; end loop;
return ena; return ena;
end function; end function;
-- c_ENABLED is true when a function's AMCAP /= 0 and the previous
-- function does not have the EFM bit set.
constant c_ENABLED : std_logic_vector(7 downto 0) := f_function_ena; constant c_ENABLED : std_logic_vector(7 downto 0) := f_function_ena;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
...@@ -167,6 +172,8 @@ architecture rtl of VME_Funct_Match is ...@@ -167,6 +172,8 @@ architecture rtl of VME_Funct_Match is
function f_efm_efd (v : integer) return std_logic_vector is function f_efm_efd (v : integer) return std_logic_vector is
variable e : std_logic_vector(7 downto 0) := (others => '0'); variable e : std_logic_vector(7 downto 0) := (others => '0');
begin begin
-- EFM and EFD are not meaningful for function 7 (as there is no next
-- function).
for i in 0 to 6 loop for i in 0 to 6 loop
e(i) := g_ADEM(i)(v); e(i) := g_ADEM(i)(v);
end loop; end loop;
...@@ -175,35 +182,31 @@ architecture rtl of VME_Funct_Match is ...@@ -175,35 +182,31 @@ architecture rtl of VME_Funct_Match is
constant c_EFM : std_logic_vector(7 downto 0) := f_efm_efd(c_ADEM_EFM); constant c_EFM : std_logic_vector(7 downto 0) := f_efm_efd(c_ADEM_EFM);
constant c_EFD : std_logic_vector(7 downto 0) := f_efm_efd(c_ADEM_EFD); constant c_EFD : std_logic_vector(7 downto 0) := f_efm_efd(c_ADEM_EFD);
constant c_EFD_ENA : boolean := unsigned(c_EFD) > 0; constant c_EFD_ENA : boolean := c_EFD /= x"00";
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Generate EFD lookup table -- Generate EFD lookup table
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
type t_efd_lut is array (0 to 7) of std_logic_vector(7 downto 0); type t_efd_lut is array (0 to 7) of std_logic_vector(2 downto 0);
function f_gen_efd_lut return t_efd_lut is function f_gen_efd_lut return t_efd_lut is
variable lut : t_efd_lut; variable lut : t_efd_lut;
begin begin
for i in 0 to 7 loop lut(0) := "000";
for i in 1 to 7 loop
if g_ADEM(i-1)(c_ADEM_EFD) = '1' then if g_ADEM(i-1)(c_ADEM_EFD) = '1' then
for j in i-1 downto 0 loop lut(i) := lut(i - 1);
if g_ADEM(j-1)(c_ADEM_EFD) = '0' then
lut(i) := std_logic_vector(to_unsigned(j, 8));
exit;
end if;
end loop;
else else
lut(i) := std_logic_vector(to_unsigned(i, 8)); lut(i) := std_logic_vector(to_unsigned(i, 3));
end if; end if;
end loop; end loop;
return lut; return lut;
end function; end function;
-- Map from function defined by address to real function. Handle extra
-- decoders.
constant c_EFD_LUT : t_efd_lut := f_gen_efd_lut; constant c_EFD_LUT : t_efd_lut := f_gen_efd_lut;
------------------------------------------------------------------------------
begin begin
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
...@@ -237,6 +240,7 @@ begin ...@@ -237,6 +240,7 @@ begin
-- Create 64-bit ADEM/ADER based on EFM and DFS setting -- Create 64-bit ADEM/ADER based on EFM and DFS setting
gen_efm_ena: if c_EFM(i) = '1' generate gen_efm_ena: if c_EFM(i) = '1' generate
-- Extra mask
gen_dfs_ena: if g_ADEM(i)(c_ADEM_DFS) = '1' generate gen_dfs_ena: if g_ADEM(i)(c_ADEM_DFS) = '1' generate
s_adem(i) <= dfs_adem_i(i+1) & dfs_adem_i(i)(c_ADEM_M) & c_ADEM_M_PAD; s_adem(i) <= dfs_adem_i(i+1) & dfs_adem_i(i)(c_ADEM_M) & c_ADEM_M_PAD;
end generate; end generate;
...@@ -261,13 +265,13 @@ begin ...@@ -261,13 +265,13 @@ begin
end generate; end generate;
process (ader_i(i), am_i, xam_i) begin process (ader_i(i), am_i, xam_i) begin
if ader_i(i)(c_ADER_XAM_MODE) then if ader_i(i)(c_ADER_XAM_MODE) = '1' then
s_ader(i)(31 downto 0) <= ader_i(i)(c_ADER_C_XAM) & c_ADER_C_XAM_PAD; s_ader(i)(31 downto 0) <= ader_i(i)(c_ADER_C_XAM) & c_ADER_C_XAM_PAD;
if ader_i(i)(c_ADER_XAM) = xam_i then if ader_i(i)(c_ADER_XAM) = xam_i then
s_am_match(i) <= '1'; s_am_match(i) <= '1';
else else
s_am_match(i) <= '1'; s_am_match(i) <= '0';
end if; end if;
else else
s_ader(i)(31 downto 0) <= ader_i(i)(c_ADER_C_AM) & c_ADER_C_AM_PAD; s_ader(i)(31 downto 0) <= ader_i(i)(c_ADER_C_AM) & c_ADER_C_AM_PAD;
...@@ -275,7 +279,7 @@ begin ...@@ -275,7 +279,7 @@ begin
if ader_i(i)(c_ADER_AM) = am_i then if ader_i(i)(c_ADER_AM) = am_i then
s_am_match(i) <= '1'; s_am_match(i) <= '1';
else else
s_am_match(i) <= '1'; s_am_match(i) <= '0';
end if; end if;
end if; end if;
end process; end process;
...@@ -353,7 +357,7 @@ begin ...@@ -353,7 +357,7 @@ begin
if rst_n_i = '0' then if rst_n_i = '0' then
addr_o <= (others => '0'); addr_o <= (others => '0');
else else
if decode_i then if decode_i = '1' then
addr_o <= addr_i and not s_adem_sel; addr_o <= addr_i and not s_adem_sel;
end if; end if;
end if; end if;
...@@ -363,42 +367,27 @@ begin ...@@ -363,42 +367,27 @@ begin
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- EFD decoder and output latch -- EFD decoder and output latch
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
gen_efd_ena: if c_EFD_ENA = true generate process (clk_i) begin
process (clk_i) begin if rising_edge(clk_i) then
if rising_edge(clk_i) then if rst_n_i = '0' then
if rst_n_i = '0' then function_o <= (others => '0');
function_o <= (others => '0'); else
else if decode_i = '1' then
if decode_i then sel_o <= '1';
case s_function_ena is case s_function_ena is
when "00000001" => function_o <= c_EFD_LUT(0); when "00000001" => function_o <= c_EFD_LUT(0);
when "00000010" => function_o <= c_EFD_LUT(1); when "00000010" => function_o <= c_EFD_LUT(1);
when "00000100" => function_o <= c_EFD_LUT(2); when "00000100" => function_o <= c_EFD_LUT(2);
when "00001000" => function_o <= c_EFD_LUT(3); when "00001000" => function_o <= c_EFD_LUT(3);
when "00010000" => function_o <= c_EFD_LUT(4); when "00010000" => function_o <= c_EFD_LUT(4);
when "00100000" => function_o <= c_EFD_LUT(5); when "00100000" => function_o <= c_EFD_LUT(5);
when "01000000" => function_o <= c_EFD_LUT(6); when "01000000" => function_o <= c_EFD_LUT(6);
when "10000000" => function_o <= c_EFD_LUT(7); when "10000000" => function_o <= c_EFD_LUT(7);
when others => function_o <= (others => '0'); when others => function_o <= (others => '0');
end case; sel_o <= '0';
end if; end case;
end if;
end if;
end process;
end generate;
gen_efd_dis: if c_EFD_ENA = false generate
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
function_o <= (others => '0');
else
if decode_i then
function_o <= s_function_ena;
end if;
end if; end if;
end if; end if;
end process; end if;
end generate; end process;
end rtl; end rtl;
hdl/vme64x-core/rtl/VME_bus.vhd
View file @ 845dd9b5
...@@ -121,7 +121,6 @@ entity VME_bus is ...@@ -121,7 +121,6 @@ entity VME_bus is
am_o : out std_logic_vector( 5 downto 0); am_o : out std_logic_vector( 5 downto 0);
xam_o : out std_logic_vector( 7 downto 0); xam_o : out std_logic_vector( 7 downto 0);
sel_i : in std_logic; sel_i : in std_logic;
function_i : in std_logic_vector( 7 downto 0);
--CR/CSR space signals: --CR/CSR space signals:
cr_csr_addr_o : out std_logic_vector(18 downto 2); cr_csr_addr_o : out std_logic_vector(18 downto 2);
......
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @ 845dd9b5
...@@ -384,7 +384,6 @@ package vme64x_pack is ...@@ -384,7 +384,6 @@ package vme64x_pack is
am_o : out std_logic_vector( 5 downto 0); am_o : out std_logic_vector( 5 downto 0);
xam_o : out std_logic_vector( 7 downto 0); xam_o : out std_logic_vector( 7 downto 0);
sel_i : in std_logic; sel_i : in std_logic;
function_i : in std_logic_vector( 3 downto 0);
cr_csr_addr_o : out std_logic_vector(18 downto 2); cr_csr_addr_o : out std_logic_vector(18 downto 2);
cr_csr_data_i : in std_logic_vector( 7 downto 0); cr_csr_data_i : in std_logic_vector( 7 downto 0);
cr_csr_data_o : out std_logic_vector( 7 downto 0); cr_csr_data_o : out std_logic_vector( 7 downto 0);
...@@ -412,7 +411,7 @@ package vme64x_pack is ...@@ -412,7 +411,7 @@ package vme64x_pack is
ader_i : in t_ader_array(0 to 7); ader_i : in t_ader_array(0 to 7);
dfs_adem_i : in t_adem_array(0 to 7); dfs_adem_i : in t_adem_array(0 to 7);
sel_o : out std_logic; sel_o : out std_logic;
function_o : out std_logic_vector( 3 downto 0) function_o : out std_logic_vector( 2 downto 0)
); );
end component VME_Funct_Match; end component VME_Funct_Match;
......
hdl/vme64x-core/rtl/xvme64x_core.vhd
View file @ 845dd9b5
...@@ -183,7 +183,7 @@ begin -- wrapper ...@@ -183,7 +183,7 @@ begin -- wrapper
U_Wrapped_VME : VME64xCore_Top U_Wrapped_VME : VME64xCore_Top
generic map ( generic map (
g_CLOCK => g_CLOCK_PERIOD, g_CLOCK_PERIOD => g_CLOCK_PERIOD,
g_WB_DATA_WIDTH => g_WB_DATA_WIDTH, g_WB_DATA_WIDTH => g_WB_DATA_WIDTH,
g_WB_ADDR_WIDTH => g_WB_ADDR_WIDTH, g_WB_ADDR_WIDTH => g_WB_ADDR_WIDTH,
g_MANUFACTURER_ID => g_MANUFACTURER_ID, g_MANUFACTURER_ID => g_MANUFACTURER_ID,
......
hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd
View file @ 845dd9b5
...@@ -34,6 +34,7 @@ library ieee; ...@@ -34,6 +34,7 @@ library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use work.wishbone_pkg.all; use work.wishbone_pkg.all;
use work.vme64x_pack.all;
package xvme64x_core_pkg is package xvme64x_core_pkg is
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment