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VME64x core
Commit 7e121be4 authored by Tristan Gingold's avatar Tristan Gingold
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Renaming of signals, remove some intermediate signals.

parent c3937071
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hdl/vme64x-core/rtl/VME_Wb_master.vhd
View file @ 7e121be4
...@@ -93,7 +93,7 @@ entity VME_Wb_master is ...@@ -93,7 +93,7 @@ entity VME_Wb_master is
rty_i : in std_logic; rty_i : in std_logic;
err_i : in std_logic; err_i : in std_logic;
cyc_o : out std_logic; cyc_o : out std_logic;
memReq_o : out std_logic; stb_o : out std_logic;
WBdata_o : out std_logic_vector(g_WB_DATA_WIDTH-1 downto 0); WBdata_o : out std_logic_vector(g_WB_DATA_WIDTH-1 downto 0);
wbData_i : in std_logic_vector(g_WB_DATA_WIDTH-1 downto 0); wbData_i : in std_logic_vector(g_WB_DATA_WIDTH-1 downto 0);
locAddr_o : out std_logic_vector(g_WB_ADDR_WIDTH-1 downto 0); locAddr_o : out std_logic_vector(g_WB_ADDR_WIDTH-1 downto 0);
...@@ -105,33 +105,31 @@ end VME_Wb_master; ...@@ -105,33 +105,31 @@ end VME_Wb_master;
architecture Behavioral of VME_Wb_master is architecture Behavioral of VME_Wb_master is
signal s_AckWithError : std_logic; signal s_AckWithError : std_logic;
signal s_cyc : std_logic;
begin begin
-- stb handler -- stb handler
process (clk_i) process (clk_i)
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if reset_i = '1' or (stall_i = '0' and s_cyc = '1') then if reset_i = '1' then
memReq_o <= '0'; stb_o <= '0';
elsif memReq_i = '1' and BERRcondition_i = '0' then cyc_o <= '0';
memReq_o <= '1'; else
end if; if memReq_i = '1' and BERRcondition_i = '0' then
end if; stb_o <= '1';
end process; cyc_o <= '1';
else
-- One pulse for stb_o
stb_o <= '0';
-- cyc_o handler -- But s_cyc is set for the whole cycle
process (clk_i) if memAckWB_i = '1' then
begin cyc_o <= '0';
if rising_edge(clk_i) then end if;
if reset_i = '1' or memAckWB_i = '1' then end if;
s_cyc <= '0';
elsif memReq_i = '1' and BERRcondition_i = '0' then
s_cyc <= '1';
end if; end if;
end if; end if;
end process; end process;
cyc_o <= s_cyc;
process (clk_i) process (clk_i)
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
......
hdl/vme64x-core/rtl/VME_bus.vhd
View file @ 7e121be4
...@@ -136,11 +136,6 @@ architecture RTL of VME_bus is ...@@ -136,11 +136,6 @@ architecture RTL of VME_bus is
signal s_rw : std_logic; signal s_rw : std_logic;
-- External buffer signals
signal s_dtackOE : std_logic;
signal s_dataDir : std_logic;
signal s_addrDir : std_logic;
-- Local data & address -- Local data & address
signal s_locDataIn : std_logic_vector(63 downto 0); signal s_locDataIn : std_logic_vector(63 downto 0);
signal s_locDataOut : std_logic_vector(63 downto 0); -- Local data signal s_locDataOut : std_logic_vector(63 downto 0); -- Local data
...@@ -215,7 +210,6 @@ architecture RTL of VME_bus is ...@@ -215,7 +210,6 @@ architecture RTL of VME_bus is
-- Main FSM signals -- Main FSM signals
signal s_mainFSMstate : t_mainFSMstates; signal s_mainFSMstate : t_mainFSMstates;
signal s_mainDTACK : std_logic; -- DTACK driving
signal s_memReq : std_logic; -- Global memory request signal s_memReq : std_logic; -- Global memory request
signal s_WBReq : std_logic; -- WB memory request signal s_WBReq : std_logic; -- WB memory request
signal s_dataPhase : std_logic; -- for MBLT signal s_dataPhase : std_logic; -- for MBLT
...@@ -270,12 +264,8 @@ begin ...@@ -270,12 +264,8 @@ begin
-- L | L | B to A L | L | B to Y -- L | L | B to A L | L | B to Y
-- H | L |A to B, B to Y | -- H | L |A to B, B to Y |
VME_DATA_DIR_o <= s_dataDir;
VME_DATA_OE_N_o <= '0'; -- Driven IFF DIR = 1 VME_DATA_OE_N_o <= '0'; -- Driven IFF DIR = 1
VME_ADDR_DIR_o <= s_addrDir;
VME_ADDR_OE_N_o <= '0'; -- Driven IFF DIR = 1 VME_ADDR_OE_N_o <= '0'; -- Driven IFF DIR = 1
VME_DTACK_OE_o <= s_dtackOE;
VME_DTACK_n_o <= s_mainDTACK;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Access Mode Decoders -- Access Mode Decoders
...@@ -340,16 +330,16 @@ begin ...@@ -340,16 +330,16 @@ begin
-- on rising edge of AS. -- on rising edge of AS.
s_memReq <= '0'; s_memReq <= '0';
decode_start_o <= '0'; decode_start_o <= '0';
s_dtackOE <= '0'; VME_DTACK_OE_o <= '0';
s_mainDTACK <= '1'; VME_DTACK_n_o <= '1';
s_dataDir <= '0'; VME_DATA_DIR_o <= '0';
s_addrDir <= '0'; VME_ADDR_DIR_o <= '0';
s_dataPhase <= '0'; s_dataPhase <= '0';
s_transferActive <= '0'; s_transferActive <= '0';
s_retry <= '0'; s_retry <= '0';
s_BERR_out <= '0'; s_BERR_out <= '0';
s_mainFSMstate <= IDLE; s_mainFSMstate <= IDLE;
s_sel <= "0000"; s_sel <= "0000";
s_ADDRlatched <= (others => '0'); s_ADDRlatched <= (others => '0');
s_LWORDlatched_n <= '0'; s_LWORDlatched_n <= '0';
...@@ -364,10 +354,10 @@ begin ...@@ -364,10 +354,10 @@ begin
else else
s_memReq <= '0'; s_memReq <= '0';
decode_start_o <= '0'; decode_start_o <= '0';
s_dtackOE <= '0'; VME_DTACK_OE_o <= '0';
s_mainDTACK <= '1'; VME_DTACK_n_o <= '1';
s_dataDir <= '0'; VME_DATA_DIR_o <= '0';
s_addrDir <= '0'; VME_ADDR_DIR_o <= '0';
s_dataPhase <= '0'; s_dataPhase <= '0';
s_transferActive <= '0'; s_transferActive <= '0';
s_retry <= '0'; s_retry <= '0';
...@@ -420,8 +410,7 @@ begin ...@@ -420,8 +410,7 @@ begin
end if; end if;
when DECODE_ACCESS => when DECODE_ACCESS =>
-- check if this slave board is addressed and if it is, check -- check if this slave board is addressed.
-- the access mode
if decode_done_i = '1' then if decode_done_i = '1' then
if decode_sel_i = '1' and module_enable_i = '1' then if decode_sel_i = '1' and module_enable_i = '1' then
...@@ -442,8 +431,8 @@ begin ...@@ -442,8 +431,8 @@ begin
when WAIT_FOR_DS => when WAIT_FOR_DS =>
-- wait until DS /= "11" -- wait until DS /= "11"
s_dtackOE <= '1'; VME_DTACK_OE_o <= '1';
s_addrDir <= (s_is_d64) and VME_WRITE_n_i; VME_ADDR_DIR_o <= (s_is_d64) and VME_WRITE_n_i;
s_dataPhase <= s_dataPhase; s_dataPhase <= s_dataPhase;
s_transferActive <= '1'; s_transferActive <= '1';
...@@ -457,9 +446,9 @@ begin ...@@ -457,9 +446,9 @@ begin
when LATCH_DS => when LATCH_DS =>
-- this state is necessary indeed the VME master can assert the -- this state is necessary indeed the VME master can assert the
-- DS lines not at the same time -- DS lines not at the same time
s_dtackOE <= '1'; VME_DTACK_OE_o <= '1';
s_dataDir <= VME_WRITE_n_i; VME_DATA_DIR_o <= VME_WRITE_n_i;
s_addrDir <= (s_is_d64) and VME_WRITE_n_i; VME_ADDR_DIR_o <= (s_is_d64) and VME_WRITE_n_i;
s_dataPhase <= s_dataPhase; s_dataPhase <= s_dataPhase;
s_transferActive <= '1'; s_transferActive <= '1';
if s_DS_latch_count = 0 then if s_DS_latch_count = 0 then
...@@ -484,9 +473,9 @@ begin ...@@ -484,9 +473,9 @@ begin
end if; end if;
when CHECK_TRANSFER_TYPE => when CHECK_TRANSFER_TYPE =>
s_dtackOE <= '1'; VME_DTACK_OE_o <= '1';
s_dataDir <= VME_WRITE_n_i; VME_DATA_DIR_o <= VME_WRITE_n_i;
s_addrDir <= (s_is_d64) and VME_WRITE_n_i; VME_ADDR_DIR_o <= (s_is_d64) and VME_WRITE_n_i;
s_dataPhase <= s_dataPhase; s_dataPhase <= s_dataPhase;
s_transferActive <= '1'; s_transferActive <= '1';
...@@ -518,9 +507,9 @@ begin ...@@ -518,9 +507,9 @@ begin
when MEMORY_REQ => when MEMORY_REQ =>
-- To request the memory CR/CSR or WB memory it is sufficient to -- To request the memory CR/CSR or WB memory it is sufficient to
-- generate a pulse on s_memReq signal -- generate a pulse on s_memReq signal
s_dtackOE <= '1'; VME_DTACK_OE_o <= '1';
s_dataDir <= VME_WRITE_n_i; VME_DATA_DIR_o <= VME_WRITE_n_i;
s_addrDir <= (s_is_d64) and VME_WRITE_n_i; VME_ADDR_DIR_o <= (s_is_d64) and VME_WRITE_n_i;
s_dataPhase <= s_dataPhase; s_dataPhase <= s_dataPhase;
s_transferActive <= '1'; s_transferActive <= '1';
...@@ -552,9 +541,9 @@ begin ...@@ -552,9 +541,9 @@ begin
end if; end if;
when DATA_TO_BUS => when DATA_TO_BUS =>
s_dtackOE <= '1'; VME_DTACK_OE_o <= '1';
s_dataDir <= VME_WRITE_n_i; VME_DATA_DIR_o <= VME_WRITE_n_i;
s_addrDir <= (s_is_d64) and VME_WRITE_n_i; VME_ADDR_DIR_o <= (s_is_d64) and VME_WRITE_n_i;
s_dataPhase <= s_dataPhase; s_dataPhase <= s_dataPhase;
s_transferActive <= '1'; s_transferActive <= '1';
s_mainFSMstate <= DTACK_LOW; s_mainFSMstate <= DTACK_LOW;
...@@ -571,15 +560,15 @@ begin ...@@ -571,15 +560,15 @@ begin
end if; end if;
when DTACK_LOW => when DTACK_LOW =>
s_dtackOE <= '1'; VME_DTACK_OE_o <= '1';
s_dataDir <= VME_WRITE_n_i; VME_DATA_DIR_o <= VME_WRITE_n_i;
s_addrDir <= (s_is_d64) and VME_WRITE_n_i; VME_ADDR_DIR_o <= (s_is_d64) and VME_WRITE_n_i;
s_dataPhase <= s_dataPhase; s_dataPhase <= s_dataPhase;
s_transferActive <= '1'; s_transferActive <= '1';
-- Set DTACK (or retry or berr) -- Set DTACK (or retry or berr)
if s_BERRcondition = '0' and s_rty1 = '0' then if s_BERRcondition = '0' and s_rty1 = '0' then
s_mainDTACK <= '0'; VME_DTACK_n_o <= '0';
elsif s_BERRcondition = '0' and s_rty1 = '1' then elsif s_BERRcondition = '0' and s_rty1 = '1' then
s_retry <= '1'; s_retry <= '1';
else else
...@@ -587,7 +576,7 @@ begin ...@@ -587,7 +576,7 @@ begin
end if; end if;
if VME_DS_n_i = "11" then if VME_DS_n_i = "11" then
s_dataDir <= '0'; VME_DATA_DIR_o <= '0';
case s_transferType is case s_transferType is
when SINGLE => when SINGLE =>
-- Cycle should be finished, but allow another access at -- Cycle should be finished, but allow another access at
...@@ -611,8 +600,8 @@ begin ...@@ -611,8 +600,8 @@ begin
end if; end if;
when INCREMENT_ADDR => when INCREMENT_ADDR =>
s_dtackOE <= '1'; VME_DTACK_OE_o <= '1';
s_addrDir <= (s_is_d64) and VME_WRITE_n_i; VME_ADDR_DIR_o <= (s_is_d64) and VME_WRITE_n_i;
s_dataPhase <= s_dataPhase; s_dataPhase <= s_dataPhase;
s_transferActive <= '1'; s_transferActive <= '1';
...@@ -814,7 +803,7 @@ begin ...@@ -814,7 +803,7 @@ begin
rty_i => rty_i, rty_i => rty_i,
err_i => err_i, err_i => err_i,
cyc_o => cyc_o, cyc_o => cyc_o,
memReq_o => stb_o, stb_o => stb_o,
WBdata_o => dat_o, WBdata_o => dat_o,
wbData_i => dat_i, wbData_i => dat_i,
locAddr_o => adr_o, locAddr_o => adr_o,
......
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @ 7e121be4
...@@ -376,7 +376,7 @@ package vme64x_pack is ...@@ -376,7 +376,7 @@ package vme64x_pack is
err_o : out std_logic; err_o : out std_logic;
rty_o : out std_logic; rty_o : out std_logic;
cyc_o : out std_logic; cyc_o : out std_logic;
memReq_o : out std_logic; stb_o : out std_logic;
WBdata_o : out std_logic_vector(g_WB_DATA_WIDTH-1 downto 0); WBdata_o : out std_logic_vector(g_WB_DATA_WIDTH-1 downto 0);
locAddr_o : out std_logic_vector(g_WB_ADDR_WIDTH-1 downto 0); locAddr_o : out std_logic_vector(g_WB_ADDR_WIDTH-1 downto 0);
WbSel_o : out std_logic_vector(g_WB_DATA_WIDTH/8-1 downto 0); WbSel_o : out std_logic_vector(g_WB_DATA_WIDTH/8-1 downto 0);
......
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