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VME64x core
Commit 7a8f2b5c authored by Tom Levens's avatar Tom Levens
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Inline VME_SharedComps.vhd 

The components in VME_SharedComps.vhd are only used in single places.
Therefore to simplify the project, they have been inlined.
Signed-off-by: Tom Levens's avatarTom Levens <tom.levens@cern.ch>
parent 29269caa
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Showing with 57 additions and 515 deletions
hdl/vme64x-core/rtl/Manifest.py
View file @ 7a8f2b5c
......@@ -12,6 +12,5 @@ files = [ "xvme64x_core.vhd",
"VME_Funct_Match.vhd",
"VME_Init.vhd",
"VME_IRQ_Controller.vhd",
"VME_SharedComps.vhd",
"VME_swapper.vhd",
"VME_Wb_master.vhd"]
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @ 7a8f2b5c
......@@ -272,18 +272,12 @@ architecture RTL of VME64xCore_Top is
signal s_BAR : std_logic_vector(4 downto 0);
-- Oversampled input signals
signal VME_RST_n_oversampled : std_logic;
signal VME_AS_n_oversampled : std_logic;
--signal VME_AS_n_oversampled1 : std_logic; -- for the IRQ_Controller
--signal VME_LWORD_n_oversampled : std_logic;
signal VME_WRITE_n_oversampled : std_logic;
signal VME_DS_n_oversampled : std_logic_vector(1 downto 0);
signal VME_DS_n_oversampled_1 : std_logic_vector(1 downto 0);
signal VME_GA_oversampled : std_logic_vector(5 downto 0);
signal VME_IACK_n_oversampled : std_logic;
signal VME_IACKIN_n_oversampled : std_logic;
signal s_reg_1 : std_logic_vector(1 downto 0) := (others => '0');
signal s_reg_2 : std_logic_vector(1 downto 0) := (others => '0');
signal s_VME_RST_n : std_logic_vector(2 downto 0);
signal s_VME_AS_n : std_logic_vector(2 downto 0);
signal s_VME_WRITE_n : std_logic_vector(2 downto 0);
signal s_VME_DS_n : std_logic_vector(5 downto 0);
signal s_VME_IACK_n : std_logic_vector(2 downto 0);
signal s_VME_IACKIN_n : std_logic_vector(2 downto 0);
begin
......@@ -294,63 +288,18 @@ begin
-- necessary to avoid metastability problems. With 3 samples the probability
-- of metastability problem will be very low but of course the transfer rate
-- will be slow down a little.
GAinputSample : RegInputSample
generic map (
width => 6
)
port map (
reg_i => VME_GA_i,
reg_o => VME_GA_oversampled,
clk_i => clk_i
);
RegInputSample : process(clk_i)
process (clk_i)
begin
if rising_edge(clk_i) then
s_reg_1 <= VME_DS_n_i;
s_reg_2 <= s_reg_1;
VME_DS_n_oversampled <= s_reg_2;
s_VME_RST_n <= s_VME_RST_n(1 downto 0) & VME_RST_n_i;
s_VME_AS_n <= s_VME_AS_n(1 downto 0) & VME_AS_n_i;
s_VME_WRITE_n <= s_VME_WRITE_n(1 downto 0) & VME_WRITE_n_i;
s_VME_DS_n <= s_VME_DS_n(3 downto 0) & VME_DS_n_i;
s_VME_IACK_n <= s_VME_IACK_n(1 downto 0) & VME_IACK_n_i;
s_VME_IACKIN_n <= s_VME_IACKIN_n(1 downto 0) & VME_IACKIN_n_i;
end if;
end process;
VME_DS_n_oversampled_1 <= s_reg_2; -- to avoid timing problem during BLT and
-- MBLT accesses
WRITEinputSample : SigInputSample
port map (
sig_i => VME_WRITE_n_i,
sig_o => VME_WRITE_n_oversampled,
clk_i => clk_i
);
ASinputSample : SigInputSample
port map (
sig_i => VME_AS_n_i,
sig_o => VME_AS_n_oversampled,
clk_i => clk_i
);
RSTinputSample : SigInputSample
port map (
sig_i => VME_RST_n_i,
sig_o => VME_RST_n_oversampled,
clk_i => clk_i
);
IACKinputSample : SigInputSample
port map (
sig_i => VME_IACK_n_i,
sig_o => VME_IACK_n_oversampled,
clk_i => clk_i
);
IACKINinputSample : SigInputSample
port map (
sig_i => VME_IACKIN_n_i,
sig_o => VME_IACKIN_n_oversampled,
clk_i => clk_i
);
------------------------------------------------------------------------------
-- VME Bus
------------------------------------------------------------------------------
......@@ -367,15 +316,15 @@ begin
reset_o => s_reset, -- asserted when '1'
-- VME
VME_RST_n_i => VME_RST_n_oversampled,
VME_AS_n_i => VME_AS_n_oversampled,
VME_RST_n_i => s_VME_RST_n(2),
VME_AS_n_i => s_VME_AS_n(2),
VME_LWORD_n_o => VME_LWORD_n_o,
VME_LWORD_n_i => VME_LWORD_n_i,
VME_RETRY_n_o => VME_RETRY_n_o,
VME_RETRY_OE_o => VME_RETRY_OE_o,
VME_WRITE_n_i => VME_WRITE_n_oversampled,
VME_DS_n_i => VME_DS_n_oversampled,
VME_DS_ant_n_i => VME_DS_n_oversampled_1,
VME_WRITE_n_i => s_VME_WRITE_n(2),
VME_DS_n_i => s_VME_DS_n(5 downto 4),
VME_DS_ant_n_i => s_VME_DS_n(3 downto 2),
VME_DTACK_n_o => s_VME_DTACK_VMEbus,
VME_DTACK_OE_o => s_VME_DTACK_OE_VMEbus,
VME_BERR_o => VME_BERR_o,
......@@ -388,7 +337,7 @@ begin
VME_DATA_DIR_o => s_VME_DATA_DIR_VMEbus,
VME_DATA_OE_N_o => VME_DATA_OE_N_o,
VME_AM_i => VME_AM_i,
VME_IACK_n_i => VME_IACK_n_oversampled,
VME_IACK_n_i => s_VME_IACK_n(2),
-- WB
memReq_o => STB_o,
......@@ -440,19 +389,19 @@ begin
-- Multiplexer added on the output signal used by either VMEbus.vhd and the
-- IRQ_controller.vhd
VME_DATA_o <= s_VME_DATA_VMEbus
when VME_IACK_n_oversampled = '1'
when s_VME_IACK_n(2) = '1'
else s_VME_DATA_IRQ;
VME_DTACK_n_o <= s_VME_DTACK_VMEbus and s_VME_DTACK_IRQ;
--when VME_IACK_n_oversampled = '1'
--when s_VME_IACK_n(2) = '1'
--else s_VME_DTACK_IRQ;
VME_DTACK_OE_o <= s_VME_DTACK_OE_VMEbus or s_VME_DTACK_OE_IRQ;
--when VME_IACK_n_oversampled = '1'
--when s_VME_IACK_n(2) = '1'
--else s_VME_DTACK_OE_IRQ;
VME_DATA_DIR_o <= s_VME_DATA_DIR_VMEbus
when VME_IACK_n_oversampled = '1'
when s_VME_IACK_n(2) = '1'
else s_VME_DATA_DIR_IRQ;
------------------------------------------------------------------------------
......@@ -465,9 +414,9 @@ begin
port map (
clk_i => clk_i,
reset_n_i => s_reset_IRQ, -- asserted when low
VME_IACKIN_n_i => VME_IACKIN_n_oversampled,
VME_AS_n_i => VME_AS_n_oversampled,
VME_DS_n_i => VME_DS_n_oversampled,
VME_IACKIN_n_i => s_VME_IACKIN_n(2),
VME_AS_n_i => s_VME_AS_n(2),
VME_DS_n_i => s_VME_DS_n(5 downto 4),
VME_ADDR_123_i => VME_ADDR_i(3 downto 1),
INT_Level_i => s_INT_Level,
INT_Vector_i => s_INT_Vector,
......@@ -506,7 +455,7 @@ begin
CRAM_Wen => s_CRAMwea,
en_wr_CSR => s_en_wr_CSR,
CrCsrOffsetAddr => s_CrCsrOffsetAddr,
VME_GA_oversampled => VME_GA_oversampled,
VME_GA_oversampled => VME_GA_i,
locDataIn => s_CSRData_o,
err_flag => s_err_flag,
reset_flag => s_reset_flag,
......
hdl/vme64x-core/rtl/VME_SharedComps.vhd deleted 100644 → 0
View file @ 29269caa
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- VME64x Core
-- http://www.ohwr.org/projects/vme64x-core
--------------------------------------------------------------------------------
--
-- unit name: VME_SharedComps (VME_SharedComps.vhd)
--
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch>
--
-- description: This component implements the rising and falling edge
-- detection and the triple and double sample entities.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- triple sample sig_i signals to avoid metastable states
entity SigInputSample is
port (
sig_i,
clk_i : in std_logic;
sig_o : out std_logic
);
end SigInputSample;
architecture RTL of SigInputSample is
signal s_1: std_logic;
signal s_2: std_logic;
begin
process (clk_i) begin
if rising_edge(clk_i) then
s_1 <= sig_i;
s_2 <= s_1;
sig_o <= s_2;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- double sample sig_i signals to avoid metastable states
entity DoubleSigInputSample is
port (
sig_i,
clk_i : in std_logic;
sig_o : out std_logic
);
end DoubleSigInputSample;
architecture RTL of DoubleSigInputSample is
signal s_1 : std_logic;
begin
process (clk_i) begin
if rising_edge(clk_i) then
s_1 <= sig_i;
sig_o <= s_1;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity SingleRegInputSample is
generic (
width : natural := 8
);
port (
reg_i : in std_logic_vector(width-1 downto 0);
reg_o : out std_logic_vector(width-1 downto 0);
clk_i : in std_logic
);
end SingleRegInputSample;
architecture RTL of SingleRegInputSample is
begin
process (clk_i) begin
if rising_edge(clk_i) then
reg_o <= reg_i;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity FlipFlopD is
port (
reset,
sig_i,
clk_i,
enable : in std_logic;
sig_o : out std_logic
);
end FlipFlopD;
architecture RTL of FlipFlopD is
begin
process (clk_i) begin
if rising_edge(clk_i) then
if reset = '1' then
sig_o <= '0';
elsif enable = '1' then
sig_o <= sig_i;
end if;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Reg32bit is
port (
reset,
clk_i,
enable : in std_logic;
di : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0)
);
end Reg32bit;
architecture RTL of Reg32bit is
begin
process (clk_i) begin
if rising_edge(clk_i) then
if reset = '0' then
do <= (others => '0');
elsif enable = '1' then
do <= di;
end if;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- detect rising edge
entity RisEdgeDetection is
port (
sig_i,
clk_i : in std_logic;
RisEdge_o : out std_logic
);
end RisEdgeDetection;
architecture RTL of RisEdgeDetection is
signal s_1: std_logic;
begin
process (clk_i) begin
if rising_edge(clk_i) then
s_1 <= sig_i;
if s_1 = '0' and sig_i = '1' then
RisEdge_o <= '1';
else
RisEdge_o <= '0';
end if;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- detect falling edge
entity FallingEdgeDetection is
port (
sig_i,
clk_i : in std_logic;
FallEdge_o : out std_logic
);
end FallingEdgeDetection;
architecture RTL of FallingEdgeDetection is
signal s_1: std_logic;
begin
process (clk_i) begin
if rising_edge(clk_i) then
s_1 <= sig_i;
if s_1 = '1' and sig_i = '0' then
FallEdge_o <= '1';
else
FallEdge_o <= '0';
end if;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- give pulse (sigEdge_o) at rising and falling edge
entity EdgeDetection is
port (
sig_i,
clk_i : in std_logic;
sigEdge_o : out std_logic
);
end EdgeDetection;
architecture RTL of EdgeDetection is
signal s_1: std_logic;
begin
process (clk_i) begin
if rising_edge(clk_i) then
s_1 <= sig_i;
if (s_1 = '0' and sig_i = '1') or (s_1 = '1' and sig_i = '0') then
sigEdge_o <= '1';
else
sigEdge_o <= '0';
end if;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- triple sample input register reg_i to avoid metastable states
-- and catching of transition values
entity RegInputSample is
generic (
width : natural := 8
);
port (
reg_i : in std_logic_vector(width-1 downto 0);
reg_o : out std_logic_vector(width-1 downto 0);
clk_i : in std_logic
);
end RegInputSample;
architecture RTL of RegInputSample is
signal reg_1,
reg_2 : std_logic_vector(width-1 downto 0);
begin
process (clk_i) begin
if rising_edge(clk_i) then
reg_1 <= reg_i;
reg_2 <= reg_1;
reg_o <= reg_2;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- triple sample input register reg_i to avoid metastable states
-- and catching of transition values
entity DoubleRegInputSample is
generic (
width : natural := 8
);
port (
reg_i : in std_logic_vector(width-1 downto 0);
reg_o : out std_logic_vector(width-1 downto 0);
clk_i : in std_logic
);
end DoubleRegInputSample;
architecture RTL of DoubleRegInputSample is
signal reg_1,
reg_2 : std_logic_vector(width-1 downto 0);
begin
process (clk_i)
begin
if rising_edge(clk_i) then
reg_1 <= reg_i;
reg_o <= reg_1;
end if;
end process;
end RTL;
hdl/vme64x-core/rtl/VME_bus.vhd
View file @ 7a8f2b5c
......@@ -242,6 +242,7 @@ architecture RTL of VME_bus is
signal s_CSRaddressed : std_logic; -- CSR space is addressed
signal s_CSRdata : unsigned(7 downto 0); -- CSR data write/read
signal s_CRdataIn : std_logic_vector(7 downto 0); -- CR data bus
signal s_CRdataIn1 : std_logic_vector(7 downto 0); --
signal s_CRAMdataIn : std_logic_vector(7 downto 0); -- CRAM data bus
signal s_FUNC_ADEM : t_FUNC_32b_array_std;
signal s_FUNC_AMCAP : t_FUNC_64b_array_std;
......@@ -266,6 +267,7 @@ architecture RTL of VME_bus is
signal s_initReadCounter1 : std_logic_vector(8 downto 0);
signal s_CRaddr : unsigned(18 downto 0);
signal s_prev_VME_AS_n : std_logic;
signal s_is_d64 : std_logic;
signal s_base_addr : unsigned(63 downto 0);
signal s_nx_base_addr : std_logic_vector(63 downto 0);
......@@ -1376,38 +1378,36 @@ begin
------------------------------------------------------------------------------
-- Edge Detection and Sampling
------------------------------------------------------------------------------
ASfallingEdge : FallingEdgeDetection
port map (
sig_i => VME_AS_n_i,
clk_i => clk_i,
FallEdge_o => s_VMEaddrLatch
);
process (clk_i)
begin
if rising_edge(clk_i) then
s_prev_VME_AS_n <= VME_AS_n_i;
s_VMEaddrLatch <= '0';
s_mainFSMreset <= '0';
ASrisingEdge : RisEdgeDetection
port map (
sig_i => VME_AS_n_i,
clk_i => clk_i,
RisEdge_o => s_mainFSMreset
);
if VME_AS_n_i = '0' and s_prev_VME_AS_n = '1' then
s_VMEaddrLatch <= '1';
end if;
CRinputSample : DoubleRegInputSample
generic map (
width => 8
)
port map (
reg_i => CRdata_i,
reg_o => s_CRdataIn,
clk_i => clk_i
);
if VME_AS_n_i = '1' and s_prev_VME_AS_n = '0' then
s_mainFSMreset <= '1';
end if;
end if;
end process;
CRAMinputSample : SingleRegInputSample
generic map (
width => 8
)
port map (
reg_i => CRAMdata_i,
reg_o => s_CRAMdataIn,
clk_i => clk_i
);
process (clk_i)
begin
if rising_edge(clk_i) then
s_CRdataIn1 <= CRdata_i;
s_CRdataIn <= s_CRdataIn1;
end if;
end process;
process (clk_i)
begin
if rising_edge(clk_i) then
s_CRAMdataIn <= CRAMdata_i;
end if;
end process;
end RTL;
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @ 7a8f2b5c
......@@ -846,99 +846,6 @@ package vme64x_pack is
);
end component VME_swapper;
component Reg32bit is
port (
reset,
clk_i,
enable : in std_logic;
di : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0)
);
end component Reg32bit;
component FlipFlopD is
port (
reset,
enable,
sig_i,
clk_i : in std_logic;
sig_o : out std_logic := '0'
);
end component FlipFlopD;
component EdgeDetection is
port (
sig_i,
clk_i : in std_logic;
sigEdge_o : out std_logic := '0'
);
end component EdgeDetection;
component FallingEdgeDetection is
port (
sig_i,
clk_i : in std_logic;
FallEdge_o : out std_logic
);
end component FallingEdgeDetection;
component RisEdgeDetection is
port (
sig_i,
clk_i : in std_logic;
RisEdge_o : out std_logic
);
end component RisEdgeDetection;
component DoubleSigInputSample is
port (
sig_i,
clk_i : in std_logic;
sig_o : out std_logic
);
end component DoubleSigInputSample;
component SigInputSample is
port (
sig_i,
clk_i : in std_logic;
sig_o : out std_logic
);
end component SigInputSample;
component DoubleRegInputSample is
generic (
width : natural := 8
);
port (
reg_i : in std_logic_vector(width-1 downto 0);
reg_o : out std_logic_vector(width-1 downto 0) := (others => '0');
clk_i : in std_logic
);
end component DoubleRegInputSample;
component RegInputSample is
generic (
width : natural := 8
);
port (
reg_i : in std_logic_vector(width-1 downto 0);
reg_o : out std_logic_vector(width-1 downto 0) := (others => '0');
clk_i : in std_logic
);
end component RegInputSample;
component SingleRegInputSample is
generic (
width : natural := 8
);
port (
reg_i : in std_logic_vector(width-1 downto 0);
reg_o : out std_logic_vector(width-1 downto 0) := (others => '0');
clk_i : in std_logic
);
end component SingleRegInputSample;
component VME_IRQ_Controller
generic (
g_retry_timeout : integer range 1024 to 16777215
......
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