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VME64x core
Commit 73230942 authored by Tristan Gingold's avatar Tristan Gingold
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vme_bus: cleanup

parent 29b8b02b
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Showing with 17 additions and 20 deletions
hdl/rtl/vme_bus.vhd
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...@@ -136,6 +136,7 @@ architecture rtl of vme_bus is ...@@ -136,6 +136,7 @@ architecture rtl of vme_bus is
signal vme_idff_lword_n : std_logic; signal vme_idff_lword_n : std_logic;
signal vme_idff_am : std_logic_vector(5 downto 0); signal vme_idff_am : std_logic_vector(5 downto 0);
-- As these signals are synchronized, they correspond to latched values.
signal vme_idff_ds_n : std_logic_vector(1 downto 0); signal vme_idff_ds_n : std_logic_vector(1 downto 0);
signal vme_idff_write_n : std_logic; signal vme_idff_write_n : std_logic;
...@@ -321,17 +322,15 @@ begin ...@@ -321,17 +322,15 @@ begin
decode_start_o <= '0'; decode_start_o <= '0';
-- VME -- VME
vme_dtack_oe_o <= '0'; vme_dtack_oe_o <= '0';
vme_dtack_n_o <= '1'; vme_dtack_n_o <= '1';
vme_data_dir_o <= '0'; vme_data_dir_o <= '0';
vme_odff_addr_dir <= '0'; vme_odff_addr_dir <= '0';
vme_berr_n_o <= '1'; vme_odff_lword_n <= '0';
vme_addr_o <= (others => '0'); vme_berr_n_o <= '1';
vme_lword_n_o <= '1'; vme_iackout_n_o <= '1';
vme_data_o <= (others => '0'); s_MBLT_Data <= '0';
vme_iackout_n_o <= '1'; s_mainFSMstate <= IDLE;
s_MBLT_Data <= '0';
s_mainFSMstate <= IDLE;
-- WB -- WB
s_wb_start <= '0'; s_wb_start <= '0';
...@@ -526,7 +525,7 @@ begin ...@@ -526,7 +525,7 @@ begin
-- A Slave MUST NOT respond with a falling edge on DTACK* during -- A Slave MUST NOT respond with a falling edge on DTACK* during
-- an unaligned transfer cycle, if it does not have UAT -- an unaligned transfer cycle, if it does not have UAT
-- capability. -- capability.
if vme_odff_lword_n = '0' and vme_idff_ds_n /= "00" then if vme_idff_lword_n = '0' and vme_idff_ds_n /= "00" then
-- unaligned. -- unaligned.
s_mainFSMstate <= WAIT_END; s_mainFSMstate <= WAIT_END;
else else
...@@ -542,10 +541,10 @@ begin ...@@ -542,10 +541,10 @@ begin
if g_VME32 then if g_VME32 then
-- only for MBLT -- only for MBLT
vme_addr_o <= data_reg(63 downto 33); vme_odff_addr <= data_reg(63 downto 33);
vme_lword_n_o <= data_reg(32); vme_odff_lword_n <= data_reg(32);
end if; end if;
vme_data_o <= data_reg(31 downto 0); vme_odff_data <= data_reg(31 downto 0);
if s_transferType = MBLT and vme_idff_write_n = '1' then if s_transferType = MBLT and vme_idff_write_n = '1' then
-- Prefetch. -- Prefetch.
...@@ -696,11 +695,6 @@ begin ...@@ -696,11 +695,6 @@ begin
s_wb_done <= '0'; s_wb_done <= '0';
--if vme_odff_lword_n = '1' and vme_odff_addr(1) = '0' and g_VME32 then
-- -- Word/byte access with A1=0
-- s_locDataIn(31 downto 16) <= vme_odff_data(15 downto 0);
--end if;
if vme_idff_write_n = '0' then if vme_idff_write_n = '0' then
-- Get the data to write (in case of write!). -- Get the data to write (in case of write!).
if g_VME32 and s_transferType = MBLT then if g_VME32 and s_transferType = MBLT then
...@@ -893,5 +887,8 @@ begin ...@@ -893,5 +887,8 @@ begin
else '0'; else '0';
vme_addr_dir_o <= vme_odff_addr_dir; vme_addr_dir_o <= vme_odff_addr_dir;
vme_addr_o <= vme_odff_addr;
vme_data_o <= vme_odff_data;
vme_lword_n_o <= vme_odff_lword_n;
end rtl; end rtl;
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