Commit 72eff0ad authored by Tom Levens's avatar Tom Levens

WIP

parent a3b2fde3
......@@ -2,12 +2,9 @@ files = [ "xvme64x_core.vhd",
"xvme64x_core_pkg.vhd",
"VME64xCore_Top.vhd",
"vme64x_pack.vhd",
"VME_Access_Decode.vhd",
"VME_Am_Match.vhd",
"VME_bus.vhd",
"VME_CR_CSR_Space.vhd",
"VME_User_CSR.vhd",
"VME_CRAM.vhd",
"VME_Funct_Match.vhd",
"VME_IRQ_Controller.vhd",
"VME_swapper.vhd",
......
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--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- VME64x Core
-- http://www.ohwr.org/projects/vme64x-core
--------------------------------------------------------------------------------
--
-- unit name: VME_Am_Match (VME_Am_Match.vhd)
--
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch>
--
-- description:
--
-- This component checks if the AM match. If it is the correspondent AmMatch's
-- bit is asserted. This condition is necessary but not sufficient to select
-- the function and access the board.
--
-- If DFS = '0' the function supports only access modes with the same address
-- width;
-- 1 function --> only 1 address width;
-- with address width I mean A16, A24, A32 or A64.
-- is sufficient check the AMCAP;
-- AmMatch(i) <= s_FUNC_AMCAP(i)(to_integer(unsigned(Am))).
--
-- If DFS = '1' the function supports access modes with different address
-- widths so AmMatch(i) is asserted only if ADER[7:2] = AM and
-- s_FUNC_AMCAP(i)(to_integer(unsigned(Am)))='1'.
--
-- If ADER(i)'s XAM bit is asserted than AmMatch(i) is asserted only if
-- AM = 0x20 and if the -- XAMCAP(i)(to_integer(unsigned(XAm))) = '1' and if
-- DFS = '1' also ADER[9:2] must be equal -- to XAM[7:0] lines.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vme64x_pack.all;
entity VME_Am_Match is
port (
clk_i : in std_logic;
reset : in std_logic;
mainFSMreset : in std_logic;
Ader0 : in std_logic_vector(31 downto 0);
Ader1 : in std_logic_vector(31 downto 0);
Ader2 : in std_logic_vector(31 downto 0);
Ader3 : in std_logic_vector(31 downto 0);
Ader4 : in std_logic_vector(31 downto 0);
Ader5 : in std_logic_vector(31 downto 0);
Ader6 : in std_logic_vector(31 downto 0);
Ader7 : in std_logic_vector(31 downto 0);
AmCap0 : in std_logic_vector(63 downto 0);
AmCap1 : in std_logic_vector(63 downto 0);
AmCap2 : in std_logic_vector(63 downto 0);
AmCap3 : in std_logic_vector(63 downto 0);
AmCap4 : in std_logic_vector(63 downto 0);
AmCap5 : in std_logic_vector(63 downto 0);
AmCap6 : in std_logic_vector(63 downto 0);
AmCap7 : in std_logic_vector(63 downto 0);
XAmCap0 : in std_logic_vector(255 downto 0);
XAmCap1 : in std_logic_vector(255 downto 0);
XAmCap2 : in std_logic_vector(255 downto 0);
XAmCap3 : in std_logic_vector(255 downto 0);
XAmCap4 : in std_logic_vector(255 downto 0);
XAmCap5 : in std_logic_vector(255 downto 0);
XAmCap6 : in std_logic_vector(255 downto 0);
XAmCap7 : in std_logic_vector(255 downto 0);
Am : in std_logic_vector(5 downto 0);
XAm : in std_logic_vector(7 downto 0);
DFS_i : in std_logic_vector(7 downto 0);
decode : in std_logic;
AmMatch : out std_logic_vector(7 downto 0)
);
end VME_Am_Match;
architecture Behavioral of VME_Am_Match is
signal s_FUNC_ADER : t_FUNC_32b_array;
signal s_FUNC_AMCAP : t_FUNC_64b_array;
signal s_FUNC_XAMCAP : t_FUNC_256b_array;
signal s_amcap_match : std_logic_vector(7 downto 0);
signal s_xamcap_match : std_logic_vector(7 downto 0);
begin
s_FUNC_ADER(0) <= unsigned(Ader0);
s_FUNC_ADER(1) <= unsigned(Ader1);
s_FUNC_ADER(2) <= unsigned(Ader2);
s_FUNC_ADER(3) <= unsigned(Ader3);
s_FUNC_ADER(4) <= unsigned(Ader4);
s_FUNC_ADER(5) <= unsigned(Ader5);
s_FUNC_ADER(6) <= unsigned(Ader6);
s_FUNC_ADER(7) <= unsigned(Ader7);
s_FUNC_AMCAP(0) <= unsigned(AmCap0);
s_FUNC_AMCAP(1) <= unsigned(AmCap1);
s_FUNC_AMCAP(2) <= unsigned(AmCap2);
s_FUNC_AMCAP(3) <= unsigned(AmCap3);
s_FUNC_AMCAP(4) <= unsigned(AmCap4);
s_FUNC_AMCAP(5) <= unsigned(AmCap5);
s_FUNC_AMCAP(6) <= unsigned(AmCap6);
s_FUNC_AMCAP(7) <= unsigned(AmCap7);
s_FUNC_XAMCAP(0) <= unsigned(XAmCap0);
s_FUNC_XAMCAP(1) <= unsigned(XAmCap1);
s_FUNC_XAMCAP(2) <= unsigned(XAmCap2);
s_FUNC_XAMCAP(3) <= unsigned(XAmCap3);
s_FUNC_XAMCAP(4) <= unsigned(XAmCap4);
s_FUNC_XAMCAP(5) <= unsigned(XAmCap5);
s_FUNC_XAMCAP(6) <= unsigned(XAmCap6);
s_FUNC_XAMCAP(7) <= unsigned(XAmCap7);
p_AMmatch: process(clk_i) begin
if rising_edge(clk_i) then
if mainFSMreset = '1' or reset = '1' then
AmMatch <= (others => '0');
elsif decode = '1' then
for i in AmMatch'range loop
if DFS_i(i) = '1' then
if s_FUNC_ADER(i)(c_ADER_XAM_MODE) = '0' then
if unsigned(s_FUNC_ADER(i)(7 downto 2)) = unsigned(Am) then
AmMatch(i) <= s_amcap_match(i);
else
AmMatch(i) <= '0';
end if;
else
if (unsigned(XAm) = unsigned(s_FUNC_ADER(i)(9 downto 2))) then
AmMatch(i) <= s_xamcap_match(i) and s_amcap_match(i);
else
AmMatch(i) <= '0';
end if;
end if;
else
if s_FUNC_ADER(i)(c_ADER_XAM_MODE) = '1' then
AmMatch(i) <= s_xamcap_match(i) and s_amcap_match(i);
else
AmMatch(i) <= s_amcap_match(i);
end if;
end if;
end loop;
end if;
end if;
end process;
-- Check if the AM is in the AMCAP register
process (s_FUNC_AMCAP, Am) begin
s_amcap_match <= (others => '0');
for i in 0 to 7 loop
s_amcap_match(i) <= s_FUNC_AMCAP(i)(to_integer(unsigned(Am)));
end loop;
end process;
-- Check if the XAM is in the XAMCAP register
process (s_FUNC_XAMCAP, XAm) begin
s_xamcap_match <= (others => '0');
for i in 0 to 7 loop
s_xamcap_match(i) <= s_FUNC_XAMCAP(i)(to_integer(unsigned(XAm)));
end loop;
end process;
end Behavioral;
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- VME64x Core
-- http://www.ohwr.org/projects/vme64x-core
--------------------------------------------------------------------------------
--
-- unit name: VME_CRAM (VME_CRAM.vhd)
--
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch>
--
-- description: CRAM memory
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vme64x_pack.all;
entity VME_CRAM is
generic (
g_BEG_CRAM : std_logic_vector(23 downto 0);
g_END_CRAM : std_logic_vector(23 downto 0)
);
port (
clk_i : in std_logic;
we_i : in std_logic;
addr_i : in std_logic_vector(18 downto 2);
data_i : in std_logic_vector( 7 downto 0);
data_o : out std_logic_vector( 7 downto 0)
);
end VME_CRAM;
architecture rtl of VME_CRAM is
type t_cram is array (f_size(g_BEG_CRAM, g_END_CRAM)-1 downto 0)
of std_logic_vector(7 downto 0);
signal s_cram : t_cram;
signal s_addr : unsigned(18 downto 2);
signal s_addr_1 : unsigned(18 downto 2);
begin
s_addr <= unsigned(addr_i(18 downto 2));
process (clk_i) begin
if rising_edge(clk_i) then
if we_i = '1' then
s_cram(to_integer(s_addr)) <= data_i;
end if;
s_addr_1 <= s_addr;
end if;
end process;
data_o <= s_cram(to_integer(s_addr_1));
end rtl;
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......@@ -91,33 +91,45 @@ end VME_User_CSR;
architecture rtl of VME_User_CSR is
signal s_addr : unsigned(18 downto 2);
signal s_irq_vector : std_logic_vector(7 downto 0);
signal s_irq_level : std_logic_vector(7 downto 0);
signal s_endian : std_logic_vector(7 downto 0);
signal s_wb32bits : std_logic_vector(7 downto 0);
signal s_reg_irq_vector : std_logic_vector(7 downto 0);
signal s_reg_irq_level : std_logic_vector(7 downto 0);
signal s_reg_endian : std_logic_vector(7 downto 0);
signal s_reg_wb32bits : std_logic_vector(7 downto 0);
-- Value for unused memory locations
constant c_UNUSED : std_logic_vector(7 downto 0) := x"ff";
begin
-- Addresses
constant c_IRQ_VECTOR : integer := 16#0002f#/4;
constant c_IRQ_LEVEL : integer := 16#0002b#/4;
constant c_ENDIAN : integer := 16#00023#/4;
constant c_TIME0_NS : integer := 16#0001f#/4;
constant c_TIME1_NS : integer := 16#0001b#/4;
constant c_TIME2_NS : integer := 16#00017#/4;
constant c_TIME3_NS : integer := 16#00013#/4;
constant c_TIME4_NS : integer := 16#0000f#/4;
constant c_BYTES0 : integer := 16#0000b#/4;
constant c_BYTES1 : integer := 16#00007#/4;
constant c_WB32BITS : integer := 16#00003#/4;
s_addr <= unsigned(addr_i);
begin
s_reg_wb32bits <= x"01" when g_WB_DATA_WIDTH = 32 else x"00";
s_wb32bits <= x"01" when g_WB_DATA_WIDTH = 32 else x"00";
-- Write
process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
s_reg_irq_vector <= x"00";
s_reg_irq_level <= x"00";
s_reg_endian <= x"00";
s_irq_vector <= x"00";
s_irq_level <= x"00";
s_endian <= x"00";
else
if we_i = '1' then
case s_addr is
when c_ADDR_IRQ_VECTOR(18 downto 2) => s_reg_irq_vector <= data_i;
when c_ADDR_IRQ_LEVEL(18 downto 2) => s_reg_irq_level <= data_i;
when c_ADDR_ENDIAN(18 downto 2) => s_reg_endian <= data_i;
case to_integer(unsigned(addr_i)) is
when c_IRQ_VECTOR => s_irq_vector <= data_i;
when c_IRQ_LEVEL => s_irq_level <= data_i;
when c_ENDIAN => s_endian <= data_i;
when others => null;
end case;
end if;
......@@ -125,9 +137,9 @@ begin
end if;
end process;
irq_vector_o <= s_reg_irq_vector;
irq_level_o <= s_reg_irq_level;
endian_o <= s_reg_endian(2 downto 0);
irq_vector_o <= s_irq_vector;
irq_level_o <= s_irq_level;
endian_o <= s_endian(2 downto 0);
-- Read
process (clk_i)
......@@ -136,19 +148,19 @@ begin
if rst_n_i = '0' then
data_o <= x"00";
else
case s_addr is
when c_ADDR_IRQ_VECTOR(18 downto 2) => data_o <= s_reg_irq_vector;
when c_ADDR_IRQ_LEVEL(18 downto 2) => data_o <= s_reg_irq_level;
when c_ADDR_ENDIAN(18 downto 2) => data_o <= s_reg_endian;
when c_ADDR_TIME0_NS(18 downto 2) => data_o <= time_i( 7 downto 0);
when c_ADDR_TIME1_NS(18 downto 2) => data_o <= time_i(15 downto 8);
when c_ADDR_TIME2_NS(18 downto 2) => data_o <= time_i(23 downto 16);
when c_ADDR_TIME3_NS(18 downto 2) => data_o <= time_i(31 downto 24);
when c_ADDR_TIME4_NS(18 downto 2) => data_o <= time_i(39 downto 32);
when c_ADDR_BYTES0(18 downto 2) => data_o <= bytes_i( 7 downto 0);
when c_ADDR_BYTES1(18 downto 2) => data_o <= bytes_i(15 downto 8);
when c_ADDR_WB32BITS(18 downto 2) => data_o <= s_reg_wb32bits;
when others => data_o <= x"ff";
case to_integer(unsigned(addr_i)) is
when c_IRQ_VECTOR => data_o <= s_irq_vector;
when c_IRQ_LEVEL => data_o <= s_irq_level;
when c_ENDIAN => data_o <= s_endian;
when c_TIME0_NS => data_o <= time_i( 7 downto 0);
when c_TIME1_NS => data_o <= time_i(15 downto 8);
when c_TIME2_NS => data_o <= time_i(23 downto 16);
when c_TIME3_NS => data_o <= time_i(31 downto 24);
when c_TIME4_NS => data_o <= time_i(39 downto 32);
when c_BYTES0 => data_o <= bytes_i( 7 downto 0);
when c_BYTES1 => data_o <= bytes_i(15 downto 8);
when c_WB32BITS => data_o <= s_wb32bits;
when others => data_o <= c_UNUSED;
end case;
end if;
end if;
......
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......@@ -142,6 +142,7 @@ entity xvme64x_core is
irq_level_i : in std_logic_vector( 7 downto 0) := (others => '0');
irq_vector_i : in std_logic_vector( 7 downto 0) := (others => '0');
endian_i : in std_logic_vector( 2 downto 0) := (others => '0');
function_o : out std_logic_vector( 3 downto 0);
user_csr_addr_o : out std_logic_vector(18 downto 2);
user_csr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
......@@ -275,6 +276,7 @@ begin -- wrapper
STALL_i => master_i.stall,
endian_i => endian_i,
function_o => function_o,
user_csr_addr_o => user_csr_addr_o,
user_csr_data_i => user_csr_data_i,
......
......@@ -54,7 +54,6 @@ package xvme64x_core_pkg is
type t_vme64x_out is record
iackout_n : std_logic;
dtack_oe : std_logic;
dtack_n : std_logic;
data_dir : std_logic;
......@@ -164,6 +163,7 @@ package xvme64x_core_pkg is
irq_level_i : in std_logic_vector( 7 downto 0) := (others => '0');
irq_vector_i : in std_logic_vector( 7 downto 0) := (others => '0');
endian_i : in std_logic_vector( 2 downto 0) := (others => '0');
function_o : out std_logic_vector( 3 downto 0);
user_csr_addr_o : out std_logic_vector(18 downto 2);
user_csr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
user_csr_data_o : out std_logic_vector( 7 downto 0);
......
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