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VME64x core
Commit 71c91f0b authored by dpedrett's avatar dpedrett
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vme64x_core Program ID 0x54. CRAM reduced to 1 KByte. 100 MHz clock supported 

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@154 665b4545-5c6b-4c24-801b-41150b02b44b
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hdl/vme64x-core/rtl/VME64xCore_Top.vhd
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hdl/vme64x-core/rtl/VME_Access_Decode.vhd
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hdl/vme64x-core/rtl/VME_Am_Match.vhd
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......@@ -5,15 +5,14 @@
--______________________________________________________________________________________
-- File: VME_ Am_Match.vhd
--______________________________________________________________________________________
-- Description: this component checks if the AM match the capability of the function.
-- Description: this component checks if the AM match.
-- If it is the corrispondent AmMatch's bit is asserted. This condition is necessary but
-- not sufficient to select the function and access the board.
-- If DFS = '0' the function supports only access modes with the same address width;
-- 1 function --> only 1 address width;
-- is sufficient check the AMCAP; AmMatch(i) <= s_FUNC_AMCAP(i)(to_integer(unsigned(Am))).
-- If DFS = '1' the function supports access modes with different address wide so AmMatch(i)
-- is asserted only if AMCAP(i)(to_integer(unsigned(Am))) = '1' and ADER[7:2] = AM and
-- s_FUNC_AMCAP(i)(to_integer(unsigned(Am)))='1'.
-- is asserted only if ADER[7:2] = AM and s_FUNC_AMCAP(i)(to_integer(unsigned(Am)))='1'.
-- If ADER(i)'s XAM bit is asserted than AmMatch(i) is asserted only if AM = 0x20 and if the
-- XAMCAP(i)(to_integer(unsigned(XAm))) = '1' and if DFS = '1' also ADER[9:2] must be equal
-- to XAM[7:0] lines.
......@@ -21,8 +20,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
-- Date 08/2012
-- Version v0.02
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -42,11 +41,14 @@ use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.vme64x_pack.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity VME_Am_Match is
Port ( clk_i : in std_logic;
s_reset : in std_logic;
s_mainFSMreset : in std_logic;
reset : in std_logic;
mainFSMreset : in std_logic;
Ader0 : in std_logic_vector (31 downto 0);
Ader1 : in std_logic_vector (31 downto 0);
Ader2 : in std_logic_vector (31 downto 0);
......@@ -74,10 +76,12 @@ entity VME_Am_Match is
Am : in std_logic_vector (5 downto 0);
XAm : in std_logic_vector (7 downto 0);
DFS_i : in std_logic_vector (7 downto 0);
s_decode : in std_logic;
decode : in std_logic;
AmMatch : out std_logic_vector (7 downto 0));
end VME_Am_Match;
--===========================================================================
-- Architecture declaration
--===========================================================================
architecture Behavioral of VME_Am_Match is
signal s_FUNC_ADER : t_FUNC_32b_array;
signal s_FUNC_AMCAP : t_FUNC_64b_array;
......@@ -85,6 +89,9 @@ architecture Behavioral of VME_Am_Match is
signal s_amcap_match : std_logic_vector(7 downto 0);
signal s_xamcap_match : std_logic_vector(7 downto 0);
signal debugAm : integer;
--===========================================================================
-- Architecture begin
--===========================================================================
begin
s_FUNC_ADER(0) <= unsigned(Ader0);
......@@ -117,10 +124,10 @@ begin
p_AMmatch : process(clk_i)
begin
if rising_edge(clk_i) then
if s_mainFSMreset = '1' or s_reset = '1' then
if mainFSMreset = '1' or reset = '1' then
AmMatch <= (others => '0');
debugAm <= 0;
elsif s_decode = '1' then
elsif decode = '1' then
for i in AmMatch'range loop
if DFS_i(i) = '1' then
if s_FUNC_ADER(i)(XAM_MODE) = '0' then
......@@ -171,4 +178,6 @@ begin
end process;
------------------------------------------------------
end Behavioral;
--===========================================================================
-- Architecture end
--===========================================================================
hdl/vme64x-core/rtl/VME_CRAM.vhd 0 → 100755
View file @ 71c91f0b
--______________________________________________________________________________|
-- VME TO WB INTERFACE |
-- |
-- CERN,BE/CO-HT |
--______________________________________________________________________________|
-- File: VME_CRAM.vhd |
--______________________________________________________________________________|
-- Description: RAM memory
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.02
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.vme64x_pack.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity VME_CRAM is
generic (dl : integer;
al : integer := f_log2_size(c_CRAM_SIZE)
);
port (clk : in std_logic;
we : in std_logic;
aw : in std_logic_vector(al - 1 downto 0);
di : in std_logic_vector(dl - 1 downto 0);
dw : out std_logic_vector(dl - 1 downto 0)
);
end VME_CRAM;
--===========================================================================
-- Architecture declaration
--===========================================================================
architecture syn of VME_CRAM is
type ram_type is array (2**al - 1 downto 0) of std_logic_vector (dl - 1 downto 0);
signal CRAM : ram_type;
--===========================================================================
-- Architecture begin
--===========================================================================
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
CRAM(conv_integer(aw)) <= di;
end if;
dw <= CRAM(conv_integer(aw));
end if;
end process;
end syn;
--===========================================================================
-- Architecture end
--===========================================================================
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
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hdl/vme64x-core/rtl/VME_CR_pack.vhd
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......@@ -11,7 +11,7 @@
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
-- Version v0.02
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -42,7 +42,7 @@ package VME_CR_pack is
constant c_amcapMBLT : std_logic_vector(63 downto 0) :=
"0000000000000000000000000000000000000000000000000000000100000000";
constant c_amcap1 : std_logic_vector(63 downto 0) :=
"1011101100000000000000000000000000000000000000000000000000001011"; --A24
"1011101100000000000000000000000000000000000000000000000000000000"; --A24
constant c_amcap2 : std_logic_vector(63 downto 0) :=
"0000000000000000001000100000000000000000000000000000000000000000"; --A16
constant c_amcapA64 : std_logic_vector(63 downto 0) :=
......@@ -117,13 +117,13 @@ package VME_CR_pack is
(
16#00# => (others => '0'),
-- Length of ROM
16#01# => x"01",
16#02# => x"00",
16#01# => x"00",
16#02# => x"10",
16#03# => x"00",
--Configuration ROM data acces width
16#04# => x"00",
16#04# => x"84", --D32, D16, D08
--CSR data acces width
16#05# => x"81", -- it was 01...changed by Davide
16#05# => x"84", --D32, D16, D08
--CR/CSR Space Specification ID
16#06# => x"01",
--Ascii "C"
......@@ -144,48 +144,48 @@ package VME_CR_pack is
16#11# => x"04",
16#12# => x"04",
16#13# => x"03",
--Point to ascii null terminatied
--Point to ascii null terminatied
16#14# => x"00",
16#15# => x"00",
16#16# => x"00",
--Program Id code
16#1F# => x"02",
--Offset to BEG_USER_CR --Added by Davide
--Program Id code
16#1F# => x"54",
--Offset to BEG_USER_CR
16#20# => x"00",
16#21# => x"00",
16#22# => x"00",
--Offset to END_USER_CR --Added by Davide
--Offset to END_USER_CR
16#23# => x"00",
16#24# => x"00",
16#25# => x"00",
--Offset to BEG_CRAM --Added by Davide
--Offset to BEG_CRAM
16#26# => x"00",
16#27# => x"10", --10
16#28# => x"00", --00
--Offset to END_CRAM --Added by Davide
16#29# => x"07",
16#2A# => x"fb",
16#27# => x"10",
16#28# => x"00",
--Offset to END_CRAM
16#29# => x"00",
16#2A# => x"13",
16#2B# => x"ff",
--Offset to BEG_USER_CSR --Added by Davide
--Offset to BEG_USER_CSR
16#2C# => x"00",
16#2D# => x"00",
16#2E# => x"00", --NB: 0x7fbf0 and NOT 0x7fbf3 because is possible access with D32 mode
--Offset to END_USER_CSR --Added by Davide
16#2E# => x"00", -- 0x7fbf0 and NOT 0x7fbf3 because is possible access with D32 mode
--Offset to END_USER_CSR
16#2F# => x"00",
16#30# => x"00",
16#31# => x"00",
--CRAM_ACCESS_WIDTH
16#39# => x"81",
16#3f# => x"84", --D32, D16, D08
--Function data access width
16#40# => x"85", -- Fun 0 accepts MD32, D16, D08(EO) cycles
16#41# => x"85", -- Fun 1
16#42# => x"85", -- Fun 2
16#43# => x"85", -- Fun 3
16#44# => x"85", -- Fun 4
16#45# => x"85", -- Fun 5
16#46# => x"85", -- Fun 6
16#47# => x"85", -- Fun 7
16#40# => x"86", -- Fun 0 accepts D64, D32, D16, D08(EO) cycles
16#41# => x"86", -- Fun 1
16#42# => x"86", -- Fun 2
16#43# => x"86", -- Fun 3
16#44# => x"86", -- Fun 4
16#45# => x"86", -- Fun 5
16#46# => x"86", -- Fun 6
16#47# => x"86", -- Fun 7
--Function AM code Mask
......
hdl/vme64x-core/rtl/VME_CSR_pack.vhd
View file @ 71c91f0b
......@@ -11,7 +11,7 @@
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
-- Version v0.02
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -78,7 +78,7 @@ FUNC6_ADER_3 =>x"00",
IRQ_Vector =>x"00", --"00" because each Slot has a different IRQ Vector
-- and the VME Master should set this value
IRQ_level =>x"02",
WB32or64 =>x"01", -- 32 bit WB of default
WB32or64 =>x"00", -- 32 bit WB of default
others => (others => '0'));
end VME_CSR_pack;
......
hdl/vme64x-core/rtl/VME_DpBlockRam.vhd deleted 100755 → 0
View file @ 94d5e1de
--==============================================================--
--Design Units : CTX1 Control and Statistics
--Size:
--Speed:
--File Name: MebRam.vhd
--
--Purpose: The dpblockram implements a synthetisable model of a
-- dual port RAM.
-- There are an input data and addr ports to allow the
-- writing at the reception of a GMT frame.
-- The output data and addr ports allow a simultanous
-- reading of the circular buffer by the user, at the
-- same time than it is beeing written.
--
-- The frame and the millisecond stamp are stored in the
-- same ram word. It is the task of the MEB block to
-- separate the frame data from the millisecond stamp data.
--
--Limitations:
--
--Errors:
--
--Libraries:
--
--Dependancies: It instantiates a synthetisable model of a DPRAM
-- See MebRam.vhd
--
--Author: Pablo Antonio Alvarez Sanchez
-- European Organisation for Nuclear Research
-- SL SPS/LHC -- Control -- Timing Division
-- CERN, Geneva, Switzerland, CH-1211
-- Building 864 Room 1 - A24
--
--Simulator: ModelSim XE 5.5e_p1
--==============================================================--
--Revision List
--Version Author Date Changes
--
--1.0 PAAS 30.09.2002 Added comments, tested with the
-- rest of the design
--==============================================================--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dpblockram is
generic (dl : integer := 8; -- Length of the data word
al : integer := 19; -- Size of the addr map (10 = 1024 words)
nw : integer := 2**19); -- Number of words
-- 'nw' has to be coherent with 'al'
port (clk : in std_logic; -- Global Clock
we : in std_logic; -- Write Enable
aw : in std_logic_vector(al - 1 downto 0); -- Write Address
ar : in std_logic_vector(al - 1 downto 0); -- Read Address
di : in std_logic_vector(dl - 1 downto 0); -- Data input
dw : out std_logic_vector(dl - 1 downto 0); -- Data write, normaly open
do : out std_logic_vector(dl - 1 downto 0)); -- Data output
end dpblockram;
-- DATA OUTPUT NOT REGISTERED!
--library synplify;
--use synplify.attributes.all;
architecture syn of dpblockram is
type ram_type is array (nw - 1 downto 0) of std_logic_vector (dl - 1 downto 0);
signal CRAM : ram_type;
signal read_a : std_logic_vector(al - 1 downto 0);
signal read_ar : std_logic_vector(al - 1 downto 0);
--attribute syn_ramstyle of RAM : signal is "block_ram";
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
CRAM(conv_integer(aw)) <= di;
end if;
read_a <= aw;
read_ar <= ar;
end if;
end process;
dw <= CRAM(conv_integer(read_a));
do <= CRAM(conv_integer(read_ar)); -- Notice that the Data Output is not registered
end syn;
hdl/vme64x-core/rtl/VME_Funct_Match.vhd
View file @ 71c91f0b
......@@ -6,16 +6,16 @@
-- File: VME_Funct_Match.vhd
--_________________________________________________________________________________________
-- Description: this component compares the Address with the ADER using the mask bits and
-- if the base address match asserts the corrisponding bit of the FunctMatch signal and
-- latches the base address that will be subtract at the Address before access the WB bus.
-- FunctMatch /= 0 is necessary but not sufficient to select one function and access the board,
-- if the base address match it asserts the corrisponding bit in the FunctMatch vector and it
-- latches the base address that will be subtract to the Address before accessing the WB bus.
-- FunctMatch /= 0 is necessary but not sufficient to select one function and to access the board,
-- indeed also the AM has to be checked (VME_AM_Match.vhd component).
-- For better understanding how this component works here one example:
-- base address = 0xc0
-- access mode: A32_S --> AM = 0x09
-- The Master write the ADERi = 0xc0000024
-- The Master writes the ADERi = 0xc0000024
-- ADEMi = 0xffffff04 --> DFS = '1' --> all the mask bits are '1'!!
-- The Master want access at the location 0x08: Address= 0xc0000008
-- The Master wants to access the location 0x08: Address= 0xc0000008
-- For i = 0 to 7 check:
-- Check if the ADEMi is compatible with the AM selected: ADEMi[31:8] /= 0
-- Address[31:8] and ADEMi[31:8] ADERi[31:8] and ADEMi[31:8]
......@@ -41,8 +41,9 @@
-- |_______|
-- No | |yes
-- FunctMatch(i) <= '0'_____| |______FunctMatch(i) <= '1'
-- DFS = '1' --> 1 function --> multiple access mode
-- The Master access with different mode only changing the ADER registers if the
--
-- DFS = '1' --> 1 function --> multiple access modes
-- The Master accesses with different modes only changing the ADER registers if the
-- DFS bit is asserted but:
-- It is easy to see that if DFS = '1' we can only address 256 bytes, indeed eg:
-- base address = 0xc0
......@@ -93,7 +94,7 @@
-- Yes, it is. Indeed now suppose that we are in this situation:
-- ADERi = 0x00000000
-- ADEMi = 0x0000ff00 --> DFS = '0'
-- A VME Master access to VMEbus for accessing at another board:
-- A VME Master takes the ownership of the VMEbus for accessing another board:
-- base address = 0xc0
-- access mode: A32_S --> AM = 0x09
-- The Master want access at the location 0x0008: Address= 0xc0000008
......@@ -113,7 +114,7 @@
-- If DFS is '1' AmMatch(i) is zero becouse ADER[7:2] is 0 (see VME_Am_Match.vhd) and
-- also FunctMatch(i) is 0 because ADEMi should has all the mask bits '1'.
--
--Follow an example about A64 access mode:
-- An example about A64 access mode:
-- base address = 0xc0
-- access mode: A64_S --> AM = 0x01
-- ADEM(i) = 0x00000001 --> EFM = '1' and DFS = '0'
......@@ -126,7 +127,7 @@
-- ADER64(i) = ADER(i+1) & ADER(i)
-- s_isprev_func64(i+1) --> '1' --> don't check if the function i + 1 is selected
-- because the next ADER and ADEM are used to decode the function i.
-- The Master want access at the location 0x0008: Address= 0xc000000000000008
-- The Master accesses the location 0x0008: Address= 0xc000000000000008
-- Check if the ADEM64i is compatible with the AM selected: ADEM64(i)[63:10] /= 0
-- Address[63:10] and ADEM64(i)[63:10] ADER64(i)[63:10] and ADEM64(i)[63:10]
-- | |
......@@ -137,12 +138,12 @@
-- No | |yes
-- FunctMatch(i) <= '0'_____| |______FunctMatch(i) <= '1'
--
-- For the 2e modes is the same, change only the ADER(i)'s XAM bit that must be '1'.
-- For the 2e modes it is the same, it changes only the ADER(i)'s XAM bit that must be '1'.
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Date 08/2012
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
......@@ -162,12 +163,15 @@ use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.vme64x_pack.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity VME_Funct_Match is
Port ( clk_i : in std_logic;
s_reset : in std_logic;
s_decode : in std_logic;
s_mainFSMreset : in std_logic;
reset : in std_logic;
decode : in std_logic;
mainFSMreset : in std_logic;
Addr : in std_logic_vector(63 downto 0);
AddrWidth : in std_logic_vector(1 downto 0);
Ader0 : in std_logic_vector(31 downto 0);
......@@ -191,24 +195,29 @@ entity VME_Funct_Match is
Nx_Base_Addr : out std_logic_vector(63 downto 0)
);
end VME_Funct_Match;
--===========================================================================
-- Architecture declaration
--===========================================================================
architecture Behavioral of VME_Funct_Match is
signal s_FUNC_ADER, s_FUNC_ADEM : t_FUNC_32b_array;
signal s_FUNC_ADER_64, s_FUNC_ADEM_64: t_FUNC_64b_array;
signal s_isprev_func64 : std_logic_vector(7 downto 0);
signal s_locAddr : unsigned(63 downto 0);
signal debugfunct : integer;
--===========================================================================
-- Architecture begin
--===========================================================================
begin
s_locAddr <= unsigned(Addr);
p_functMatch : process(clk_i)
begin
if rising_edge(clk_i) then
if s_mainFSMreset = '1' or s_reset = '1' then
if mainFSMreset = '1' or reset = '1' then
FunctMatch <= (others => '0');
Nx_Base_Addr <= (others => '0');
debugfunct <= 0;
elsif s_decode = '1' then
elsif decode = '1' then
for i in FunctMatch'range loop
case AddrWidth is
......@@ -306,4 +315,6 @@ begin
s_isprev_func64(0) <= '0';
s_FUNC_ADEM_64(7) <= (others => '0');
end Behavioral;
--===========================================================================
-- Architecture end
--===========================================================================
hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd
View file @ 71c91f0b
......@@ -6,7 +6,7 @@
-- File: VME_IRQ_Controller.vhd
--_________________________________________________________________________________________
-- Description:
-- This block acts as Interrupter; phases of an interrupt cycle:
-- This block acts as Interrupter. Phases of an interrupt cycle:
-- 1) The Interrupt Controller receives an interrupt request by the WB bus;
-- this request is a pulse on the INT_Req input
-- 2) The Interrupt Controller asserts ('0') one of the 7 VME_IRQ lines; --> request of a service.
......@@ -20,10 +20,10 @@
-- indicated on the address lines A1, A2 and A3,the data transfer width during the interrupt
-- acknowledge cycle should be equal or greater than the size the it can respond with, and
-- it shall receive a falling edge on its IACKIN*.
-- 5) If the it is the responding interrupter should send the source/ID on the VME_DATA lines
-- 5) If it is the responding interrupter should send the source/ID on the VME_DATA lines
-- (in our case the source/ID is the INT_Vector that the Master can write in the corresponding
-- register in the CR/CSR space) and terminates the interrupt cycle with an acknowledge and
-- releases the IRQ line. If it isn't the responding interrupter should pass a falling edge on
-- register in the CR/CSR space) and it terminates the interrupt cycle with an acknowledge before
-- releasing the IRQ lines. If it isn't the responding interrupter, it should pass a falling edge on
-- down the daisy-chain so other interrupters can respond.
--
-- All the output signals are registered
......@@ -75,8 +75,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
-- Date 08/2012
-- Version v0.02
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -94,7 +94,9 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.vme64x_pack.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity VME_IRQ_Controller is
Port ( clk_i : in std_logic;
reset : in std_logic;
......@@ -114,7 +116,9 @@ entity VME_IRQ_Controller is
VME_DATA_o : out std_logic_vector (31 downto 0);
VME_DATA_DIR_o : out std_logic);
end VME_IRQ_Controller;
--===========================================================================
-- Architecture declaration
--===========================================================================
architecture Behavioral of VME_IRQ_Controller is
--input signals
signal INT_Req_sample : std_logic;
......@@ -140,7 +144,9 @@ architecture Behavioral of VME_IRQ_Controller is
signal VME_DS_latched : std_logic_vector(1 downto 0);
signal DSlatch : std_logic;
signal ADDRmatch : std_logic;
--===========================================================================
-- Architecture begin
--===========================================================================
begin
-- Input sampling and edge detection
......@@ -305,6 +311,7 @@ begin
end process;
-- Update Outputs
-- Mealy FSM
process(currs,VME_AS1_n_i)
begin
case currs is
......@@ -460,5 +467,7 @@ begin
VME_DTACK_OE_o <= s_DTACK_OE_o;
VME_IACKOUT_n_o <= s_IACKOUT_o;
end Behavioral;
--===========================================================================
-- Architecture end
--===========================================================================
hdl/vme64x-core/rtl/VME_Init.vhd
View file @ 71c91f0b
......@@ -9,8 +9,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
-- Date 08/2012
-- Version v0.02
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -30,6 +30,9 @@ use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.vme64x_pack.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity VME_Init is
Port ( clk_i : in std_logic;
RSTedge : inout std_logic;
......@@ -69,7 +72,11 @@ entity VME_Init is
FUNC7_XAMCAP_o : out std_logic_vector (255 downto 0));
end VME_Init;
--===========================================================================
-- Architecture declaration
--===========================================================================
architecture Behavioral of VME_Init is
signal s_initReadCounter : unsigned(8 downto 0);
signal s_initState : t_initState;
signal s_latchCRdata : std_logic; -- Stores read CR data
......@@ -88,7 +95,10 @@ architecture Behavioral of VME_Init is
signal s_END_USER_CR : unsigned(23 downto 0);
signal s_BEG_CRAM : unsigned(23 downto 0);
signal s_END_CRAM : unsigned(23 downto 0);
--===========================================================================
-- Architecture begin
--===========================================================================
begin
InitReadCount <= std_logic_vector(s_initReadCounter);
s_CRaddr <= unsigned(CRAddr);
......@@ -107,8 +117,8 @@ begin
s_initReadCounter <= to_unsigned(0, s_initReadCounter'length);
s_latchCRdata <= '0';
s_initState <= SET_ADDR;
when SET_ADDR =>
s_initReadCounter <= s_initReadCounter+1;
s_latchCRdata <= '0';
s_initState <= GET_DATA;
......@@ -243,4 +253,6 @@ begin
FUNC7_XAMCAP_o <= std_logic_vector(s_FUNC_XAMCAP(7));
end Behavioral;
--===========================================================================
-- Architecture end
--===========================================================================
hdl/vme64x-core/rtl/VME_SharedComps.vhd
View file @ 71c91f0b
......@@ -60,7 +60,30 @@ begin
end if;
end process;
end RTL;
--***************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity SingleRegInputSample is
generic(
width: natural:=8
);
port (
reg_i: in std_logic_vector(width-1 downto 0);
reg_o: out std_logic_vector(width-1 downto 0);
clk_i: in std_logic
);
end SingleRegInputSample;
architecture RTL of SingleRegInputSample is
begin
process(clk_i)
begin
if rising_edge(clk_i) then
reg_o <= reg_i;
end if;
end process;
end RTL;
-- ***************************************************
--FlipFlopD
library IEEE;
......
hdl/vme64x-core/rtl/VME_Wb_master.vhd
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hdl/vme64x-core/rtl/VME_bus.vhd
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hdl/vme64x-core/rtl/VME_swapper.vhd
View file @ 71c91f0b
......@@ -13,8 +13,8 @@
--______________________________________________________________________________
-- Authors:
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
-- Date 08/2012
-- Version v0.02
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -30,13 +30,17 @@
---------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--===========================================================================
-- Entity declaration
--===========================================================================
entity VME_swapper is
Port ( d_i : in STD_LOGIC_VECTOR (63 downto 0);
sel : in STD_LOGIC_VECTOR (2 downto 0);
d_o : out STD_LOGIC_VECTOR (63 downto 0));
end VME_swapper;
--===========================================================================
-- Architecture declaration
--===========================================================================
architecture Behavioral of VME_swapper is
signal Byte0_i : std_logic_vector(7 downto 0);
signal Byte1_i : std_logic_vector(7 downto 0);
......@@ -54,7 +58,11 @@ signal Byte4_o : std_logic_vector(7 downto 0);
signal Byte5_o : std_logic_vector(7 downto 0);
signal Byte6_o : std_logic_vector(7 downto 0);
signal Byte7_o : std_logic_vector(7 downto 0);
--===========================================================================
-- Architecture begin
--===========================================================================
begin
process (sel,Byte0_i,Byte1_i,Byte2_i,Byte3_i,Byte7_i)
begin
case sel is
......@@ -168,6 +176,7 @@ d_o(47 downto 40) <= Byte5_o;
d_o(55 downto 48) <= Byte6_o;
d_o(63 downto 56) <= Byte7_o;
end Behavioral;
--===========================================================================
-- Architecture end
--===========================================================================
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @ 71c91f0b
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