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Commit 6be70e8c authored by dpedrett's avatar dpedrett
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WB bridge and IRQ Generator for WB data bus 32 or 64 bit 

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@155 665b4545-5c6b-4c24-801b-41150b02b44b
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hdl/boards/svec/rtl/IRQ_Generator_Top.vhd 0 → 100644
View file @ 6be70e8c
--______________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--______________________________________________________________________
-- File: IRQ_Generator_Top.vhd
--______________________________________________________________________
-- Description: This block implement a IRQ_Generator both WB 32 or 64
-- data transfer bus width compatible.
-- Block diagram:
-- ____________________________________________
-- | |
-- | |
-- | __________ ______________ |
-- | | WB | | INT_COUNT | |
-- | | LOGIC | |______________| |
-- W | | | ______________ |
-- B | | | | FREQ | |
-- | | | |______________| |
-- S | | | ______________ |
-- I | | | | | |
-- G | | | | | |
-- N | | | | IRQ | |
-- A | | | |Generator.vhd | |
-- L | | | | | |
-- S | | | | | |
-- | | | | | |
-- | |__________| | | |
-- | | | |
-- | |______________| |
-- | |
-- | |
-- |____________________________________________|
--
-- INT_COUNT --> address: 0x000
-- FREQ --> address: 0x004
-- IRQ Generator: this component sends an Interrupt request (pulse) to the
-- IRQ Controller --> Necessary to test the board.
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use work.vme64x_pack.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity IRQ_Generator_Top is
generic(g_width : integer := c_width;
g_addr_width : integer := c_addr_width
);
port ( -- IRQ_Generator
clk_i : in std_logic;
rst_i : in std_logic;
Int_Ack_i : in std_logic;
Int_Req_o : out std_logic;
-- wb slave side
cyc_i : in std_logic;
stb_i : in std_logic;
adr_i : in std_logic_vector (g_addr_width - 1 downto 0);
sel_i : in std_logic_vector (f_div8(g_width) - 1 downto 0);
we_i : in std_logic;
dat_i : in std_logic_vector (g_width - 1 downto 0);
ack_o : out std_logic;
err_o : out std_logic;
rty_o : out std_logic;
stall_o : out std_logic;
dat_o : out std_logic_vector (g_width - 1 downto 0)
);
end IRQ_Generator_Top;
--===========================================================================
-- Architecture declaration
--===========================================================================
architecture Behavioral of IRQ_Generator_Top is
signal s_rst : std_logic;
signal s_INT_COUNT : std_logic_vector(31 downto 0);
signal s_FREQ : std_logic_vector(31 downto 0);
signal s_Int_Count_o1 : std_logic_vector(31 downto 0);
signal s_Int_Count_o : std_logic_vector(31 downto 0);
signal s_Read_IntCount : std_logic;
signal s_data : std_logic_vector(31 downto 0);
signal s_data_f : std_logic_vector(31 downto 0);
signal s_data_o : std_logic_vector(g_width - 1 downto 0);
signal s_IntCount_sel : std_logic;
signal s_Freq_sel : std_logic;
signal s_wea : std_logic;
signal s_stall : std_logic;
signal s_ack : std_logic;
signal s_en_Freq : std_logic;
component IRQ_generator is
port(
clk_i : in std_logic;
reset : in std_logic;
Freq : in std_logic_vector(31 downto 0);
Int_Count_i : in std_logic_vector(31 downto 0);
Read_Int_Count : in std_logic;
INT_ack : in std_logic;
IRQ_o : out std_logic;
Int_Count_o : out std_logic_vector(31 downto 0)
);
end component IRQ_generator;
--===========================================================================
-- Architecture begin
--===========================================================================
begin
s_rst <= not(rst_i);
s_wea <= we_i and cyc_i and stb_i and (not s_stall);
s_Int_Count_o1 <= s_data when (s_IntCount_sel = '1' and s_wea = '1')
else s_Int_Count_o;
s_Read_IntCount <= '1' when s_IntCount_sel = '1' and we_i = '0' and s_ack = '1'
else '0';
s_en_Freq <= '1' when (s_Freq_sel = '1' and s_wea = '1') else '0';
------------------------------------------------------------------------------------
-- The INT_COUNT register and the INT_RATE register should be write/read both when
-- the WB data bus is 32 or 64 bit width, so the following processes have been
-- added:
gen64 : if (g_width = 64) generate
s_data <= dat_i(63 downto 32);
s_data_f <= dat_i(31 downto 0);
s_data_o <= s_INT_COUNT & s_FREQ;
s_IntCount_sel <= '1' when sel_i = "11110000" and unsigned(adr_i) = 0 else
'0' ;
s_Freq_sel <= '1' when sel_i = "00001111" and unsigned(adr_i) = 0 else
'0';
end generate gen64;
gen32 : if (g_width = 32) generate
s_data <= dat_i;
s_data_f <= dat_i;
s_data_o <= s_INT_COUNT when s_IntCount_sel = '1' else
s_FREQ when s_Freq_sel = '1' else
(others => '0');
s_IntCount_sel <= '1' when unsigned(adr_i) = 0 else
'0' ;
s_Freq_sel <= '1' when unsigned(adr_i) = 1 else
'0';
end generate gen32;
---------------------------------------------------------------
-- this process generate the ack; PIPELINED mode!
process(clk_i)
begin
if(rising_edge(clk_i)) then
if(s_rst = '0') then
s_ack <= '0';
else
s_ack <= cyc_i and stb_i and (not s_stall) ;
end if;
end if;
end process;
----------------------------------------------------------------
-- stall handler
process(clk_i)
begin
if(rising_edge(clk_i)) then
if(s_rst = '0') or s_ack = '1' then
s_stall <= '1';
elsif cyc_i = '1' then
s_stall <= '0';
end if;
end if;
end process;
-- Reg INT_COUNT
INT_COUNT : Reg32bit
port map(
reset => s_rst,
enable => '1',
di => s_Int_Count_o1,
do => s_INT_COUNT,
clk_i => clk_i
);
-- Reg FREQ
FREQ : Reg32bit
port map(
reset => s_rst,
enable => s_en_Freq,
di => s_data_f,
do => s_FREQ,
clk_i => clk_i
);
-- IRQ Generator
Inst_IRQ_generator: IRQ_generator port map(
clk_i => clk_i,
reset => s_rst,
Freq => s_FREQ,
Int_Count_i => s_INT_COUNT,
Read_Int_Count => s_Read_IntCount,
INT_ack => Int_Ack_i,
IRQ_o => Int_Req_o,
Int_Count_o => s_Int_Count_o
);
------------------------------------------------------------------
stall_o <= s_stall;
ack_o <= s_ack;
err_o <= '0';
rty_o <= '0';
dat_o <= s_data_o;
end Behavioral;
--===========================================================================
-- Architecture end
--===========================================================================
hdl/boards/svec/rtl/IRQ_generator.vhd
View file @ 6be70e8c
......@@ -57,11 +57,12 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
-- Date 08/2012
-- Version v0.02
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
......@@ -75,9 +76,12 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.vme64x_pack.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity IRQ_generator is
Port ( clk_i : in std_logic;
port ( clk_i : in std_logic;
reset : in std_logic;
Freq : in std_logic_vector (31 downto 0);
Int_Count_i : in std_logic_vector (31 downto 0);
......@@ -86,8 +90,11 @@ entity IRQ_generator is
IRQ_o : out std_logic;
Int_Count_o : out std_logic_vector (31 downto 0));
end IRQ_generator;
--===========================================================================
-- Architecture declaration
--===========================================================================
architecture Behavioral of IRQ_generator is
type t_FSM is (IDLE, CHECK, INCR, IRQ, WAIT_INT_ACK, WAIT_RD);
signal s_en_int : std_logic;
signal currs, nexts : t_FSM;
......@@ -101,16 +108,18 @@ signal s_incr : std_logic;
signal s_gen_irq : std_logic;
signal s_count0 : std_logic;
signal s_Freq : std_logic_vector(31 downto 0);
--===========================================================================
-- Architecture begin
--===========================================================================
begin
-- In/Out sample
RDinputSample : entity work.DoubleSigInputSample
RDinputSample : DoubleSigInputSample
port map(
sig_i => Read_Int_Count,
sig_o => s_Rd_Int_Count_delayed,
clk_i => clk_i
);
IRQOutputSample : entity work.FlipFlopD
IRQOutputSample : FlipFlopD
port map(
sig_i => s_IRQ_o,
sig_o => IRQ_o,
......@@ -263,6 +272,7 @@ begin
end process;
-- Update outputs
-- Moore FSM
process(currs)
begin
case currs is
......@@ -294,4 +304,6 @@ end process;
Int_Count_o <= std_logic_vector(s_count_int);
end Behavioral;
--===========================================================================
-- Architecture end
--===========================================================================
hdl/boards/svec/rtl/TOP_LEVEL.vhd
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hdl/boards/svec/rtl/WB_Bridge.vhd 0 → 100644
View file @ 6be70e8c
--______________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--______________________________________________________________________
-- File: WB_Bridge.vhd
--_____________________________________________________________________________
-- Description: Insert this block between the vme64x core and your WB Application
-- if you want use the Interrupter.
-- Indeed this component acts as a bridge between the vme64x core and your WB
-- Application, and implements the IRQ Generator that sends the Interrupt request
-- to the IRQ_Controller located in the vme64x core.
-- Remember that:
-- INT_COUNT register --> 0x00
-- INT_RATE register --> 0x04
-- These two address (byte address) are reserved; don't use these to access
-- your WB memory!
--
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.vme64x_pack.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity WB_Bridge is
generic(g_width : integer := c_width;
g_addr_width : integer := c_addr_width
);
Port ( clk_i : in std_logic;
rst_i : in std_logic;
Int_Ack_i : in std_logic;
Int_Req_o : out std_logic;
cyc_i : in std_logic;
stb_i : in std_logic;
adr_i : in std_logic_vector (g_addr_width - 1 downto 0);
dat_i : in std_logic_vector (g_width - 1 downto 0);
sel_i : in std_logic_vector (f_div8(g_width) - 1 downto 0);
we_i : in std_logic;
ack_o : out std_logic;
err_o : out std_logic;
rty_o : out std_logic;
stall_o : out std_logic;
dat_o : out std_logic_vector (g_width - 1 downto 0);
m_cyc_o : out std_logic;
m_stb_o : out std_logic;
m_adr_o : out std_logic_vector (g_addr_width - 1 downto 0);
m_dat_o : out std_logic_vector (g_width - 1 downto 0);
m_sel_o : out std_logic_vector (f_div8(g_width) - 1 downto 0);
m_we_o : out std_logic;
m_ack_i : in std_logic;
m_err_i : in std_logic;
m_stall_i : in std_logic;
m_rty_i : in std_logic;
m_dat_i : in std_logic_vector (g_width - 1 downto 0));
end WB_Bridge;
--===========================================================================
-- Architecture declaration
--===========================================================================
architecture Behavioral of WB_Bridge is
signal s_cyc : std_logic;
signal s_m_cyc : std_logic;
signal s_stb : std_logic;
signal s_m_stb : std_logic;
signal s_WbAppl : std_logic;
signal s_IRQGen : std_logic;
signal s_ack_gen : std_logic;
signal s_err_gen : std_logic;
signal s_rty_gen : std_logic;
signal s_stall_gen : std_logic;
signal s_data_o_gen : std_logic_vector(g_width - 1 downto 0);
component IRQ_Generator_Top is
generic(g_width : integer := c_width;
g_addr_width : integer := c_addr_width
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
Int_Ack_i : in std_logic;
cyc_i : in std_logic;
stb_i : in std_logic;
adr_i : in std_logic_vector(g_addr_width - 1 downto 0);
sel_i : in std_logic_vector(f_div8(g_width) - 1 downto 0);
we_i : in std_logic;
dat_i : in std_logic_vector(g_width - 1 downto 0);
Int_Req_o : out std_logic;
ack_o : out std_logic;
err_o : out std_logic;
rty_o : out std_logic;
stall_o : out std_logic;
dat_o : out std_logic_vector(g_width - 1 downto 0)
);
end component IRQ_Generator_Top;
--===========================================================================
-- Architecture begin
--===========================================================================
begin
---------------------------------------------------------------------
-- check if the IRQ Generator is addressed (0x00 or 0x04).
-- if not s_WbAppl is '1' and the component work as a bridge
-- between the vme64x core and the Wb Application
genIRQGen64 : if (g_width = 64) generate
s_IRQGen <= '1' when (unsigned(adr_i) = 0) else '0';
end generate genIRQGen64;
genIRQGen32 : if (g_width = 32) generate
s_IRQGen <= '1' when unsigned(adr_i) = 0 or
unsigned(adr_i) = 1 else '0';
end generate genIRQGen32;
s_WbAppl <= not s_IRQGen;
---------------------------------------------------------------------
s_cyc <= cyc_i and s_IRQGen;
s_stb <= stb_i and s_IRQGen;
s_m_cyc <= cyc_i and s_WbAppl;
s_m_stb <= stb_i and s_WbAppl;
----------------------------------------------------------------------
ack_o <= s_ack_gen xor m_ack_i;
err_o <= s_err_gen xor m_err_i;
rty_o <= s_rty_gen xor m_rty_i;
----------------------------------------------------------------------
stall_o <= m_stall_i when s_WbAppl ='1' else
s_stall_gen;
dat_o <= m_dat_i when s_WbAppl ='1' else
s_data_o_gen;
----------------------------------------------------------------------
m_cyc_o <= s_m_cyc;
m_stb_o <= s_m_stb;
m_adr_o <= adr_i;
m_dat_o <= dat_i;
m_sel_o <= sel_i;
m_we_o <= we_i;
----------------------------------------------------------------------
Inst_IRQ_Generator_Top: IRQ_Generator_Top
generic map(g_width => c_width,
g_addr_width => c_addr_width
)
port map(
clk_i => clk_i,
rst_i => rst_i,
Int_Ack_i => Int_Ack_i,
Int_Req_o => Int_Req_o,
cyc_i => s_cyc,
stb_i => s_stb,
adr_i => adr_i,
sel_i => sel_i,
we_i => we_i,
dat_i => dat_i,
ack_o => s_ack_gen,
err_o => s_err_gen,
rty_o => s_rty_gen,
stall_o => s_stall_gen,
dat_o => s_data_o_gen
);
end Behavioral;
--===========================================================================
-- Architecture end
--===========================================================================
hdl/boards/svec/rtl/genram_pkg.vhd
View file @ 6be70e8c
......@@ -40,7 +40,8 @@ library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
package genram_pkg is
constant c_SIZE : natural := 1024;
function f_log2_size (A : natural) return natural;
-- Single-port synchronous RAM
......
hdl/boards/svec/rtl/ram_8bits.vhd
View file @ 6be70e8c
......@@ -9,8 +9,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
-- Date 08/2012
-- Version v0.02
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -29,11 +29,12 @@ use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
library work;
use work.genram_pkg.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity ram_8bits is
generic (
size : natural := 256
size : natural := c_SIZE
);
Port ( addr : in std_logic_vector (f_log2_size(size)-1 downto 0);
di : in std_logic_vector (7 downto 0);
......@@ -41,10 +42,15 @@ entity ram_8bits is
we : in std_logic;
clk_i : in std_logic);
end ram_8bits;
--===========================================================================
-- Architecture declaration
--===========================================================================
architecture Behavioral of ram_8bits is
type t_ram_type is array(size-1 downto 0) of std_logic_vector(7 downto 0);
signal sram : t_ram_type;
--===========================================================================
-- Architecture begin
--===========================================================================
begin
process (clk_i)
begin
......@@ -56,4 +62,6 @@ process (clk_i)
end if;
end process;
end Behavioral;
--===========================================================================
-- Architecture end
--===========================================================================
hdl/boards/svec/rtl/spram.vhd
View file @ 6be70e8c
......@@ -11,8 +11,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
-- Date 08/2012
-- Version v0.02
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -33,12 +33,15 @@ use ieee.std_logic_arith.all;
library work;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity spram is
generic (
-- standard parameters
g_data_width : natural := 64;
g_size : natural := 256;
g_data_width : natural := c_wishbone_data_width;
g_size : natural := c_SIZE;
-- if true, the user can write individual bytes by using bwe_i
g_with_byte_enable : boolean := true; --not used
-- RAM read-on-write conflict resolution. Can be "read_first" (read-then-write)
......@@ -58,15 +61,19 @@ port (
q_o : out std_logic_vector(g_data_width-1 downto 0)
);
end spram;
--===========================================================================
-- Architecture declaration
--===========================================================================
architecture Behavioral of spram is
constant c_num_bytes : integer := (g_data_width)/8;
--===========================================================================
-- Architecture begin
--===========================================================================
begin
spram: for i in 0 to c_num_bytes-1 generate
ram8bits : entity work.ram_8bits
generic map(g_size)
generic map(size => c_SIZE)
port map(addr => a_i,
di => d_i(8*i+7 downto 8*i),
do => q_o(8*i+7 downto 8*i),
......@@ -76,4 +83,6 @@ begin
end generate;
end Behavioral;
--===========================================================================
-- Architecture end
--===========================================================================
hdl/boards/svec/rtl/wishbone_pkg.vhd
View file @ 6be70e8c
......@@ -15,7 +15,7 @@ package wishbone_pkg is
subtype t_wishbone_data is
std_logic_vector(c_wishbone_data_width-1 downto 0);
subtype t_wishbone_byte_select is
std_logic_vector((c_wishbone_address_width/8)-1 downto 0);
std_logic_vector((c_wishbone_data_width/8)-1 downto 0);
subtype t_wishbone_cycle_type is
std_logic_vector(2 downto 0);
subtype t_wishbone_burst_type is
......@@ -40,7 +40,6 @@ package wishbone_pkg is
err : std_logic;
rty : std_logic;
stall : std_logic;
int : std_logic;
dat : t_wishbone_data;
end record t_wishbone_slave_out;
subtype t_wishbone_master_in is t_wishbone_slave_out;
......@@ -58,14 +57,14 @@ package wishbone_pkg is
constant cc_dummy_address : std_logic_vector(c_wishbone_address_width-1 downto 0):=
(others => 'X');
constant cc_dummy_data : std_logic_vector(c_wishbone_address_width-1 downto 0) :=
constant cc_dummy_data : std_logic_vector(c_wishbone_data_width-1 downto 0) :=
(others => 'X');
constant cc_dummy_sel : std_logic_vector(c_wishbone_data_width/8-1 downto 0) :=
(others => 'X');
constant cc_dummy_slave_in : t_wishbone_slave_in :=
('X', 'X', cc_dummy_address, cc_dummy_sel, 'X', cc_dummy_data);
constant cc_dummy_slave_out : t_wishbone_slave_out :=
('X', 'X', 'X', 'X', 'X', cc_dummy_data);
('X', 'X', 'X', 'X', cc_dummy_data);
------------------------------------------------------------------------------
......
hdl/boards/svec/rtl/xwb_ram.vhd
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hdl/boards/svec/sim/testbench/VME64x_Package.vhd 0 → 100755
View file @ 6be70e8c
--------------------------------------------------------------------------------------
---------------------------VME64x_Package-----------------------------------------
--------------------------------------------------------------------------------------
-- Date : Fri Mar 03 2012
--
-- Author : Davide Pedretti
--
-- Company : CERN
--
-- Description : VME64x constants, records, type...
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.all;
use work.vme64x_pack.all;
package VME64x is
subtype Vme64xAddressType is std_logic_vector(31 downto 1); -- (31 downto 0)
subtype Vme64xDataType is std_logic_vector(31 downto 0);
subtype Vme64xAddressModType is std_logic_vector(5 downto 0);
type VME64xBusOut_Record is -- This is an output for the VME64x master
record
Vme64xAsN : std_logic;
Vme64xDs1N : std_logic;
Vme64xDs0N : std_logic;
Vme64xLWORDN : std_logic;
Vme64xIACK : std_logic;
Vme64xIACKIN : std_logic;
Vme64xWRITEN : std_logic;
Vme64xAM : Vme64xAddressModType;
Vme64xADDR : Vme64xAddressType;
Vme64xDATA : Vme64xDataType;
end record;
type VME64xBusIn_Record is -- This is an input for the VME64x master
record
Vme64xDtackN : std_logic;
Vme64xBerrN : std_logic;
Vme64xRetryN : std_logic;
Vme64xADDR : Vme64xAddressType;
Vme64xDATA : Vme64xDataType;
Vme64xLWORDN : std_logic;
Vme64xIACKOUT : std_logic;
Vme64xIRQ : std_logic_vector(6 downto 0);
end record;
-- Types
type t_Buffer_BLT is array (0 to 66) of std_logic_vector(31 downto 0); -- for BLT transfer
--The buffer has 65 positions, not 64; the last position is for test the error if i transfer more of 256 bytes.
type t_Buffer_MBLT is array (0 to 258) of std_logic_vector(63 downto 0); -- for MBLT transfer
--The buffer has 258 positions, not 256; the last position is for test the error if i transfer more of 256 bytes.
type t_dataTransferType is (D08Byte0, D08Byte1, D08Byte2, D08Byte3, D16Byte01, D16Byte23, D32); -- for D64 use dataTransferType D32!
type t_Addressing_Type is (A24, A24_BLT, A24_MBLT, A24_LCK, CR_CSR, A16, A16_LCK, A32, A32_BLT, A32_MBLT, A32_LCK,
A64, A64_BLT, A64_MBLT, A64_LCK, A32_2eVME, A64_2eVME, A32_2eSST, A64_2eSST, error);
-- Declare constants
-- constant <constant_name> : time := <time_unit> ns;
constant BA : std_logic_vector(7 downto 0) := "11110000";
constant VME_GA : std_logic_vector(5 downto 0) := "110111"; -- GA parity match '1' & slot number
constant ID_Master : std_logic_vector(7 downto 0) := "00001111"; -- max 31
constant ADER0_A16_S : std_logic_vector(31 downto 0) := "0000000000000000" & BA(7 downto 3) & "000" & c_A16 &"00";
constant ADER0_A24_S : std_logic_vector(31 downto 0) := "00000000" & BA(7 downto 3) & "00000000000" & c_A24_S &"00";
constant ADER0_A24_BLT : std_logic_vector(31 downto 0) := "00000000" & BA(7 downto 3) & "00000000000" & c_A24_BLT &"00";
constant ADER0_A24_MBLT : std_logic_vector(31 downto 0) := "00000000" & BA(7 downto 3) & "00000000000" & c_A24_MBLT &"00";
constant ADER0_A32 : std_logic_vector(31 downto 0) := BA(7 downto 3) & "0000000000000000000" & c_A32 &"00";
constant ADER0_A32_BLT : std_logic_vector(31 downto 0) := BA(7 downto 3) & "0000000000000000000" & c_A32_BLT &"00";
constant ADER0_A32_MBLT : std_logic_vector(31 downto 0) := BA(7 downto 3) & "0000000000000000000" & c_A32_MBLT &"00";
constant ADER1_A64 : std_logic_vector(31 downto 0) := "000000000000000000000000" & c_A64 &"00";
constant ADER1_A64_BLT : std_logic_vector(31 downto 0) := "000000000000000000000000" & c_A64_BLT &"00";
constant ADER1_A64_MBLT : std_logic_vector(31 downto 0) := "000000000000000000000000" & c_A64_MBLT &"00";
constant ADER1_A64_b : std_logic_vector(31 downto 0) := BA(7 downto 3) & "000000000000000000000000000";
constant ADER2_A32_2eVME : std_logic_vector(31 downto 0) := BA(7 downto 3) & "00000000000000000" & x"01" &"01";
constant ADER2_A64_2eVME : std_logic_vector(31 downto 0) := "0000000000000000000000" & x"02" &"01";
constant ADER2_A32_2eSST : std_logic_vector(31 downto 0) := "0000000000000000000000" & x"11" &"01";
constant ADER2_A64_2eSST : std_logic_vector(31 downto 0) := "0000000000000000000000" & x"12" &"01";
constant ADER2_2e_b : std_logic_vector(31 downto 0) := BA(7 downto 3) & "000000000000000000000000000";
-- CSR constants
constant c_BAR : std_logic_vector := x"7FFFF";
constant c_BIT_SET_REG : std_logic_vector := x"7FFFB";
constant c_BIT_CLR_REG : std_logic_vector := x"7FFF7";
constant c_CRAM_OWNER : std_logic_vector := x"7FFF3";
constant c_USR_BIT_SET_REG : std_logic_vector := x"7FFEF";
constant c_USR_BIT_CLR_REG : std_logic_vector := x"7FFEB";
constant c_FUNC7_ADER_0 : std_logic_vector := x"7FFDF";
constant c_FUNC7_ADER_1 : std_logic_vector := x"7FFDB";
constant c_FUNC7_ADER_2 : std_logic_vector := x"7FFD7";
constant c_FUNC7_ADER_3 : std_logic_vector := x"7FFD3";
constant c_FUNC6_ADER_0 : std_logic_vector := x"7FFCF";
constant c_FUNC6_ADER_1 : std_logic_vector := x"7FFCB";
constant c_FUNC6_ADER_2 : std_logic_vector := x"7FFC7";
constant c_FUNC6_ADER_3 : std_logic_vector := x"7FFC3";
constant c_FUNC5_ADER_0 : std_logic_vector := x"7FFBF";
constant c_FUNC5_ADER_1 : std_logic_vector := x"7FFBB";
constant c_FUNC5_ADER_2 : std_logic_vector := x"7FFB7";
constant c_FUNC5_ADER_3 : std_logic_vector := x"7FFB3";
constant c_FUNC4_ADER_0 : std_logic_vector := x"7FFAF";
constant c_FUNC4_ADER_1 : std_logic_vector := x"7FFAB";
constant c_FUNC4_ADER_2 : std_logic_vector := x"7FFA7";
constant c_FUNC4_ADER_3 : std_logic_vector := x"7FFA3";
constant c_FUNC3_ADER_0 : std_logic_vector := x"7FF9F";
constant c_FUNC3_ADER_1 : std_logic_vector := x"7FF9B";
constant c_FUNC3_ADER_2 : std_logic_vector := x"7FF97";
constant c_FUNC3_ADER_3 : std_logic_vector := x"7FF93";
constant c_FUNC2_ADER_0 : std_logic_vector := x"7FF8F";
constant c_FUNC2_ADER_1 : std_logic_vector := x"7FF8B";
constant c_FUNC2_ADER_2 : std_logic_vector := x"7FF87";
constant c_FUNC2_ADER_3 : std_logic_vector := x"7FF83";
constant c_FUNC1_ADER_0 : std_logic_vector := x"7FF7F";
constant c_FUNC1_ADER_1 : std_logic_vector := x"7FF7B";
constant c_FUNC1_ADER_2 : std_logic_vector := x"7FF77";
constant c_FUNC1_ADER_3 : std_logic_vector := x"7FF73";
constant c_FUNC0_ADER_0 : std_logic_vector := x"7FF6F";
constant c_FUNC0_ADER_1 : std_logic_vector := x"7FF6B";
constant c_FUNC0_ADER_2 : std_logic_vector := x"7FF67";
constant c_FUNC0_ADER_3 : std_logic_vector := x"7FF63";
constant c_BYTES0 : std_logic_vector := x"7FF3b";
constant c_MBLT_Endian : std_logic_vector := x"7Ff53";
constant c_IRQ_Vector : std_logic_vector := x"7FF5F";
constant c_IRQ_level : std_logic_vector := x"7FF5B";
constant c_WB32or64 : std_logic_vector := x"7FF33";
-- CR constant
constant c_StartDefinedCR : std_logic_vector := x"00000";
constant c_EndDefinedCR : std_logic_vector := x"00FFF";
end VME64x;
package body VME64x is
end VME64x;
hdl/boards/svec/sim/testbench/VME64x_SIM_Package.vhd 0 → 100755
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hdl/boards/svec/sim/testbench/VME64x_TB.vhd 0 → 100644
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hdl/boards/svec/sim/testbench/wave1.do 0 → 100644
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