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VME64x core
Commit 62b13b5e authored by Tom Levens's avatar Tom Levens
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Clean up CR/CSR space 

The CR/CSR space has been cleaned up and reworked. All decoding of the
addresses has been moved from VME_bus to VME_CR_CSR_Space to make the
code a bit more structured..

The option to have a user CR and CSR areas has been added. These are
external such that they can be implemented by the user.

The custom CSR registers (IRQ vector/level ...) have been moved to
VME_User_CSR.vhd. By default (in the xvme64x_core wrapper) this area is
mapped to 0x7FF33..7FF5F (in the reserved area) in order to maintain
compatibility with the previous version of the core. However, it can be
moved using generics to a non-reserved area for new applications. This
fixes Bug #1353.
Signed-off-by: Tom Levens's avatarTom Levens <tom.levens@cern.ch>
parent 781e4153
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hdl/vme64x-core/rtl/Manifest.py
View file @ 62b13b5e
......@@ -6,6 +6,7 @@ files = [ "xvme64x_core.vhd",
"VME_Am_Match.vhd",
"VME_bus.vhd",
"VME_CR_CSR_Space.vhd",
"VME_User_CSR.vhd",
"VME_CRAM.vhd",
"VME_Funct_Match.vhd",
"VME_IRQ_Controller.vhd",
......
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @ 62b13b5e
......@@ -143,8 +143,8 @@ entity VME64xCore_Top is
g_beg_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_end_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_beg_cram : std_logic_vector(23 downto 0) := x"001000";
g_end_cram : std_logic_vector(23 downto 0) := x"0013ff";
g_beg_cram : std_logic_vector(23 downto 0) := x"000000";
g_end_cram : std_logic_vector(23 downto 0) := x"000000";
g_beg_user_csr : std_logic_vector(23 downto 0) := x"000000";
g_end_user_csr : std_logic_vector(23 downto 0) := x"000000";
......@@ -250,31 +250,39 @@ entity VME64xCore_Top is
WE_o : out std_logic;
STALL_i : in std_logic;
-- For the swapper
endian_i : in std_logic_vector(2 downto 0);
-- User CR/CSR
user_csr_addr_o : out std_logic_vector(18 downto 2);
user_csr_data_i : in std_logic_vector( 7 downto 0);
user_csr_data_o : out std_logic_vector( 7 downto 0);
user_csr_we_o : out std_logic;
user_cr_addr_o : out std_logic_vector(18 downto 2);
user_cr_data_i : in std_logic_vector( 7 downto 0);
-- IRQ Generator
INT_ack_o : out std_logic; -- when the IRQ controller acknowledges the
irq_ack_o : out std_logic; -- when the IRQ controller acknowledges the
-- Interrupt cycle it sends a pulse to the
-- IRQ Generator
IRQ_i : in std_logic -- Interrupt request; the IRQ Generator/your
irq_i : in std_logic; -- Interrupt request; the IRQ Generator/your
-- Wb application sends a pulse to the IRQ
-- Controller which asserts one of the IRQ
-- lines.
);
irq_level_i : in std_logic_vector(7 downto 0);
irq_vector_i : in std_logic_vector(7 downto 0)
);
end VME64xCore_Top;
architecture RTL of VME64xCore_Top is
signal s_CRAMdataOut : std_logic_vector(7 downto 0);
signal s_CRAMaddr : std_logic_vector(f_log2_size(f_size(g_beg_cram, g_end_cram))-1 downto 0);
signal s_CRAMdataIn : std_logic_vector(7 downto 0);
signal s_CRAMwea : std_logic;
signal s_CRaddr : std_logic_vector(11 downto 0);
signal s_CRdata : std_logic_vector(7 downto 0);
signal s_RW : std_logic;
signal s_reset : std_logic;
signal s_IRQlevelReg : std_logic_vector(7 downto 0);
signal s_FIFOreset : std_logic;
signal s_reset_n : std_logic;
signal s_VME_DATA_IRQ : std_logic_vector(31 downto 0);
signal s_VME_DATA_VMEbus : std_logic_vector(31 downto 0);
-- signal s_VME_DATA_b : std_logic_vector(31 downto 0);
......@@ -285,28 +293,25 @@ architecture RTL of VME64xCore_Top is
signal s_VME_DTACK_OE_IRQ : std_logic;
signal s_VME_DATA_DIR_VMEbus : std_logic;
signal s_VME_DATA_DIR_IRQ : std_logic;
signal s_INT_Level : std_logic_vector(7 downto 0);
signal s_INT_Vector : std_logic_vector(7 downto 0);
signal s_VME_IRQ_n_o : std_logic_vector(6 downto 0);
signal s_reset_IRQ : std_logic;
signal s_CSRData_o : std_logic_vector(7 downto 0);
signal s_CSRData_i : std_logic_vector(7 downto 0);
signal s_CrCsrOffsetAddr : std_logic_vector(18 downto 0);
signal s_Ader0 : std_logic_vector(31 downto 0);
signal s_Ader1 : std_logic_vector(31 downto 0);
signal s_Ader2 : std_logic_vector(31 downto 0);
signal s_Ader3 : std_logic_vector(31 downto 0);
signal s_Ader4 : std_logic_vector(31 downto 0);
signal s_Ader5 : std_logic_vector(31 downto 0);
signal s_Ader6 : std_logic_vector(31 downto 0);
signal s_Ader7 : std_logic_vector(31 downto 0);
signal s_en_wr_CSR : std_logic;
signal s_err_flag : std_logic;
signal s_reset_flag : std_logic;
signal s_Sw_Reset : std_logic;
signal s_ModuleEnable : std_logic;
signal s_Endian : std_logic_vector(2 downto 0);
signal s_BAR : std_logic_vector(4 downto 0);
-- CR/CSR
signal s_cr_csr_addr : std_logic_vector(18 downto 2);
signal s_cr_csr_data_o : std_logic_vector( 7 downto 0);
signal s_cr_csr_data_i : std_logic_vector( 7 downto 0);
signal s_cr_csr_we : std_logic;
signal s_ader0 : std_logic_vector(31 downto 0);
signal s_ader1 : std_logic_vector(31 downto 0);
signal s_ader2 : std_logic_vector(31 downto 0);
signal s_ader3 : std_logic_vector(31 downto 0);
signal s_ader4 : std_logic_vector(31 downto 0);
signal s_ader5 : std_logic_vector(31 downto 0);
signal s_ader6 : std_logic_vector(31 downto 0);
signal s_ader7 : std_logic_vector(31 downto 0);
signal s_module_reset : std_logic;
signal s_module_enable : std_logic;
signal s_bar : std_logic_vector(4 downto 0);
signal s_vme_berr_n : std_logic;
-- Oversampled input signals
signal s_VME_RST_n : std_logic_vector(2 downto 0);
......@@ -393,7 +398,7 @@ begin
VME_DS_ant_n_i => s_VME_DS_n(3 downto 2),
VME_DTACK_n_o => s_VME_DTACK_VMEbus,
VME_DTACK_OE_o => s_VME_DTACK_OE_VMEbus,
VME_BERR_o => VME_BERR_o,
VME_BERR_n_o => s_vme_berr_n,
VME_ADDR_i => VME_ADDR_i,
VME_ADDR_o => VME_ADDR_o,
VME_ADDR_DIR_o => VME_ADDR_DIR_o,
......@@ -405,52 +410,48 @@ begin
VME_AM_i => VME_AM_i,
VME_IACK_n_i => s_VME_IACK_n(2),
-- WB
memReq_o => STB_o,
memAckWB_i => ACK_i,
wbData_o => DAT_o,
wbData_i => DAT_i,
locAddr_o => ADR_o,
wbSel_o => SEL_o,
RW_o => s_RW,
-- WB signals
stb_o => STB_o,
ack_i => ACK_i,
dat_o => DAT_o,
dat_i => DAT_i,
adr_o => ADR_o,
sel_o => SEL_o,
we_o => WE_o,
cyc_o => CYC_o,
err_i => ERR_i,
rty_i => RTY_i,
stall_i => STALL_i,
-- CR/CSR signals
CRAMaddr_o => s_CRAMaddr,
CRAMdata_o => s_CRAMdataIn,
CRAMdata_i => s_CRAMdataOut,
CRAMwea_o => s_CRAMwea,
CRaddr_o => s_CRaddr,
CRdata_i => s_CRdata,
en_wr_CSR => s_en_wr_CSR,
CrCsrOffsetAddr => s_CrCsrOffsetAddr,
CSRData_o => s_CSRData_o,
CSRData_i => s_CSRData_i,
err_flag_o => s_err_flag,
reset_flag_i => s_reset_flag,
Ader0 => s_Ader0,
Ader1 => s_Ader1,
Ader2 => s_Ader2,
Ader3 => s_Ader3,
Ader4 => s_Ader4,
Ader5 => s_Ader5,
Ader6 => s_Ader6,
Ader7 => s_Ader7,
ModuleEnable => s_ModuleEnable,
Endian_i => s_Endian,
Sw_Reset => s_Sw_Reset,
BAR_i => s_BAR
cr_csr_addr_o => s_cr_csr_addr,
cr_csr_data_i => s_cr_csr_data_o,
cr_csr_data_o => s_cr_csr_data_i,
cr_csr_we_o => s_cr_csr_we,
ader0_i => s_ader0,
ader1_i => s_ader1,
ader2_i => s_ader2,
ader3_i => s_ader3,
ader4_i => s_ader4,
ader5_i => s_ader5,
ader6_i => s_ader6,
ader7_i => s_ader7,
endian_i => endian_i,
module_enable_i => s_module_enable,
module_reset_i => s_module_reset,
bar_i => s_bar
);
s_reset_n <= not s_reset;
VME_BERR_o <= not s_vme_berr_n; -- The VME_BERR is asserted when '1' because
-- the buffers on the board invert the logic.
------------------------------------------------------------------------------
-- Output
------------------------------------------------------------------------------
VME_IRQ_o <= not s_VME_IRQ_n_o; -- The buffers will invert again the logic level
WE_o <= not s_RW;
INT_ack_o <= s_VME_DTACK_IRQ;
irq_ack_o <= s_VME_DTACK_IRQ;
-- Multiplexer added on the output signal used by either VMEbus.vhd and the
-- IRQ_controller.vhd
......@@ -479,13 +480,13 @@ begin
)
port map (
clk_i => clk_i,
reset_n_i => s_reset_IRQ, -- asserted when low
reset_n_i => s_reset_n, -- asserted when low
VME_IACKIN_n_i => s_VME_IACKIN_n(2),
VME_AS_n_i => s_VME_AS_n(2),
VME_DS_n_i => s_VME_DS_n(5 downto 4),
VME_ADDR_123_i => VME_ADDR_i(3 downto 1),
INT_Level_i => s_INT_Level,
INT_Vector_i => s_INT_Vector,
INT_Level_i => irq_level_i,
INT_Vector_i => irq_vector_i,
INT_Req_i => irq_i,
VME_IRQ_n_o => s_VME_IRQ_n_o,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
......@@ -495,16 +496,18 @@ begin
VME_DATA_DIR_o => s_VME_DATA_DIR_IRQ
);
s_reset_IRQ <= not(s_reset);
------------------------------------------------------------------------------
-- CR/CSR space
------------------------------------------------------------------------------
Inst_VME_CR_CSR_Space : VME_CR_CSR_Space
generic map (
g_cram_size => f_size(g_beg_cram, g_end_cram),
g_wb_data_width => g_wb_data_width,
g_cr_space => f_vme_cr_encode(
g_beg_user_cr => g_beg_user_cr,
g_end_user_cr => g_end_user_cr,
g_beg_cram => g_beg_cram,
g_end_cram => g_end_cram,
g_beg_user_csr => g_beg_user_csr,
g_end_user_csr => g_end_user_csr,
g_cr_space => f_vme_cr_encode(
g_manufacturer_id, g_board_id, g_revision_id, g_program_id,
g_ascii_ptr,
g_beg_user_cr, g_end_user_cr,
......@@ -522,37 +525,38 @@ begin
)
)
port map (
clk_i => clk_i,
reset => s_reset,
CR_addr => s_CRaddr,
CR_data => s_CRdata,
CRAM_addr => s_CRAMaddr,
CRAM_data_o => s_CRAMdataOut,
CRAM_data_i => s_CRAMdataIn,
CRAM_Wen => s_CRAMwea,
en_wr_CSR => s_en_wr_CSR,
CrCsrOffsetAddr => s_CrCsrOffsetAddr,
VME_GA_oversampled => VME_GA_i,
locDataIn => s_CSRData_o,
err_flag => s_err_flag,
reset_flag => s_reset_flag,
CSRdata => s_CSRData_i,
Ader0 => s_Ader0,
Ader1 => s_Ader1,
Ader2 => s_Ader2,
Ader3 => s_Ader3,
Ader4 => s_Ader4,
Ader5 => s_Ader5,
Ader6 => s_Ader6,
Ader7 => s_Ader7,
ModuleEnable => s_ModuleEnable,
Sw_Reset => s_Sw_Reset,
Endian_o => s_Endian,
BAR_o => s_BAR,
INT_Level => s_INT_Level,
numBytes => (others => '0'),
transfTime => (others => '0'),
INT_Vector => s_INT_Vector
clk_i => clk_i,
reset_i => s_reset,
vme_ga_i => VME_GA_i,
vme_berr_n_i => s_vme_berr_n,
bar_o => s_bar,
vme_sysfail_i => '0',
vme_sysfail_ena_o => open,
module_enable_o => s_module_enable,
module_reset_o => s_module_reset,
addr_i => s_cr_csr_addr,
data_i => s_cr_csr_data_i,
data_o => s_cr_csr_data_o,
we_i => s_cr_csr_we,
user_csr_addr_o => user_csr_addr_o,
user_csr_data_i => user_csr_data_i,
user_csr_data_o => user_csr_data_o,
user_csr_we_o => user_csr_we_o,
user_cr_addr_o => user_cr_addr_o,
user_cr_data_i => user_cr_data_i,
ader0_o => s_ader0,
ader1_o => s_ader1,
ader2_o => s_ader2,
ader3_o => s_ader3,
ader4_o => s_ader4,
ader5_o => s_ader5,
ader6_o => s_ader6,
ader7_o => s_ader7
);
end RTL;
hdl/vme64x-core/rtl/VME_CRAM.vhd
View file @ 62b13b5e
......@@ -9,7 +9,7 @@
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch>
--
-- description: RAM memory
-- description: CRAM memory
--
-- dependencies:
--
......@@ -38,32 +38,40 @@ use work.vme64x_pack.all;
entity VME_CRAM is
generic (
dl : integer;
al : integer
g_beg_cram : std_logic_vector(23 downto 0);
g_end_cram : std_logic_vector(23 downto 0)
);
port (
clk : in std_logic;
we : in std_logic;
aw : in std_logic_vector(al-1 downto 0);
di : in std_logic_vector(dl-1 downto 0);
dw : out std_logic_vector(dl-1 downto 0)
clk_i : in std_logic;
we_i : in std_logic;
addr_i : in std_logic_vector(18 downto 2);
data_i : in std_logic_vector( 7 downto 0);
data_o : out std_logic_vector( 7 downto 0)
);
end VME_CRAM;
architecture syn of VME_CRAM is
architecture rtl of VME_CRAM is
type ram_type is array (2**al-1 downto 0) of std_logic_vector (dl-1 downto 0);
signal CRAM : ram_type;
type t_cram is array (f_size(g_beg_cram, g_end_cram)-1 downto 0)
of std_logic_vector(7 downto 0);
signal s_cram : t_cram;
signal s_addr : unsigned(18 downto 2);
signal s_addr_1 : unsigned(18 downto 2);
begin
process (clk) begin
if rising_edge(clk) then
if (we = '1') then
CRAM(to_integer(unsigned(aw))) <= di;
s_addr <= unsigned(addr_i(18 downto 2));
process (clk_i) begin
if rising_edge(clk_i) then
if we_i = '1' then
s_cram(to_integer(s_addr)) <= data_i;
end if;
dw <= CRAM(to_integer(unsigned(aw)));
s_addr_1 <= s_addr;
end if;
end process;
end syn;
data_o <= s_cram(to_integer(s_addr_1));
end rtl;
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
View file @ 62b13b5e
......@@ -11,105 +11,76 @@
--
-- description:
--
-- Please note that only every fourth location in the CR/CSR space is used so
-- it is possible write the CSR/CRAM selecting the data transfer mode
-- D08_Byte3, D16_Byte23, D32. If other data transfer modes are selected the
-- write operation will not be successful. If the Master access the board for
-- a reading operation with data transfer type different than D08_Byte3,
-- D16_Byte23, D32 the data that will be read is 0.
-- Implementation of CR/CSR space.
--
-- width = 1 byte
-- width = 1 byte
-- /---------------------------------/
-- _________________________________
-- | |0x7ffff
-- | |
-- | | 0x7ffff
-- | Defined and Reserved CSR |
-- | |
-- | Table 10-13 "Defined Control |
-- | Status register Assignments" |
-- | ANSI/VITA 1.1-1997 |
-- | VME64 Extensions |
-- |_________________________________|0x7fc00
-- | |0x013ff
-- | |
-- | |
-- |_________________________________| 0x7fc00
-- |_________________________________|
-- | | 0xXXXXX
-- | User CSR |
-- |_________________________________| 0xXXXXX
-- |_________________________________|
-- | | 0xXXXXX
-- | CRAM |
-- | |
-- | |
-- | |
-- | |
-- |_________________________________|0x01000
-- | |0x00fff
-- | |
-- |_________________________________| 0xXXXXX
-- |_________________________________|
-- | | 0xXXXXX
-- | User CR |
-- |_________________________________| 0xXXXXX
-- |_________________________________|
-- | | 0x00fff
-- | Defined and reserved CR |
-- | |
-- | Table 10-12 "Defined |
-- | Configuration ROM Assignments" |
-- | ANSI/VITA 1.1-1997 |
-- | VME64 Extensions |
-- | |
-- |_________________________________|0x00000
--
-- If the size of the register is bigger than 1 byte, (eg: ADER is 4 bytes)
-- these bytes are stored in the BIG_ENDIAN ORDER.
-- User CR and User CSR are not implemented.
--
-- In addition to the registers of the table 10-13 in the CSR space you can
-- find:
-- _
-- IRQ_Vector --> 0x7FF5F |--> for the Interrupter
-- IRQ_level --> 0x7FF5B _|
--
-- Endian --> 0x7FF53 --> for the swapper
-- |_________________________________| 0x00000
--
-- WB32bits --> 0x7FF33 --> if the bit 0 is '1' it means that the WB
-- data bus is 32 bit
-- _
-- TIME0_ns --> 0x7FF4f |
-- TIME1_ns --> 0x7FF4b |
-- TIME2_ns --> 0x7FF47 |
-- TIME3_ns --> 0x7FF43 |--> to calculate the transfer rate
-- TIME4_ns --> 0x7FF3f |
-- BYTES0 --> 0x7FF3b |
-- BYTES1 --> 0x7FF37 _|
-- Please note that only every fourth location in the CR/CSR space is used,
-- so it is possible read and write the CR/CSR by selecting the data transfer
-- mode D08 (byte 3), D16 (bytes 2 & 3) or D32. If other data transfer modes
-- are used the operation will not be successful.
--
-- CRAM memory Added. How to use the CRAM: (1KB)
-- If the size of the register is bigger than 1 byte, (e.g. ADER is 4 bytes)
-- these bytes are stored in BIG ENDIAN order.
--
-- 1) The Master read the CRAM_OWNER Register location 0x7fff3; if 0 the
-- CRAM is free
-- 2) The Master write his ID in the CRAM_OWNER Register location 0x7fff3
-- 3) If the Master can read his ID in the CRAM_OWNER Register it means that it
-- is the owner of the CRAM.
-- If other Masters write their ID in the CRAM_OWNER Register when it
-- contains a non-zero value, the write operation will not be successful
-- --> this allows the first Master that writes a non-zero value to
-- acquire ownership.
-- 4) When a Master has the ownership of the CRAM the Bit Set Register's
-- bit 2, location 0x7fffb, should be setted.
-- 5) The Master can release the ownership by writing '1' in the bit 2 to
-- the Bit Set Register location 0x7fffb.
-- How to use the CRAM:
--
-- Other flags:
-- 1) The Master first reads the CRAM_OWNER register (location 0x7fff3).
-- If it is zero the CRAM is available.
-- 2) The Master writes his ID to the CRAM_OWNER register.
-- 3) If the Master can readback his ID from the CRAM_OWNER register it
-- means that he is the owner of the CRAM and has exclusive access.
-- 4) If other Masters write their ID to the CRAM_OWNER register when it
-- contains a non-zero value, the write operation will not be successful.
-- This allows the first Master that writes a non-zero value to acquire
-- ownership.
-- 5) When a Master has ownership of the CRAM, bit 2 of the Bit Set Register
-- (location 0x7fffb) will be set.
-- 6) The Master can release the ownership by writing '1' to bit 2 of the
-- Bit Clr Register (location 0x7fff7).
--
-- Module Enable --> Bit Set Register's bit 4 location 0x7fffb
-- If this bit is '0' the slave module's address decoder
-- is not enable and the Wb bus can't be accessed.
-- Error flag --> Bit Set Register's bit 3 location 0x7fffb
-- When the Slave asserts the BERR* line should asserts
-- also this bit.
-- CRAM_OWNER flag --> Bit Set Register's bit 2 location 0x7fffb
-- Bit Set Register control bits (location 0x7fffb):
--
-- The Master can clear these flags by writing '1' in the corresponding bits
-- to the Bit Clr Register location 0x7fff7.
-- 7: RESET -----------> When high the module is held in reset.
-- 6: SYSFAIL ENABLE --> When high the VME_SYSFAIL output driver is enabled.
-- 5: FAILED ----------> When high the module has failed.
-- 4: ENABLE ----------> When high the WB accesses are enabled.
-- 3: BERR ------------> When high the module has asserted BERR.
-- 2: CRAM OWNER ------> When high the CRAM is owned.
--
-- Software reset --> Bit Set Register's bit 7 location 0x7fffb
-- This bit acts as software reset, indeed if the Master
-- writes '1' here, the module will be resetted and
-- reinitializated. The reset condition is temporary
-- because during the initialization the default
-- configuration is uploaded again, so the Master don't
-- need to remove the module from reset mode by writing
-- '1' in the bit 7 to the Bit Clr Register.
-- The Master can clear these bits by writing '1' in the corresponding bits
-- to the Bit Clr Register (location 0x7fff7).
--
-- dependencies:
--
......@@ -134,283 +105,371 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vme64x_pack.all;
entity VME_CR_CSR_Space is
generic (
g_cram_size : integer;
g_wb_data_width : integer;
g_cr_space : t_cr_array
g_beg_user_cr : std_logic_vector(23 downto 0);
g_end_user_cr : std_logic_vector(23 downto 0);
g_beg_cram : std_logic_vector(23 downto 0);
g_end_cram : std_logic_vector(23 downto 0);
g_beg_user_csr : std_logic_vector(23 downto 0);
g_end_user_csr : std_logic_vector(23 downto 0);
g_cr_space : t_cr_array
);
port (
-- VMEbus.vhd signals
clk_i : in std_logic;
reset : in std_logic;
CR_addr : in std_logic_vector (11 downto 0);
CR_data : out std_logic_vector (7 downto 0);
CRAM_addr : in std_logic_vector (f_log2_size(g_cram_size)-1 downto 0);
CRAM_data_o : out std_logic_vector (7 downto 0);
CRAM_data_i : in std_logic_vector (7 downto 0);
CRAM_Wen : in std_logic;
en_wr_CSR : in std_logic;
CrCsrOffsetAddr : in std_logic_vector (18 downto 0);
VME_GA_oversampled : in std_logic_vector (5 downto 0);
locDataIn : in std_logic_vector (7 downto 0);
err_flag : in std_logic;
reset_flag : out std_logic;
CSRdata : out std_logic_vector(7 downto 0);
numBytes : in std_logic_vector(12 downto 0);
transfTime : in std_logic_vector(39 downto 0);
-- VMEbus.vhd DECODER signals
Ader0 : out std_logic_vector(31 downto 0);
Ader1 : out std_logic_vector(31 downto 0);
Ader2 : out std_logic_vector(31 downto 0);
Ader3 : out std_logic_vector(31 downto 0);
Ader4 : out std_logic_vector(31 downto 0);
Ader5 : out std_logic_vector(31 downto 0);
Ader6 : out std_logic_vector(31 downto 0);
Ader7 : out std_logic_vector(31 downto 0);
ModuleEnable : out std_logic;
Sw_Reset : out std_logic;
Endian_o : out std_logic_vector(2 downto 0);
BAR_o : out std_logic_vector(4 downto 0);
-- IRQ_controller signals
INT_Level : out std_logic_vector(7 downto 0);
INT_Vector : out std_logic_vector(7 downto 0)
reset_i : in std_logic;
vme_ga_i : in std_logic_vector(5 downto 0);
vme_berr_n_i : in std_logic;
bar_o : out std_logic_vector(4 downto 0);
vme_sysfail_i : in std_logic;
vme_sysfail_ena_o : out std_logic;
module_enable_o : out std_logic;
module_reset_o : out std_logic;
addr_i : in std_logic_vector(18 downto 2);
data_i : in std_logic_vector( 7 downto 0);
data_o : out std_logic_vector( 7 downto 0);
we_i : in std_logic;
user_csr_addr_o : out std_logic_vector(18 downto 2);
user_csr_data_i : in std_logic_vector( 7 downto 0);
user_csr_data_o : out std_logic_vector( 7 downto 0);
user_csr_we_o : out std_logic;
user_cr_addr_o : out std_logic_vector(18 downto 2);
user_cr_data_i : in std_logic_vector( 7 downto 0);
ader0_o : out std_logic_vector(31 downto 0);
ader1_o : out std_logic_vector(31 downto 0);
ader2_o : out std_logic_vector(31 downto 0);
ader3_o : out std_logic_vector(31 downto 0);
ader4_o : out std_logic_vector(31 downto 0);
ader5_o : out std_logic_vector(31 downto 0);
ader6_o : out std_logic_vector(31 downto 0);
ader7_o : out std_logic_vector(31 downto 0)
);
end VME_CR_CSR_Space;
architecture Behavioral of VME_CR_CSR_Space is
architecture rtl of VME_CR_CSR_Space is
signal s_addr : unsigned(18 downto 2);
signal s_ga_parity : std_logic;
signal s_cr_access : std_logic;
signal s_csr_access : std_logic;
signal s_cram_access : std_logic;
signal s_user_cr_access : std_logic;
signal s_user_csr_access : std_logic;
signal s_cr_data : std_logic_vector(7 downto 0);
signal s_csr_data : std_logic_vector(7 downto 0);
signal s_cram_data : std_logic_vector(7 downto 0);
signal s_CSRarray : t_csr_array; -- Array of CSR registers
signal s_bar_written : std_logic;
signal s_CSRdata : unsigned(7 downto 0);
signal s_FUNC_ADER : t_FUNC_32b_array;
signal s_CrCsrOffsetAddr : unsigned(18 downto 0);
signal s_locDataIn : unsigned(7 downto 0);
signal s_CrCsrOffsetAderIndex : unsigned(18 downto 0);
signal s_odd_parity : std_logic;
--signal s_BARerror : std_logic;
signal s_BAR_o : std_logic_vector(4 downto 0);
signal s_cram_addr : std_logic_vector(18 downto 2);
signal s_cram_we : std_logic;
signal s_reg_bar : std_logic_vector(7 downto 0);
signal s_reg_bit_reg : std_logic_vector(7 downto 0);
signal s_reg_cram_owner : std_logic_vector(7 downto 0);
signal s_reg_usr_bit_reg : std_logic_vector(7 downto 0);
signal s_reg_ader0 : std_logic_vector(31 downto 0);
signal s_reg_ader1 : std_logic_vector(31 downto 0);
signal s_reg_ader2 : std_logic_vector(31 downto 0);
signal s_reg_ader3 : std_logic_vector(31 downto 0);
signal s_reg_ader4 : std_logic_vector(31 downto 0);
signal s_reg_ader5 : std_logic_vector(31 downto 0);
signal s_reg_ader6 : std_logic_vector(31 downto 0);
signal s_reg_ader7 : std_logic_vector(31 downto 0);
signal s_cr_rom : t_cr_array(g_cr_space'range) := g_cr_space;
begin
-- check the parity:
s_odd_parity <= VME_GA_oversampled(5) xor VME_GA_oversampled(4) xor
VME_GA_oversampled(3) xor VME_GA_oversampled(2) xor
VME_GA_oversampled(1) xor VME_GA_oversampled(0);
-- If the crate is not driving the GA lines or the parity is even the BAR
-- register is set to 0x00 and the following flag is asserted; the board will
-- not answer if the master accesses its CR/CSR space and we can see a time
-- out error in the VME bus.
--s_BARerror <= not(s_BAR_o(4) or s_BAR_o(3)or s_BAR_o(2) or s_BAR_o(1) or s_BAR_o(0));
s_addr <= unsigned(addr_i);
-- CR
process(clk_i)
------------------------------------------------------------------------------
-- Defined CR
------------------------------------------------------------------------------
s_cr_access <= '1' when s_addr >= c_beg_cr(18 downto 2) and
s_addr <= c_end_cr(18 downto 2)
else '0';
process (clk_i)
begin
if rising_edge(clk_i) then
CR_data <= g_cr_space(to_integer(unsigned(CR_addr)));
s_cr_data <= s_cr_rom(to_integer(s_addr));
end if;
end process;
-- CSR Write
s_locDataIn <= unsigned(locDataIn);
------------------------------------------------------------------------------
-- Defined CSR
------------------------------------------------------------------------------
s_csr_access <= '1' when s_addr >= c_beg_csr(18 downto 2) and
s_addr <= c_end_csr(18 downto 2)
else '0';
s_CrCsrOffsetAderIndex <= s_CrCsrOffsetAddr -
(c_FUNC0_ADER_3_addr(18 downto 0) srl 2) +
FUNC0_ADER_3;
-- If the crate is not driving the GA lines or the parity is even the BAR
-- register is set to 0x00 and the board will not answer CR/CSR accesses.
s_ga_parity <= vme_ga_i(5) xor vme_ga_i(4) xor vme_ga_i(3) xor
vme_ga_i(2) xor vme_ga_i(1) xor vme_ga_i(0);
p_CSR_Write : process(clk_i)
-- Write
process (clk_i)
begin
if rising_edge(clk_i) then
if reset = '1' then
s_CSRarray(BAR) <= (others => '0');
s_bar_written <= '0';
for i in BAR-1 downto WB32bits loop -- Initialization of the CSR memory
s_CSRarray(i) <= x"00";
end loop;
elsif s_bar_written = '0' and s_odd_parity = '1' then
-- initialization of BAR reg to access the CR/CSR space
s_CSRarray(BAR)(7 downto 3) <= unsigned(not VME_GA_oversampled(4 downto 0));
s_CSRarray(BAR)(2 downto 0) <= "000";
s_bar_written <= '1';
elsif s_odd_parity = '0' then
s_CSRarray(BAR) <= (others => '0');
elsif (en_wr_CSR = '1') then
case to_integer(s_CrCsrOffsetAddr) is
when to_integer("00" & c_BAR_addr(18 downto 2)) =>
s_CSRarray(BAR) <= s_locDataIn(7 downto 0);
s_bar_written <= '1';
when to_integer("00" & c_BIT_SET_REG_addr(18 downto 2)) =>
for i in 0 to 7 loop
s_CSRarray(BIT_SET_CLR_REG)(i) <= s_locDataIn(i);
end loop;
when to_integer("00" & c_BIT_CLR_REG_addr(18 downto 2)) =>
for i in 0 to 7 loop
if s_locDataIn(i) = '1' and i = 2 then
s_CSRarray(BIT_SET_CLR_REG)(i) <= '0';
s_CSRarray(CRAM_OWNER) <= x"00";
elsif s_locDataIn(i) = '1' and i = 3 then
reset_flag <= '1';
else
if s_locDataIn(i) = '1' then
s_CSRarray(BIT_SET_CLR_REG)(i) <= '0';
end if;
if reset_i = '1' then
if s_ga_parity = '1' then
s_reg_bar <= (not vme_ga_i(4 downto 0)) & "000";
else
s_reg_bar <= x"00";
end if;
s_reg_bit_reg <= x"00";
s_reg_cram_owner <= x"00";
s_reg_usr_bit_reg <= x"00";
s_reg_ader0 <= x"00000000";
s_reg_ader1 <= x"00000000";
s_reg_ader2 <= x"00000000";
s_reg_ader3 <= x"00000000";
s_reg_ader4 <= x"00000000";
s_reg_ader5 <= x"00000000";
s_reg_ader6 <= x"00000000";
s_reg_ader7 <= x"00000000";
else
if we_i = '1' and s_csr_access = '1' then
case s_addr is
when c_addr_bar(18 downto 2) =>
s_reg_bar <= data_i;
when c_addr_bit_set_reg(18 downto 2) =>
for i in 0 to 7 loop
s_reg_bit_reg(i) <= s_reg_bit_reg(i) or data_i(i);
end loop;
when c_addr_bit_clr_reg(18 downto 2) =>
for i in 0 to 7 loop
s_reg_bit_reg(i) <= s_reg_bit_reg(i) and (not data_i(i));
end loop;
if data_i(2) = '1' then
s_reg_cram_owner <= x"00";
end if;
end loop;
when to_integer("00" & c_CRAM_OWNER_addr(18 downto 2)) =>
if s_CSRarray(CRAM_OWNER) = x"00" and s_locDataIn(7 downto 0) /= x"00" then
-- Write register give ownership only if register value is 0
s_CSRarray(CRAM_OWNER) <= s_locDataIn(7 downto 0);
s_CSRarray(BIT_SET_CLR_REG)(2) <= '1';
end if;
when to_integer("00" & c_USR_BIT_SET_REG_addr(18 downto 2)) =>
s_CSRarray(USR_BIT_SET_CLR_REG) <= s_locDataIn(7 downto 0);
when to_integer("00" & c_USR_BIT_CLR_REG_addr(18 downto 2)) =>
for i in 0 to 7 loop
if s_locDataIn(i) = '1' then
s_CSRarray(USR_BIT_SET_CLR_REG)(i) <= '0';
when c_addr_cram_owner(18 downto 2) =>
if s_reg_cram_owner = x"00" then
s_reg_cram_owner <= data_i;
s_reg_bit_reg(2) <= '1';
end if;
end loop;
when to_integer("00" & c_FUNC0_ADER_3_addr(18 downto 2)) to
to_integer("00" & c_FUNC7_ADER_0_addr(18 downto 2)) =>
s_CSRarray(to_integer(s_CrCsrOffsetAderIndex)) <= s_locDataIn(7 downto 0);
when c_addr_usr_set_reg(18 downto 2) =>
for i in 0 to 7 loop
s_reg_usr_bit_reg(i) <= s_reg_usr_bit_reg(i) or data_i(i);
end loop;
when to_integer("00" & c_IRQ_Vector_addr(18 downto 2)) =>
s_CSRarray(IRQ_Vector) <= s_locDataIn(7 downto 0);
when c_addr_usr_clr_reg(18 downto 2) =>
for i in 0 to 7 loop
s_reg_usr_bit_reg(i) <= s_reg_usr_bit_reg(i) and (not data_i(i));
end loop;
when to_integer("00" & c_IRQ_level_addr(18 downto 2)) =>
s_CSRarray(IRQ_level) <= s_locDataIn(7 downto 0);
when c_addr_func7_ader_0(18 downto 2) => s_reg_ader7( 7 downto 0) <= data_i;
when c_addr_func7_ader_1(18 downto 2) => s_reg_ader7(15 downto 8) <= data_i;
when c_addr_func7_ader_2(18 downto 2) => s_reg_ader7(23 downto 16) <= data_i;
when c_addr_func7_ader_3(18 downto 2) => s_reg_ader7(31 downto 24) <= data_i;
when c_addr_func6_ader_0(18 downto 2) => s_reg_ader6( 7 downto 0) <= data_i;
when c_addr_func6_ader_1(18 downto 2) => s_reg_ader6(15 downto 8) <= data_i;
when c_addr_func6_ader_2(18 downto 2) => s_reg_ader6(23 downto 16) <= data_i;
when c_addr_func6_ader_3(18 downto 2) => s_reg_ader6(31 downto 24) <= data_i;
when c_addr_func5_ader_0(18 downto 2) => s_reg_ader5( 7 downto 0) <= data_i;
when c_addr_func5_ader_1(18 downto 2) => s_reg_ader5(15 downto 8) <= data_i;
when c_addr_func5_ader_2(18 downto 2) => s_reg_ader5(23 downto 16) <= data_i;
when c_addr_func5_ader_3(18 downto 2) => s_reg_ader5(31 downto 24) <= data_i;
when c_addr_func4_ader_0(18 downto 2) => s_reg_ader4( 7 downto 0) <= data_i;
when c_addr_func4_ader_1(18 downto 2) => s_reg_ader4(15 downto 8) <= data_i;
when c_addr_func4_ader_2(18 downto 2) => s_reg_ader4(23 downto 16) <= data_i;
when c_addr_func4_ader_3(18 downto 2) => s_reg_ader4(31 downto 24) <= data_i;
when c_addr_func3_ader_0(18 downto 2) => s_reg_ader3( 7 downto 0) <= data_i;
when c_addr_func3_ader_1(18 downto 2) => s_reg_ader3(15 downto 8) <= data_i;
when c_addr_func3_ader_2(18 downto 2) => s_reg_ader3(23 downto 16) <= data_i;
when c_addr_func3_ader_3(18 downto 2) => s_reg_ader3(31 downto 24) <= data_i;
when c_addr_func2_ader_0(18 downto 2) => s_reg_ader2( 7 downto 0) <= data_i;
when c_addr_func2_ader_1(18 downto 2) => s_reg_ader2(15 downto 8) <= data_i;
when c_addr_func2_ader_2(18 downto 2) => s_reg_ader2(23 downto 16) <= data_i;
when c_addr_func2_ader_3(18 downto 2) => s_reg_ader2(31 downto 24) <= data_i;
when c_addr_func1_ader_0(18 downto 2) => s_reg_ader1( 7 downto 0) <= data_i;
when c_addr_func1_ader_1(18 downto 2) => s_reg_ader1(15 downto 8) <= data_i;
when c_addr_func1_ader_2(18 downto 2) => s_reg_ader1(23 downto 16) <= data_i;
when c_addr_func1_ader_3(18 downto 2) => s_reg_ader1(31 downto 24) <= data_i;
when c_addr_func0_ader_0(18 downto 2) => s_reg_ader0( 7 downto 0) <= data_i;
when c_addr_func0_ader_1(18 downto 2) => s_reg_ader0(15 downto 8) <= data_i;
when c_addr_func0_ader_2(18 downto 2) => s_reg_ader0(23 downto 16) <= data_i;
when c_addr_func0_ader_3(18 downto 2) => s_reg_ader0(31 downto 24) <= data_i;
when to_integer("00" & c_Endian_addr(18 downto 2)) =>
s_CSRarray(Endian) <= s_locDataIn(7 downto 0);
when others => null;
end case;
end if;
when others => null;
end case;
if vme_berr_n_i = '0' then
s_reg_bit_reg(3) <= '1';
end if;
else
if g_wb_data_width = 32 then
s_CSRarray(WB32bits) <= x"01";
else
s_CSRarray(WB32bits) <= x"00";
if vme_sysfail_i = '1' then
s_reg_bit_reg(5) <= '1';
end if;
reset_flag <= '0';
s_CSRarray(BYTES0) <= unsigned(numBytes(7 downto 0));
s_CSRarray(BYTES1) <= resize(unsigned(numBytes(12 downto 8)), 8);
s_CSRarray(TIME0_ns) <= unsigned(transfTime(7 downto 0));
s_CSRarray(TIME1_ns) <= unsigned(transfTime(15 downto 8));
s_CSRarray(TIME2_ns) <= unsigned(transfTime(23 downto 16));
s_CSRarray(TIME3_ns) <= unsigned(transfTime(31 downto 24));
s_CSRarray(TIME4_ns) <= unsigned(transfTime(39 downto 32));
end if;
end if;
end process;
-- CSR Read
process(s_CSRarray, s_CrCsrOffsetAddr, err_flag)
bar_o <= s_reg_bar(7 downto 3);
ader0_o <= s_reg_ader0;
ader1_o <= s_reg_ader1;
ader2_o <= s_reg_ader2;
ader3_o <= s_reg_ader3;
ader4_o <= s_reg_ader4;
ader5_o <= s_reg_ader5;
ader6_o <= s_reg_ader6;
ader7_o <= s_reg_ader7;
module_enable_o <= s_reg_bit_reg(4);
vme_sysfail_ena_o <= s_reg_bit_reg(6);
module_reset_o <= s_reg_bit_reg(7);
-- Read
process (clk_i)
begin
s_CSRdata <= (others => '0');
case (s_CrCsrOffsetAddr) is
when "00" & c_BAR_addr(18 downto 2) => s_CSRdata <= s_CSRarray(BAR);
when "00" & c_BIT_SET_REG_addr(18 downto 2) => s_CSRdata <= s_CSRarray(
BIT_SET_CLR_REG)(7 downto 4) & err_flag & s_CSRarray(BIT_SET_CLR_REG)(2 downto 0);
when "00" & c_BIT_CLR_REG_addr(18 downto 2) => s_CSRdata <= s_CSRarray(
BIT_SET_CLR_REG)(7 downto 4) & err_flag & s_CSRarray(BIT_SET_CLR_REG)(2 downto 0);
when "00" & c_CRAM_OWNER_addr(18 downto 2) => s_CSRdata <= s_CSRarray(CRAM_OWNER);
when "00" & c_USR_BIT_SET_REG_addr(18 downto 2) => s_CSRdata <= s_CSRarray(USR_BIT_SET_CLR_REG);
when "00" & c_USR_BIT_CLR_REG_addr(18 downto 2) => s_CSRdata <= s_CSRarray(USR_BIT_SET_CLR_REG);
when "00" & c_FUNC7_ADER_0_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC7_ADER_0);
when "00" & c_FUNC7_ADER_1_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC7_ADER_1);
when "00" & c_FUNC7_ADER_2_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC7_ADER_2);
when "00" & c_FUNC7_ADER_3_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC7_ADER_3);
when "00" & c_FUNC6_ADER_0_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC6_ADER_0);
when "00" & c_FUNC6_ADER_1_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC6_ADER_1);
when "00" & c_FUNC6_ADER_2_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC6_ADER_2);
when "00" & c_FUNC6_ADER_3_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC6_ADER_3);
when "00" & c_FUNC5_ADER_0_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC5_ADER_0);
when "00" & c_FUNC5_ADER_1_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC5_ADER_1);
when "00" & c_FUNC5_ADER_2_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC5_ADER_2);
when "00" & c_FUNC5_ADER_3_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC5_ADER_3);
when "00" & c_FUNC4_ADER_0_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC4_ADER_0);
when "00" & c_FUNC4_ADER_1_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC4_ADER_1);
when "00" & c_FUNC4_ADER_2_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC4_ADER_2);
when "00" & c_FUNC4_ADER_3_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC4_ADER_3);
when "00" & c_FUNC3_ADER_0_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC3_ADER_0);
when "00" & c_FUNC3_ADER_1_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC3_ADER_1);
when "00" & c_FUNC3_ADER_3_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC3_ADER_3);
when "00" & c_FUNC2_ADER_0_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC2_ADER_0);
when "00" & c_FUNC2_ADER_1_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC2_ADER_1);
when "00" & c_FUNC2_ADER_2_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC2_ADER_2);
when "00" & c_FUNC2_ADER_3_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC2_ADER_3);
when "00" & c_FUNC1_ADER_0_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC1_ADER_0);
when "00" & c_FUNC1_ADER_1_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC1_ADER_1);
when "00" & c_FUNC1_ADER_2_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC1_ADER_2);
when "00" & c_FUNC1_ADER_3_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC1_ADER_3);
when "00" & c_FUNC0_ADER_0_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC0_ADER_0);
when "00" & c_FUNC0_ADER_1_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC0_ADER_1);
when "00" & c_FUNC0_ADER_2_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC0_ADER_2);
when "00" & c_FUNC0_ADER_3_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC0_ADER_3);
when "00" & c_IRQ_Vector_addr (18 downto 2) => s_CSRdata <= s_CSRarray(IRQ_Vector);
when "00" & c_IRQ_level_addr(18 downto 2) => s_CSRdata <= s_CSRarray(IRQ_level);
when "00" & c_Endian_addr(18 downto 2) => s_CSRdata <= s_CSRarray(Endian);
when "00" & c_TIME0_ns_addr(18 downto 2) => s_CSRdata <= s_CSRarray(TIME0_ns);
when "00" & c_TIME1_ns_addr(18 downto 2) => s_CSRdata <= s_CSRarray(TIME1_ns);
when "00" & c_TIME2_ns_addr(18 downto 2) => s_CSRdata <= s_CSRarray(TIME2_ns);
when "00" & c_TIME3_ns_addr(18 downto 2) => s_CSRdata <= s_CSRarray(TIME3_ns);
when "00" & c_TIME4_ns_addr(18 downto 2) => s_CSRdata <= s_CSRarray(TIME4_ns);
when "00" & c_BYTES0_addr(18 downto 2) => s_CSRdata <= s_CSRarray(BYTES0);
when "00" & c_BYTES1_addr(18 downto 2) => s_CSRdata <= s_CSRarray(BYTES1);
when "00" & c_WB32bits_addr(18 downto 2) => s_CSRdata <= s_CSRarray(WB32bits);
when others => s_CSRdata <= (others => '0');
end case;
if rising_edge(clk_i) then
if reset_i = '1' then
s_csr_data <= x"ff";
else
case s_addr is
when c_addr_bar(18 downto 2) => s_csr_data <= s_reg_bar;
when c_addr_bit_set_reg(18 downto 2) => s_csr_data <= s_reg_bit_reg;
when c_addr_bit_clr_reg(18 downto 2) => s_csr_data <= s_reg_bit_reg;
when c_addr_cram_owner(18 downto 2) => s_csr_data <= s_reg_cram_owner;
when c_addr_usr_set_reg(18 downto 2) => s_csr_data <= s_reg_usr_bit_reg;
when c_addr_usr_clr_reg(18 downto 2) => s_csr_data <= s_reg_usr_bit_reg;
when c_addr_func7_ader_0(18 downto 2) => s_csr_data <= s_reg_ader7( 7 downto 0);
when c_addr_func7_ader_1(18 downto 2) => s_csr_data <= s_reg_ader7(15 downto 8);
when c_addr_func7_ader_2(18 downto 2) => s_csr_data <= s_reg_ader7(23 downto 16);
when c_addr_func7_ader_3(18 downto 2) => s_csr_data <= s_reg_ader7(31 downto 24);
when c_addr_func6_ader_0(18 downto 2) => s_csr_data <= s_reg_ader6( 7 downto 0);
when c_addr_func6_ader_1(18 downto 2) => s_csr_data <= s_reg_ader6(15 downto 8);
when c_addr_func6_ader_2(18 downto 2) => s_csr_data <= s_reg_ader6(23 downto 16);
when c_addr_func6_ader_3(18 downto 2) => s_csr_data <= s_reg_ader6(31 downto 24);
when c_addr_func5_ader_0(18 downto 2) => s_csr_data <= s_reg_ader5( 7 downto 0);
when c_addr_func5_ader_1(18 downto 2) => s_csr_data <= s_reg_ader5(15 downto 8);
when c_addr_func5_ader_2(18 downto 2) => s_csr_data <= s_reg_ader5(23 downto 16);
when c_addr_func5_ader_3(18 downto 2) => s_csr_data <= s_reg_ader5(31 downto 24);
when c_addr_func4_ader_0(18 downto 2) => s_csr_data <= s_reg_ader4( 7 downto 0);
when c_addr_func4_ader_1(18 downto 2) => s_csr_data <= s_reg_ader4(15 downto 8);
when c_addr_func4_ader_2(18 downto 2) => s_csr_data <= s_reg_ader4(23 downto 16);
when c_addr_func4_ader_3(18 downto 2) => s_csr_data <= s_reg_ader4(31 downto 24);
when c_addr_func3_ader_0(18 downto 2) => s_csr_data <= s_reg_ader3( 7 downto 0);
when c_addr_func3_ader_1(18 downto 2) => s_csr_data <= s_reg_ader3(15 downto 8);
when c_addr_func3_ader_2(18 downto 2) => s_csr_data <= s_reg_ader3(23 downto 16);
when c_addr_func3_ader_3(18 downto 2) => s_csr_data <= s_reg_ader3(31 downto 24);
when c_addr_func2_ader_0(18 downto 2) => s_csr_data <= s_reg_ader2( 7 downto 0);
when c_addr_func2_ader_1(18 downto 2) => s_csr_data <= s_reg_ader2(15 downto 8);
when c_addr_func2_ader_2(18 downto 2) => s_csr_data <= s_reg_ader2(23 downto 16);
when c_addr_func2_ader_3(18 downto 2) => s_csr_data <= s_reg_ader2(31 downto 24);
when c_addr_func1_ader_0(18 downto 2) => s_csr_data <= s_reg_ader1( 7 downto 0);
when c_addr_func1_ader_1(18 downto 2) => s_csr_data <= s_reg_ader1(15 downto 8);
when c_addr_func1_ader_2(18 downto 2) => s_csr_data <= s_reg_ader1(23 downto 16);
when c_addr_func1_ader_3(18 downto 2) => s_csr_data <= s_reg_ader1(31 downto 24);
when c_addr_func0_ader_0(18 downto 2) => s_csr_data <= s_reg_ader0( 7 downto 0);
when c_addr_func0_ader_1(18 downto 2) => s_csr_data <= s_reg_ader0(15 downto 8);
when c_addr_func0_ader_2(18 downto 2) => s_csr_data <= s_reg_ader0(23 downto 16);
when c_addr_func0_ader_3(18 downto 2) => s_csr_data <= s_reg_ader0(31 downto 24);
when others => s_csr_data <= x"ff";
end case;
end if;
end if;
end process;
INT_Level <= std_logic_vector(s_CSRarray(IRQ_level));
INT_Vector <= std_logic_vector(s_CSRarray(IRQ_Vector));
CSRdata <= std_logic_vector(s_CSRdata);
s_CrCsrOffsetAddr <= unsigned(CrCsrOffsetAddr);
-- Generate a vector of 8 array (unsigned 32 bits).
GADER_1 : for i in 0 to 7 generate
GADER_2 : for h in 0 to 3 generate
s_FUNC_ADER(i)(8*(4-h)-1 downto 8*(3-h)) <= s_CSRarray(FUNC0_ADER_3+(h+i*4));
end generate GADER_2;
end generate GADER_1;
-- To the decoder
Ader0 <= std_logic_vector(s_FUNC_ADER(0));
Ader1 <= std_logic_vector(s_FUNC_ADER(1));
Ader2 <= std_logic_vector(s_FUNC_ADER(2));
Ader3 <= std_logic_vector(s_FUNC_ADER(3));
Ader4 <= std_logic_vector(s_FUNC_ADER(4));
Ader5 <= std_logic_vector(s_FUNC_ADER(5));
Ader6 <= std_logic_vector(s_FUNC_ADER(6));
Ader7 <= std_logic_vector(s_FUNC_ADER(7));
ModuleEnable <= s_CSRarray(BIT_SET_CLR_REG)(4);
Endian_o <= std_logic_vector(s_CSRarray(Endian)(2 downto 0));
Sw_Reset <= s_CSRarray(BIT_SET_CLR_REG)(7);
BAR_o <= s_BAR_o;
s_BAR_o <= std_logic_vector(s_CSRarray(BAR)(7 downto 3));
------------------------------------------------------------------------------
-- CRAM
CRAM_1 : VME_CRAM
generic map (
dl => 8,
al => f_log2_size(g_cram_size)
)
port map (
clk => clk_i,
we => CRAM_Wen,
aw => CRAM_addr,
di => CRAM_data_i,
dw => CRAM_data_o
);
------------------------------------------------------------------------------
gen_cram: if f_size(g_beg_cram, g_end_cram) > 1 generate
s_cram_access <= '1' when s_addr(18 downto 2) >= unsigned(g_beg_cram(18 downto 2)) and
s_addr(18 downto 2) <= unsigned(g_end_cram(18 downto 2))
else '0';
s_cram_addr <= std_logic_vector(s_addr - unsigned(g_beg_cram(18 downto 2)));
s_cram_we <= we_i and s_cram_access;
cmp_cram: VME_CRAM
generic map (
g_beg_cram => g_beg_cram,
g_end_cram => g_end_cram
)
port map (
clk_i => clk_i,
we_i => s_cram_we,
addr_i => s_cram_addr,
data_i => data_i,
data_o => s_cram_data
);
end generate;
gen_no_cram: if f_size(g_beg_cram, g_end_cram) <= 1 generate
s_cram_access <= '0';
s_cram_addr <= (others => '0');
s_cram_data <= x"00";
end generate;
------------------------------------------------------------------------------
-- User CR/CSR
------------------------------------------------------------------------------
gen_user_cr: if f_size(g_beg_user_cr, g_end_user_cr) > 1 generate
s_user_cr_access <= '1' when s_addr >= unsigned(g_beg_user_cr(18 downto 2)) and
s_addr <= unsigned(g_end_user_cr(18 downto 2))
else '0';
user_cr_addr_o <= std_logic_vector(s_addr - unsigned(g_beg_user_cr(18 downto 2)));
end generate;
gen_no_user_cr: if f_size(g_beg_user_cr, g_end_user_cr) <= 1 generate
s_user_cr_access <= '0';
user_cr_addr_o <= (others => '0');
end generate;
gen_user_csr: if f_size(g_beg_user_csr, g_end_user_csr) > 1 generate
s_user_csr_access <= '1' when s_addr >= unsigned(g_beg_user_csr(18 downto 2)) and
s_addr <= unsigned(g_end_user_csr(18 downto 2))
else '0';
user_csr_addr_o <= std_logic_vector(s_addr - unsigned(g_beg_user_csr(18 downto 2)));
end generate;
gen_no_user_csr: if f_size(g_beg_user_csr, g_end_user_csr) <= 1 generate
s_user_csr_access <= '0';
user_csr_addr_o <= (others => '0');
end generate;
user_csr_data_o <= data_i;
user_csr_we_o <= we_i and s_user_csr_access;
------------------------------------------------------------------------------
-- Read Multiplexer
------------------------------------------------------------------------------
process (
s_cr_access, s_cr_data,
s_csr_access, s_csr_data,
s_cram_access, s_cram_data,
s_user_cr_access, user_cr_data_i,
s_user_csr_access, user_csr_data_i
) begin
if s_cr_access = '1' then
data_o <= s_cr_data;
elsif s_csr_access = '1' then
data_o <= s_csr_data;
elsif s_cram_access = '1' then
data_o <= s_cram_data;
elsif s_user_cr_access = '1' then
data_o <= user_cr_data_i;
elsif s_user_csr_access = '1' then
data_o <= user_csr_data_i;
else
data_o <= x"ff";
end if;
end process;
end Behavioral;
end rtl;
hdl/vme64x-core/rtl/VME_User_CSR.vhd 0 → 100644
View file @ 62b13b5e
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- VME64x Core
-- http://www.ohwr.org/projects/vme64x-core
--------------------------------------------------------------------------------
--
-- unit name: VME_User_CSR (VME_User_CSR.vhd)
--
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch>
--
-- description:
--
-- This module implements the user CSR registers that were added to the
-- reserved area of the defined CSR in previous versions of this core.
--
-- To achieve the previous memory map layout, it is necessary to set the
-- following generics on the VME64xCore_Top:
--
-- g_beg_user_csr => x"07ff33",
-- g_end_user_csr => x"07ff5f",
--
-- However, for new designs it would be better to choose somewhere outside
-- the reserved area (from x"7fc00" to x"7ff5f"). For example:
--
-- g_beg_user_csr => x"07fbd3",
-- g_end_user_csr => x"07fbff",
--
-- The following registers are implemented:
-- _
-- IRQ_Vector --> 0x0002F |--> For the VME_IRQ_Controller
-- IRQ_level --> 0x0002B _|
--
-- Endian --> 0x00023 ----> For the VME_swapper
-- _
-- TIME0_ns --> 0x0001F |
-- TIME1_ns --> 0x0001B |
-- TIME2_ns --> 0x00017 |
-- TIME3_ns --> 0x00013 |--> To calculate the transfer rate
-- TIME4_ns --> 0x0000F | (not currently implemented)
-- BYTES0 --> 0x0000B |
-- BYTES1 --> 0x00007 _|
--
-- WB32bits --> 0x00003 ----> If bit 0 is '1' the WB data bus is 32b
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vme64x_pack.all;
entity VME_User_CSR is
generic (
g_wb_data_width : integer
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
addr_i : in std_logic_vector(18 downto 2);
data_i : in std_logic_vector( 7 downto 0);
data_o : out std_logic_vector( 7 downto 0);
we_i : in std_logic;
irq_vector_o : out std_logic_vector( 7 downto 0);
irq_level_o : out std_logic_vector( 7 downto 0);
endian_o : out std_logic_vector( 2 downto 0);
bytes_i : in std_logic_vector(15 downto 0);
time_i : in std_logic_vector(39 downto 0)
);
end VME_User_CSR;
architecture rtl of VME_User_CSR is
signal s_addr : unsigned(18 downto 2);
signal s_reg_irq_vector : std_logic_vector(7 downto 0);
signal s_reg_irq_level : std_logic_vector(7 downto 0);
signal s_reg_endian : std_logic_vector(7 downto 0);
signal s_reg_wb32bits : std_logic_vector(7 downto 0);
begin
s_addr <= unsigned(addr_i);
s_reg_wb32bits <= x"01" when g_wb_data_width = 32 else x"00";
-- Write
process (clk_i)
begin
if rising_edge(clk_i) then
if reset_i = '1' then
s_reg_irq_vector <= x"00";
s_reg_irq_level <= x"00";
s_reg_endian <= x"00";
else
if we_i = '1' then
case s_addr is
when c_addr_irq_vector(18 downto 2) => s_reg_irq_vector <= data_i;
when c_addr_irq_level(18 downto 2) => s_reg_irq_level <= data_i;
when c_addr_endian(18 downto 2) => s_reg_endian <= data_i;
when others => null;
end case;
end if;
end if;
end if;
end process;
irq_vector_o <= s_reg_irq_vector;
irq_level_o <= s_reg_irq_level;
endian_o <= s_reg_endian(2 downto 0);
-- Read
process (clk_i)
begin
if rising_edge(clk_i) then
if reset_i = '1' then
data_o <= x"00";
else
case s_addr is
when c_addr_irq_vector(18 downto 2) => data_o <= s_reg_irq_vector;
when c_addr_irq_level(18 downto 2) => data_o <= s_reg_irq_level;
when c_addr_endian(18 downto 2) => data_o <= s_reg_endian;
when c_addr_time0_ns(18 downto 2) => data_o <= time_i( 7 downto 0);
when c_addr_time1_ns(18 downto 2) => data_o <= time_i(15 downto 8);
when c_addr_time2_ns(18 downto 2) => data_o <= time_i(23 downto 16);
when c_addr_time3_ns(18 downto 2) => data_o <= time_i(31 downto 24);
when c_addr_time4_ns(18 downto 2) => data_o <= time_i(39 downto 32);
when c_addr_bytes0(18 downto 2) => data_o <= bytes_i( 7 downto 0);
when c_addr_bytes1(18 downto 2) => data_o <= bytes_i(15 downto 8);
when c_addr_wb32bits(18 downto 2) => data_o <= s_reg_wb32bits;
when others => data_o <= x"ff";
end case;
end if;
end if;
end process;
end rtl;
hdl/vme64x-core/rtl/VME_bus.vhd
View file @ 62b13b5e
......@@ -121,7 +121,7 @@ entity VME_bus is
VME_DS_ant_n_i : in std_logic_vector(1 downto 0);
VME_DTACK_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_BERR_o : out std_logic;
VME_BERR_n_o : out std_logic;
VME_ADDR_i : in std_logic_vector(31 downto 1);
VME_ADDR_o : out std_logic_vector(31 downto 1) := (others => '0');
VME_ADDR_DIR_o : out std_logic;
......@@ -135,49 +135,42 @@ entity VME_bus is
-- because VME_IACKIN_n_i is delayed the
-- more you are away from Slots 0
-- WB signals
memReq_o : out std_logic;
memAckWB_i : in std_logic;
wbData_o : out std_logic_vector(g_wb_data_width-1 downto 0);
wbData_i : in std_logic_vector(g_wb_data_width-1 downto 0);
locAddr_o : out std_logic_vector(g_wb_addr_width-1 downto 0);
wbSel_o : out std_logic_vector(g_wb_data_width/8-1 downto 0);
RW_o : out std_logic;
stb_o : out std_logic;
ack_i : in std_logic;
dat_o : out std_logic_vector(g_wb_data_width-1 downto 0);
dat_i : in std_logic_vector(g_wb_data_width-1 downto 0);
adr_o : out std_logic_vector(g_wb_addr_width-1 downto 0);
sel_o : out std_logic_vector(g_wb_data_width/8-1 downto 0);
we_o : out std_logic;
cyc_o : out std_logic;
err_i : in std_logic;
rty_i : in std_logic;
stall_i : in std_logic;
--CR/CSR space signals:
CRAMaddr_o : out std_logic_vector(f_log2_size(f_size(g_beg_cram, g_end_cram))-1 downto 0);
CRAMdata_o : out std_logic_vector(7 downto 0);
CRAMdata_i : in std_logic_vector(7 downto 0);
CRAMwea_o : out std_logic;
CRaddr_o : out std_logic_vector(11 downto 0);
CRdata_i : in std_logic_vector(7 downto 0);
en_wr_CSR : out std_logic;
CrCsrOffsetAddr : out std_logic_vector(18 downto 0);
CSRData_o : out std_logic_vector(7 downto 0);
CSRData_i : in std_logic_vector(7 downto 0);
err_flag_o : out std_logic;
reset_flag_i : in std_logic;
Ader0 : in std_logic_vector(31 downto 0);
Ader1 : in std_logic_vector(31 downto 0);
Ader2 : in std_logic_vector(31 downto 0);
Ader3 : in std_logic_vector(31 downto 0);
Ader4 : in std_logic_vector(31 downto 0);
Ader5 : in std_logic_vector(31 downto 0);
Ader6 : in std_logic_vector(31 downto 0);
Ader7 : in std_logic_vector(31 downto 0);
ModuleEnable : in std_logic;
Endian_i : in std_logic_vector(2 downto 0);
Sw_Reset : in std_logic;
BAR_i : in std_logic_vector(4 downto 0)
cr_csr_addr_o : out std_logic_vector(18 downto 2);
cr_csr_data_i : in std_logic_vector( 7 downto 0);
cr_csr_data_o : out std_logic_vector( 7 downto 0);
cr_csr_we_o : out std_logic;
ader0_i : in std_logic_vector(31 downto 0);
ader1_i : in std_logic_vector(31 downto 0);
ader2_i : in std_logic_vector(31 downto 0);
ader3_i : in std_logic_vector(31 downto 0);
ader4_i : in std_logic_vector(31 downto 0);
ader5_i : in std_logic_vector(31 downto 0);
ader6_i : in std_logic_vector(31 downto 0);
ader7_i : in std_logic_vector(31 downto 0);
endian_i : in std_logic_vector(2 downto 0);
module_enable_i : in std_logic;
module_reset_i : in std_logic;
bar_i : in std_logic_vector(4 downto 0)
);
end VME_bus;
architecture RTL of VME_bus is
signal s_reset : std_logic;
signal s_rw : std_logic;
-- Input signals
signal s_VMEaddrInput : unsigned(31 downto 1);
......@@ -202,7 +195,6 @@ architecture RTL of VME_bus is
signal s_phase2addr : unsigned(63 downto 0) := (others => '0'); --
-- signal s_phase3addr : unsigned(63 downto 0); --
signal s_addrOffset : unsigned(17 downto 0); -- block transfers|
signal s_CrCsrOffsetAddr : unsigned(18 downto 0) := (others => '0'); -- CR/CSR address
signal s_DataShift : unsigned(5 downto 0);
-- uncomment if 2e is implemented:
--signal s_2eLatchAddr : std_logic_vector(1 downto 0); -- for 2e transfers
......@@ -261,16 +253,6 @@ architecture RTL of VME_bus is
-- WishBone signals
signal s_sel : unsigned(7 downto 0); -- SEL WB signal
signal s_nx_sel : std_logic_vector(7 downto 0);
signal s_RW : std_logic; -- RW WB signal
-- CR/CSR related signals
signal s_CRaddressed : std_logic; -- CR is addressed
signal s_CRAMaddressed : std_logic; -- CRAM is addressed
signal s_CSRaddressed : std_logic; -- CSR space is addressed
signal s_CSRdata : unsigned(7 downto 0); -- CSR data write/read
signal s_CRdataIn : std_logic_vector(7 downto 0); -- CR data bus
signal s_CRdataIn1 : std_logic_vector(7 downto 0); --
signal s_CRAMdataIn : std_logic_vector(7 downto 0); -- CRAM data bus
-- Error signals
signal s_BERRcondition : std_logic; -- Condition for asserting BERR
......@@ -278,8 +260,6 @@ architecture RTL of VME_bus is
signal s_rty1 : std_logic;
-- Initialization signals
signal s_CRaddr : unsigned(18 downto 0);
signal s_prev_VME_AS_n : std_logic;
signal s_is_d64 : std_logic;
signal s_base_addr : unsigned(63 downto 0);
......@@ -288,12 +268,9 @@ architecture RTL of VME_bus is
signal s_VMEdata64In : unsigned(63 downto 0);
signal s_BERR_out : std_logic;
signal s_errorflag : std_logic;
signal s_resetflag : std_logic;
signal s_sw_reset : std_logic;
signal s_decode : std_logic;
signal s_AckWb : std_logic;
signal s_CRCSRtype : std_logic;
signal s_err : std_logic;
signal s_rty : std_logic;
......@@ -309,8 +286,6 @@ begin
-- Used to drive the VME_ADDR_DIR_o
s_is_d64 <= '1' when s_sel = "11111111" else '0';
s_RW <= VME_WRITE_n_i;
-- HW and SW reset
s_reset <= (not rst_n_i) or (not VME_RST_n_i) or s_sw_reset;
reset_o <= s_reset; -- Asserted when high
......@@ -615,9 +590,9 @@ begin
s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_dataPhase <= s_dataPhase;
s_FSM.s_transferActive <= '1';
if s_memAck = '1' and s_RW = '0' then
if s_memAck = '1' and VME_WRITE_n_i = '0' then
s_mainFSMstate <= DTACK_LOW;
elsif s_memAck = '1' and s_RW = '1' then
elsif s_memAck = '1' and VME_WRITE_n_i = '1' then
if s_transferType = MBLT then
s_FSM.s_dataToAddrBus <= '1';
else
......@@ -755,24 +730,9 @@ begin
-- s_berr_1 <= s_berr;
-- s_berr_2 <= s_berr and s_berr_1;
if (s_BERR_out = '1') then
VME_BERR_o <= '1'; -- The VME_BERR is asserted when '1' becouse
-- the buffers on the board invert the logic
VME_BERR_n_o <= '0';
else
VME_BERR_o <= '0';
end if;
end if;
end process;
-- When the VME_BERR line is asserted this process asserts the error flag;
-- This flag acts as the BERR flag --> BIT SET REGISTER's bit 3 in the CSR
-- space
FlagError : process (clk_i)
begin
if rising_edge (clk_i) then
if s_resetflag = '1' or s_reset = '1' then
s_errorflag <= '0';
elsif (s_BERR_out = '1') then
s_errorflag <= '1';
VME_BERR_n_o <= '1';
end if;
end if;
end process;
......@@ -787,12 +747,9 @@ begin
process (clk_i)
begin
if rising_edge(clk_i) then
if s_reset = '1' then s_BERRcondition <= '0';
if s_reset = '1' then
s_BERRcondition <= '0';
elsif
(s_CRAMaddressed = '1' and s_CRaddressed = '1') or
(s_CRAMaddressed = '1' and s_CSRaddressed = '1') or
(s_CRaddressed = '1' and s_confAccess = '1' and s_RW = '0') or
(s_CSRaddressed = '1' and s_CRaddressed = '1') or
((s_transferType = error or s_wberr1 = '1') and s_transferActive = '1') or
(s_typeOfDataTransfer = TypeError) or
(s_addressingType = AM_Error) or
......@@ -962,16 +919,6 @@ begin
end if;
end process;
s_CrCsrOffsetAddr <= "00" & s_locAddr(18 downto 2)
when s_mainFSMreset = '0'
else (others => '0');
s_CRaddr <= s_CrCsrOffsetAddr;
CRaddr_o <= std_logic_vector(s_CRaddr(11 downto 0));
CRAMaddr_o <= std_logic_vector(resize(s_CrCsrOffsetAddr - unsigned(g_beg_cram(18 downto 0)),
f_log2_size(f_size(g_beg_cram, g_end_cram))));
------------------------------------------------------------------------------
-- Data Handler Process
------------------------------------------------------------------------------
......@@ -997,28 +944,6 @@ begin
end if;
end process;
CSRData_o <= std_logic_vector(s_locDataIn(7 downto 0));
process (clk_i)
begin
if rising_edge(clk_i) then
CRAMdata_o <= std_logic_vector(s_locDataIn(7 downto 0));
if (
s_confAccess = '1' and s_CRAMaddressed = '1' and s_memReq = '1' and
s_RW = '0' and (
s_typeOfDataTransfer = D08_3 or s_typeOfDataTransfer = D32 or
s_typeOfDataTransfer = D16_23 or (
s_typeOfDataTransfer = D64 and s_transferType /= MBLT
)
)
) then
CRAMwea_o <= '1';
else
CRAMwea_o <= '0';
end if;
end if;
end process;
-- Swap the data during read or write operation
-- sel= 000 --> No swap
-- sel= 001 --> Swap Byte eg: 01234567 become 10325476
......@@ -1028,45 +953,27 @@ begin
swapper_write : VME_swapper
port map (
d_i => std_logic_vector(s_locDataIn),
sel => Endian_i,
sel => endian_i,
d_o => s_locDataInSwap
);
swapper_read : VME_swapper
port map (
d_i => std_logic_vector(s_locData),
sel => Endian_i,
sel => endian_i,
d_o => s_locDataSwap
);
-- Data from WB or CR/CSR to VME bus
s_CRCSRtype <= '1' when (
s_typeOfDataTransfer = D08_3 or
s_typeOfDataTransfer = D32 or
s_typeOfDataTransfer = D16_23 or
(s_typeOfDataTransfer = D64 and s_transferType /= MBLT)
) else '0';
process (clk_i)
begin
if rising_edge(clk_i) then
if s_cardSel = '1' then
s_locDataOut <= unsigned(s_locDataOutWb);
elsif s_confAccess = '1' and s_CSRaddressed = '1' and
s_CRAMaddressed = '0' and s_CRaddressed = '0' and
s_CRCSRtype = '1'
then
s_locDataOut <= resize(s_CSRdata, s_locDataOut'length);
elsif s_confAccess = '1' and s_CRaddressed = '1' and
s_CRAMaddressed = '0' and s_CSRaddressed = '0' and
s_CRCSRtype = '1'
then
s_locDataOut <= resize(unsigned(s_CRdataIn), s_locDataOut'length);
elsif s_confAccess = '1' and s_CRAMaddressed = '1' and
s_CRaddressed = '0' and s_CSRaddressed = '0' and
s_CRCSRtype = '1'
then
s_locDataOut <= resize(unsigned(s_CRAMdataIn), s_locDataOut'length);
elsif s_confAccess = '1' then
s_locDataOut <= resize(unsigned(cr_csr_data_i), s_locDataOut'length);
else
s_locDataOut <= (others => '0');
end if;
......@@ -1074,7 +981,6 @@ begin
end process;
s_locData(63 downto 0) <= s_locDataOut(63 downto 0) sll to_integer(unsigned(s_DataShift));
s_CSRdata <= unsigned(CSRData_i);
------------------------------------------------------------------------------
-- Memory Mapping
......@@ -1178,20 +1084,22 @@ begin
memAckWb_o => s_AckWb,
err_o => s_err,
rty_o => s_rty,
RW_i => s_RW,
RW_i => VME_WRITE_n_i,
stall_i => stall_i,
rty_i => rty_i,
err_i => err_i,
cyc_o => cyc_o,
memReq_o => memReq_o,
WBdata_o => wbData_o,
wbData_i => wbData_i,
locAddr_o => locAddr_o,
memAckWB_i => memAckWB_i,
WbSel_o => wbSel_o,
RW_o => RW_o
memReq_o => stb_o,
WBdata_o => dat_o,
wbData_i => dat_i,
locAddr_o => adr_o,
memAckWB_i => ack_i,
WbSel_o => sel_o,
RW_o => s_rw
);
we_o <= not s_rw;
------------------------------------------------------------------------------
-- Decoder
------------------------------------------------------------------------------
......@@ -1205,16 +1113,16 @@ begin
reset => s_reset,
mainFSMreset => s_mainFSMreset,
decode => s_decode,
ModuleEnable => ModuleEnable,
ModuleEnable => module_enable_i,
Addr => std_logic_vector(s_locAddr),
Ader0 => Ader0,
Ader1 => Ader1,
Ader2 => Ader2,
Ader3 => Ader3,
Ader4 => Ader4,
Ader5 => Ader5,
Ader6 => Ader6,
Ader7 => Ader7,
Ader0 => ader0_i,
Ader1 => ader1_i,
Ader2 => ader2_i,
Ader3 => ader3_i,
Ader4 => ader4_i,
Ader5 => ader5_i,
Ader6 => ader6_i,
Ader7 => ader7_i,
Adem0 => g_f0_adem,
Adem1 => g_f1_adem,
Adem2 => g_f2_adem,
......@@ -1241,7 +1149,7 @@ begin
XAmCap7 => g_f7_xamcap,
Am => s_AMlatched,
XAm => std_logic_vector(s_XAM),
BAR_i => BAR_i,
BAR_i => bar_i,
AddrWidth => s_addrWidth,
Funct_Sel => s_func_sel,
Base_Addr => s_nx_base_addr,
......@@ -1251,34 +1159,6 @@ begin
s_base_addr <= unsigned(s_nx_base_addr);
-- CR/CSR addressing
-- Please note that the location of the user defined CR and CSR regions as
-- well as the CRAM region are programmable. If these regions are overlapped
-- the vme64x core asserts the BERR* line
s_CSRaddressed <= '1' when (
s_locAddr(18 downto 0) <= x"7FFFF" and
s_locAddr(18 downto 0) >= x"7FC00"
) xor (
s_locAddr(18 downto 0) >= unsigned(g_beg_user_csr(18 downto 0)) and
s_locAddr(18 downto 0) <= unsigned(g_end_user_csr(18 downto 0)) and
unsigned(g_beg_user_csr) < unsigned(g_end_user_csr)
) else '0';
s_CRaddressed <= '1' when (
s_locAddr(18 downto 0) <= x"00FFF" and
s_locAddr(18 downto 0) >= x"00000"
) xor (
s_locAddr(18 downto 0) >= unsigned(g_beg_user_cr(18 downto 0)) and
s_locAddr(18 downto 0) <= unsigned(g_end_user_cr(18 downto 0)) and
unsigned(g_beg_user_cr) < unsigned(g_end_user_cr)
) else '0';
s_CRAMaddressed <= '1' when (
s_locAddr(18 downto 0) >= unsigned(g_beg_cram(18 downto 0)) and
s_locAddr(18 downto 0) <= unsigned(g_end_cram(18 downto 0)) and
unsigned(g_beg_cram) < unsigned(g_end_cram)
) else '0';
------------------------------------------------------------------------------
-- Acknowledge
------------------------------------------------------------------------------
......@@ -1309,29 +1189,25 @@ begin
------------------------------------------------------------------------------
-- CR/CSR In/Out
------------------------------------------------------------------------------
en_wr_CSR <= '1'
when (
(s_typeOfDataTransfer = D08_3 or
s_typeOfDataTransfer = D32 or
s_typeOfDataTransfer = D16_23 or
(s_typeOfDataTransfer = D64 and s_transferType /= MBLT)
) and s_memReq = '1' and s_confAccess = '1' and s_RW = '0'
) else '0';
cr_csr_data_o <= std_logic_vector(s_locDataIn(7 downto 0));
cr_csr_addr_o <= std_logic_vector(s_locAddr(18 downto 2));
CrCsrOffsetAddr <= std_logic_vector(s_CrCsrOffsetAddr);
cr_csr_we_o <= '1' when s_memReq = '1' and
s_confAccess = '1' and
s_RW = '0'
else '0';
err_flag_o <= s_errorflag;
s_resetflag <= reset_flag_i;
-- Software reset: the VME Master assert the BIT SET REGISTER's bit 7. The
-- reset will be effective the next AS rising edge at the end of the write
-- operation in this register. The sw reset is a pulse
------------------------------------------------------------------------------
-- Software Reset
------------------------------------------------------------------------------
-- The VME Master assert the BIT SET REGISTER's bit 7. The reset will be
-- effective the next AS rising edge at the end of the write operation in this
-- register.
process (clk_i)
begin
if rising_edge(clk_i) then
if s_mainFSMreset = '1' then
s_sw_reset <= Sw_Reset;
s_sw_reset <= module_reset_i;
else
s_sw_reset <= '0';
end if;
......@@ -1358,19 +1234,4 @@ begin
end if;
end process;
process (clk_i)
begin
if rising_edge(clk_i) then
s_CRdataIn1 <= CRdata_i;
s_CRdataIn <= s_CRdataIn1;
end if;
end process;
process (clk_i)
begin
if rising_edge(clk_i) then
s_CRAMdataIn <= CRAMdata_i;
end if;
end process;
end RTL;
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @ 62b13b5e
......@@ -135,55 +135,6 @@ package vme64x_pack is
constant c_A32_2eSST : std_logic_vector(7 downto 0) := "00010001"; -- 0x11
constant c_A64_2eSST : std_logic_vector(7 downto 0) := "00010010"; -- 0x12
-- CSR array's index:
constant BAR : integer := 255;
constant BIT_SET_CLR_REG : integer := 254;
constant USR_BIT_SET_CLR_REG : integer := 253;
constant CRAM_OWNER : integer := 252;
constant FUNC7_ADER_0 : integer := 251;
constant FUNC7_ADER_1 : integer := FUNC7_ADER_0 - 1;
constant FUNC7_ADER_2 : integer := FUNC7_ADER_0 - 2;
constant FUNC7_ADER_3 : integer := FUNC7_ADER_0 - 3;
constant FUNC6_ADER_0 : integer := FUNC7_ADER_0 - 4;
constant FUNC6_ADER_1 : integer := FUNC7_ADER_0 - 5;
constant FUNC6_ADER_2 : integer := FUNC7_ADER_0 - 6;
constant FUNC6_ADER_3 : integer := FUNC7_ADER_0 - 7;
constant FUNC5_ADER_0 : integer := FUNC7_ADER_0 - 8;
constant FUNC5_ADER_1 : integer := FUNC7_ADER_0 - 9;
constant FUNC5_ADER_2 : integer := FUNC7_ADER_0 - 10;
constant FUNC5_ADER_3 : integer := FUNC7_ADER_0 - 11;
constant FUNC4_ADER_0 : integer := FUNC7_ADER_0 - 12;
constant FUNC4_ADER_1 : integer := FUNC7_ADER_0 - 13;
constant FUNC4_ADER_2 : integer := FUNC7_ADER_0 - 14;
constant FUNC4_ADER_3 : integer := FUNC7_ADER_0 - 15;
constant FUNC3_ADER_0 : integer := FUNC7_ADER_0 - 16;
constant FUNC3_ADER_1 : integer := FUNC7_ADER_0 - 17;
constant FUNC3_ADER_2 : integer := FUNC7_ADER_0 - 18;
constant FUNC3_ADER_3 : integer := FUNC7_ADER_0 - 19;
constant FUNC2_ADER_0 : integer := FUNC7_ADER_0 - 20;
constant FUNC2_ADER_1 : integer := FUNC7_ADER_0 - 21;
constant FUNC2_ADER_2 : integer := FUNC7_ADER_0 - 22;
constant FUNC2_ADER_3 : integer := FUNC7_ADER_0 - 23;
constant FUNC1_ADER_0 : integer := FUNC7_ADER_0 - 24;
constant FUNC1_ADER_1 : integer := FUNC7_ADER_0 - 25;
constant FUNC1_ADER_2 : integer := FUNC7_ADER_0 - 26;
constant FUNC1_ADER_3 : integer := FUNC7_ADER_0 - 27;
constant FUNC0_ADER_0 : integer := FUNC7_ADER_0 - 28;
constant FUNC0_ADER_1 : integer := FUNC7_ADER_0 - 29;
constant FUNC0_ADER_2 : integer := FUNC7_ADER_0 - 30;
constant FUNC0_ADER_3 : integer := FUNC7_ADER_0 - 31;
constant IRQ_Vector : integer := FUNC0_ADER_3 - 1;
constant IRQ_level : integer := FUNC0_ADER_3 - 2;
constant TIME0_ns : integer := FUNC0_ADER_3 - 5;
constant TIME1_ns : integer := FUNC0_ADER_3 - 6;
constant TIME2_ns : integer := FUNC0_ADER_3 - 7;
constant TIME3_ns : integer := FUNC0_ADER_3 - 8;
constant TIME4_ns : integer := FUNC0_ADER_3 - 9;
constant BYTES0 : integer := FUNC0_ADER_3 - 10;
constant BYTES1 : integer := FUNC0_ADER_3 - 11;
constant WB32bits : integer := FUNC0_ADER_3 - 12;
constant Endian : integer := FUNC0_ADER_3 - 4;
-- Main Finite State machine signals default:
-- When the S_FPGA detects the magic sequency, it erases the A_FPGA so
-- I don't need to drive the s_dtackOE, s_dataOE, s_addrOE, s_addrDir, s_dataDir
......@@ -221,56 +172,72 @@ package vme64x_pack is
s_DTACK_OE => '0'
);
-- CSR address:
constant c_BAR_addr : unsigned(19 downto 0) := x"7FFFF"; -- VME64x defined CSR
constant c_BIT_SET_REG_addr : unsigned(19 downto 0) := x"7FFFB";
constant c_BIT_CLR_REG_addr : unsigned(19 downto 0) := x"7FFF7";
constant c_CRAM_OWNER_addr : unsigned(19 downto 0) := x"7FFF3";
constant c_USR_BIT_SET_REG_addr : unsigned(19 downto 0) := x"7FFEF";
constant c_USR_BIT_CLR_REG_addr : unsigned(19 downto 0) := x"7FFEB";
constant c_FUNC7_ADER_0_addr : unsigned(19 downto 0) := x"7FFDF";
constant c_FUNC7_ADER_1_addr : unsigned(19 downto 0) := x"7FFDB";
constant c_FUNC7_ADER_2_addr : unsigned(19 downto 0) := x"7FFD7";
constant c_FUNC7_ADER_3_addr : unsigned(19 downto 0) := x"7FFD3";
constant c_FUNC6_ADER_0_addr : unsigned(19 downto 0) := x"7FFCF";
constant c_FUNC6_ADER_1_addr : unsigned(19 downto 0) := x"7FFCB";
constant c_FUNC6_ADER_2_addr : unsigned(19 downto 0) := x"7FFC7";
constant c_FUNC6_ADER_3_addr : unsigned(19 downto 0) := x"7FFC3";
constant c_FUNC5_ADER_0_addr : unsigned(19 downto 0) := x"7FFBF";
constant c_FUNC5_ADER_1_addr : unsigned(19 downto 0) := x"7FFBB";
constant c_FUNC5_ADER_2_addr : unsigned(19 downto 0) := x"7FFB7";
constant c_FUNC5_ADER_3_addr : unsigned(19 downto 0) := x"7FFB3";
constant c_FUNC4_ADER_0_addr : unsigned(19 downto 0) := x"7FFAF";
constant c_FUNC4_ADER_1_addr : unsigned(19 downto 0) := x"7FFAB";
constant c_FUNC4_ADER_2_addr : unsigned(19 downto 0) := x"7FFA7";
constant c_FUNC4_ADER_3_addr : unsigned(19 downto 0) := x"7FFA3";
constant c_FUNC3_ADER_0_addr : unsigned(19 downto 0) := x"7FF9F";
constant c_FUNC3_ADER_1_addr : unsigned(19 downto 0) := x"7FF9B";
constant c_FUNC3_ADER_2_addr : unsigned(19 downto 0) := x"7FF97";
constant c_FUNC3_ADER_3_addr : unsigned(19 downto 0) := x"7FF93";
constant c_FUNC2_ADER_0_addr : unsigned(19 downto 0) := x"7FF8F";
constant c_FUNC2_ADER_1_addr : unsigned(19 downto 0) := x"7FF8B";
constant c_FUNC2_ADER_2_addr : unsigned(19 downto 0) := x"7FF87";
constant c_FUNC2_ADER_3_addr : unsigned(19 downto 0) := x"7FF83";
constant c_FUNC1_ADER_0_addr : unsigned(19 downto 0) := x"7FF7F";
constant c_FUNC1_ADER_1_addr : unsigned(19 downto 0) := x"7FF7B";
constant c_FUNC1_ADER_2_addr : unsigned(19 downto 0) := x"7FF77";
constant c_FUNC1_ADER_3_addr : unsigned(19 downto 0) := x"7FF73";
constant c_FUNC0_ADER_0_addr : unsigned(19 downto 0) := x"7FF6F";
constant c_FUNC0_ADER_1_addr : unsigned(19 downto 0) := x"7FF6B";
constant c_FUNC0_ADER_2_addr : unsigned(19 downto 0) := x"7FF67";
constant c_FUNC0_ADER_3_addr : unsigned(19 downto 0) := x"7FF63"; -- VME64x defined CSR
constant c_IRQ_Vector_addr : unsigned(19 downto 0) := x"7FF5F"; -- VME64x reserved CSR
constant c_IRQ_level_addr : unsigned(19 downto 0) := x"7FF5B"; -- VME64x reserved CSR
constant c_TIME0_ns_addr : unsigned(19 downto 0) := x"7FF4f"; -- VME64x reserved CSR
constant c_TIME1_ns_addr : unsigned(19 downto 0) := x"7FF4b";
constant c_TIME2_ns_addr : unsigned(19 downto 0) := x"7FF47";
constant c_TIME3_ns_addr : unsigned(19 downto 0) := x"7FF43";
constant c_TIME4_ns_addr : unsigned(19 downto 0) := x"7FF3f";
constant c_BYTES0_addr : unsigned(19 downto 0) := x"7FF3b";
constant c_BYTES1_addr : unsigned(19 downto 0) := x"7FF37";
constant c_WB32bits_addr : unsigned(19 downto 0) := x"7FF33";
constant c_Endian_addr : unsigned(19 downto 0) := x"7FF53"; -- VME64x reserved CSR
-- Defined CR area
constant c_beg_cr : unsigned(19 downto 0) := x"00000";
constant c_end_cr : unsigned(19 downto 0) := x"00FFF";
-- Defined CSR area
-- NOTE: by the standard, the defined CSR area is from 7FC00..7FFFF and the
-- area from 7FC00..7FF5F is reserved. However the previous version of
-- this core placed some user defined registers from 7FF30..7FF5F.
-- Therefore, to allow compatibility with that version, the reserved
-- area is not decoded as part of the defined CSR. However, it is not
-- advisable to place any registers in this area in new designs.
constant c_beg_csr : unsigned(19 downto 0) := x"7FF60";
constant c_end_csr : unsigned(19 downto 0) := x"7FFFF";
-- Defined CSR addresses
constant c_addr_bar : unsigned(19 downto 0) := x"7FFFF";
constant c_addr_bit_set_reg : unsigned(19 downto 0) := x"7FFFB";
constant c_addr_bit_clr_reg : unsigned(19 downto 0) := x"7FFF7";
constant c_addr_cram_owner : unsigned(19 downto 0) := x"7FFF3";
constant c_addr_usr_set_reg : unsigned(19 downto 0) := x"7FFEF";
constant c_addr_usr_clr_reg : unsigned(19 downto 0) := x"7FFEB";
constant c_addr_func7_ader_0 : unsigned(19 downto 0) := x"7FFDF";
constant c_addr_func7_ader_1 : unsigned(19 downto 0) := x"7FFDB";
constant c_addr_func7_ader_2 : unsigned(19 downto 0) := x"7FFD7";
constant c_addr_func7_ader_3 : unsigned(19 downto 0) := x"7FFD3";
constant c_addr_func6_ader_0 : unsigned(19 downto 0) := x"7FFCF";
constant c_addr_func6_ader_1 : unsigned(19 downto 0) := x"7FFCB";
constant c_addr_func6_ader_2 : unsigned(19 downto 0) := x"7FFC7";
constant c_addr_func6_ader_3 : unsigned(19 downto 0) := x"7FFC3";
constant c_addr_func5_ader_0 : unsigned(19 downto 0) := x"7FFBF";
constant c_addr_func5_ader_1 : unsigned(19 downto 0) := x"7FFBB";
constant c_addr_func5_ader_2 : unsigned(19 downto 0) := x"7FFB7";
constant c_addr_func5_ader_3 : unsigned(19 downto 0) := x"7FFB3";
constant c_addr_func4_ader_0 : unsigned(19 downto 0) := x"7FFAF";
constant c_addr_func4_ader_1 : unsigned(19 downto 0) := x"7FFAB";
constant c_addr_func4_ader_2 : unsigned(19 downto 0) := x"7FFA7";
constant c_addr_func4_ader_3 : unsigned(19 downto 0) := x"7FFA3";
constant c_addr_func3_ader_0 : unsigned(19 downto 0) := x"7FF9F";
constant c_addr_func3_ader_1 : unsigned(19 downto 0) := x"7FF9B";
constant c_addr_func3_ader_2 : unsigned(19 downto 0) := x"7FF97";
constant c_addr_func3_ader_3 : unsigned(19 downto 0) := x"7FF93";
constant c_addr_func2_ader_0 : unsigned(19 downto 0) := x"7FF8F";
constant c_addr_func2_ader_1 : unsigned(19 downto 0) := x"7FF8B";
constant c_addr_func2_ader_2 : unsigned(19 downto 0) := x"7FF87";
constant c_addr_func2_ader_3 : unsigned(19 downto 0) := x"7FF83";
constant c_addr_func1_ader_0 : unsigned(19 downto 0) := x"7FF7F";
constant c_addr_func1_ader_1 : unsigned(19 downto 0) := x"7FF7B";
constant c_addr_func1_ader_2 : unsigned(19 downto 0) := x"7FF77";
constant c_addr_func1_ader_3 : unsigned(19 downto 0) := x"7FF73";
constant c_addr_func0_ader_0 : unsigned(19 downto 0) := x"7FF6F";
constant c_addr_func0_ader_1 : unsigned(19 downto 0) := x"7FF6B";
constant c_addr_func0_ader_2 : unsigned(19 downto 0) := x"7FF67";
constant c_addr_func0_ader_3 : unsigned(19 downto 0) := x"7FF63";
-- User CSR addresses
constant c_addr_irq_vector : unsigned(19 downto 0) := x"0002F";
constant c_addr_irq_level : unsigned(19 downto 0) := x"0002B";
constant c_addr_endian : unsigned(19 downto 0) := x"00023";
constant c_addr_time0_ns : unsigned(19 downto 0) := x"0001F";
constant c_addr_time1_ns : unsigned(19 downto 0) := x"0001B";
constant c_addr_time2_ns : unsigned(19 downto 0) := x"00017";
constant c_addr_time3_ns : unsigned(19 downto 0) := x"00013";
constant c_addr_time4_ns : unsigned(19 downto 0) := x"0000F";
constant c_addr_bytes0 : unsigned(19 downto 0) := x"0000B";
constant c_addr_bytes1 : unsigned(19 downto 0) := x"00007";
constant c_addr_wb32bits : unsigned(19 downto 0) := x"00003";
------------------------------------------------------------------------------
-- Types
......@@ -389,9 +356,6 @@ package vme64x_pack is
type t_FUNC_256b_array is
array (0 to 7) of unsigned(255 downto 0); -- XAMCAP register array
type t_csr_array is
array(BAR downto WB32bits) of unsigned(7 downto 0);
type t_cr_array is
array (natural range <>) of std_logic_vector(7 downto 0);
......@@ -399,10 +363,6 @@ package vme64x_pack is
-- Functions
------------------------------------------------------------------------------
function f_log2_size (
A : natural
) return natural;
function f_latchDS (
clk_period : integer
) return integer;
......@@ -554,8 +514,17 @@ package vme64x_pack is
ACK_i : in std_logic;
WE_o : out std_logic;
STALL_i : in std_logic;
INT_ack_o : out std_logic;
IRQ_i : in std_logic
endian_i : in std_logic_vector(2 downto 0);
user_csr_addr_o : out std_logic_vector(18 downto 2);
user_csr_data_i : in std_logic_vector( 7 downto 0);
user_csr_data_o : out std_logic_vector( 7 downto 0);
user_csr_we_o : out std_logic;
user_cr_addr_o : out std_logic_vector(18 downto 2);
user_cr_data_i : in std_logic_vector( 7 downto 0);
irq_ack_o : out std_logic;
irq_i : in std_logic;
irq_level_i : in std_logic_vector(7 downto 0);
irq_vector_i : in std_logic_vector(7 downto 0)
);
end component;
......@@ -597,65 +566,57 @@ package vme64x_pack is
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
rst_n_i : in std_logic;
reset_o : out std_logic;
VME_RST_n_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_LWORD_n_o : out std_logic;
VME_LWORD_n_i : in std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_WRITE_n_i : in std_logic;
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_DS_ant_n_i : in std_logic_vector(1 downto 0);
VME_ADDR_i : in std_logic_vector(31 downto 1);
VME_DATA_i : in std_logic_vector(31 downto 0);
VME_AM_i : in std_logic_vector(5 downto 0);
VME_IACK_n_i : in std_logic;
memAckWB_i : in std_logic;
wbData_i : in std_logic_vector(g_wb_data_width-1 downto 0);
err_i : in std_logic;
rty_i : in std_logic;
stall_i : in std_logic;
CRAMdata_i : in std_logic_vector(7 downto 0);
CRdata_i : in std_logic_vector(7 downto 0);
CSRData_i : in std_logic_vector(7 downto 0);
reset_flag_i : in std_logic;
Ader0 : in std_logic_vector(31 downto 0);
Ader1 : in std_logic_vector(31 downto 0);
Ader2 : in std_logic_vector(31 downto 0);
Ader3 : in std_logic_vector(31 downto 0);
Ader4 : in std_logic_vector(31 downto 0);
Ader5 : in std_logic_vector(31 downto 0);
Ader6 : in std_logic_vector(31 downto 0);
Ader7 : in std_logic_vector(31 downto 0);
ModuleEnable : in std_logic;
Endian_i : in std_logic_vector(2 downto 0);
Sw_Reset : in std_logic;
BAR_i : in std_logic_vector(4 downto 0);
reset_o : out std_logic;
VME_LWORD_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_BERR_o : out std_logic;
VME_BERR_n_o : out std_logic;
VME_ADDR_i : in std_logic_vector(31 downto 1);
VME_ADDR_o : out std_logic_vector(31 downto 1);
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
VME_DATA_i : in std_logic_vector(31 downto 0);
VME_DATA_o : out std_logic_vector(31 downto 0);
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
memReq_o : out std_logic;
wbData_o : out std_logic_vector(g_wb_data_width-1 downto 0);
locAddr_o : out std_logic_vector(g_wb_addr_width-1 downto 0);
wbSel_o : out std_logic_vector(g_wb_data_width/8-1 downto 0);
RW_o : out std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_IACK_n_i : in std_logic;
stb_o : out std_logic;
ack_i : in std_logic;
dat_o : out std_logic_vector(g_wb_data_width-1 downto 0);
dat_i : in std_logic_vector(g_wb_data_width-1 downto 0);
adr_o : out std_logic_vector(g_wb_addr_width-1 downto 0);
sel_o : out std_logic_vector(g_wb_data_width/8-1 downto 0);
we_o : out std_logic;
cyc_o : out std_logic;
CRAMaddr_o : out std_logic_vector(f_log2_size(f_size(g_beg_cram, g_end_cram))-1 downto 0);
CRAMdata_o : out std_logic_vector(7 downto 0);
CRAMwea_o : out std_logic;
CRaddr_o : out std_logic_vector(11 downto 0);
en_wr_CSR : out std_logic;
CrCsrOffsetAddr : out std_logic_vector(18 downto 0);
CSRData_o : out std_logic_vector(7 downto 0);
err_flag_o : out std_logic
err_i : in std_logic;
rty_i : in std_logic;
stall_i : in std_logic;
cr_csr_addr_o : out std_logic_vector(18 downto 2);
cr_csr_data_i : in std_logic_vector( 7 downto 0);
cr_csr_data_o : out std_logic_vector( 7 downto 0);
cr_csr_we_o : out std_logic;
ader0_i : in std_logic_vector(31 downto 0);
ader1_i : in std_logic_vector(31 downto 0);
ader2_i : in std_logic_vector(31 downto 0);
ader3_i : in std_logic_vector(31 downto 0);
ader4_i : in std_logic_vector(31 downto 0);
ader5_i : in std_logic_vector(31 downto 0);
ader6_i : in std_logic_vector(31 downto 0);
ader7_i : in std_logic_vector(31 downto 0);
endian_i : in std_logic_vector(2 downto 0);
module_enable_i : in std_logic;
module_reset_i : in std_logic;
bar_i : in std_logic_vector(4 downto 0)
);
end component VME_bus;
......@@ -742,42 +703,42 @@ package vme64x_pack is
component VME_CR_CSR_Space is
generic (
g_cram_size : integer;
g_wb_data_width : integer;
g_cr_space : t_cr_array
g_beg_user_cr : std_logic_vector(23 downto 0);
g_end_user_cr : std_logic_vector(23 downto 0);
g_beg_cram : std_logic_vector(23 downto 0);
g_end_cram : std_logic_vector(23 downto 0);
g_beg_user_csr : std_logic_vector(23 downto 0);
g_end_user_csr : std_logic_vector(23 downto 0);
g_cr_space : t_cr_array
);
port (
clk_i : in std_logic;
reset : in std_logic;
CR_addr : in std_logic_vector(11 downto 0);
CRAM_addr : in std_logic_vector(f_log2_size(g_cram_size)-1 downto 0);
CRAM_data_i : in std_logic_vector(7 downto 0);
CRAM_Wen : in std_logic;
en_wr_CSR : in std_logic;
CrCsrOffsetAddr : in std_logic_vector(18 downto 0);
VME_GA_oversampled : in std_logic_vector(5 downto 0);
locDataIn : in std_logic_vector(7 downto 0);
CR_data : out std_logic_vector(7 downto 0);
err_flag : in std_logic;
CRAM_data_o : out std_logic_vector(7 downto 0);
reset_flag : out std_logic;
CSRdata : out std_logic_vector(7 downto 0);
Ader0 : out std_logic_vector(31 downto 0);
Ader1 : out std_logic_vector(31 downto 0);
Ader2 : out std_logic_vector(31 downto 0);
Ader3 : out std_logic_vector(31 downto 0);
Ader4 : out std_logic_vector(31 downto 0);
Ader5 : out std_logic_vector(31 downto 0);
Ader6 : out std_logic_vector(31 downto 0);
Ader7 : out std_logic_vector(31 downto 0);
ModuleEnable : out std_logic;
Sw_Reset : out std_logic;
numBytes : in std_logic_vector(12 downto 0);
transfTime : in std_logic_vector(39 downto 0);
Endian_o : out std_logic_vector(2 downto 0);
BAR_o : out std_logic_vector(4 downto 0);
INT_Level : out std_logic_vector(7 downto 0);
INT_Vector : out std_logic_vector(7 downto 0)
clk_i : in std_logic;
reset_i : in std_logic;
vme_ga_i : in std_logic_vector(5 downto 0);
vme_berr_n_i : in std_logic;
bar_o : out std_logic_vector(4 downto 0);
vme_sysfail_i : in std_logic;
vme_sysfail_ena_o : out std_logic;
module_enable_o : out std_logic;
module_reset_o : out std_logic;
addr_i : in std_logic_vector(18 downto 2);
data_i : in std_logic_vector( 7 downto 0);
data_o : out std_logic_vector( 7 downto 0);
we_i : in std_logic;
user_csr_addr_o : out std_logic_vector(18 downto 2);
user_csr_data_i : in std_logic_vector( 7 downto 0);
user_csr_data_o : out std_logic_vector( 7 downto 0);
user_csr_we_o : out std_logic;
user_cr_addr_o : out std_logic_vector(18 downto 2);
user_cr_data_i : in std_logic_vector( 7 downto 0);
ader0_o : out std_logic_vector(31 downto 0);
ader1_o : out std_logic_vector(31 downto 0);
ader2_o : out std_logic_vector(31 downto 0);
ader3_o : out std_logic_vector(31 downto 0);
ader4_o : out std_logic_vector(31 downto 0);
ader5_o : out std_logic_vector(31 downto 0);
ader6_o : out std_logic_vector(31 downto 0);
ader7_o : out std_logic_vector(31 downto 0)
);
end component VME_CR_CSR_Space;
......@@ -818,6 +779,25 @@ package vme64x_pack is
);
end component VME_Am_Match;
component VME_User_CSR is
generic (
g_wb_data_width : integer
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
addr_i : in std_logic_vector(18 downto 2);
data_i : in std_logic_vector( 7 downto 0);
data_o : out std_logic_vector( 7 downto 0);
we_i : in std_logic;
irq_vector_o : out std_logic_vector( 7 downto 0);
irq_level_o : out std_logic_vector( 7 downto 0);
endian_o : out std_logic_vector( 2 downto 0);
bytes_i : in std_logic_vector(15 downto 0);
time_i : in std_logic_vector(39 downto 0)
);
end component VME_User_CSR;
component VME_Wb_master is
generic (
g_wb_data_width : integer;
......@@ -884,15 +864,15 @@ package vme64x_pack is
component VME_CRAM is
generic (
dl : integer;
al : integer
g_beg_cram : std_logic_vector(23 downto 0);
g_end_cram : std_logic_vector(23 downto 0)
);
port (
clk : in std_logic;
we : in std_logic;
aw : in std_logic_vector(al-1 downto 0);
di : in std_logic_vector(dl-1 downto 0);
dw : out std_logic_vector(dl-1 downto 0)
clk_i : in std_logic;
we_i : in std_logic;
addr_i : in std_logic_vector(18 downto 2);
data_i : in std_logic_vector( 7 downto 0);
data_o : out std_logic_vector( 7 downto 0)
);
end component VME_CRAM;
......@@ -900,16 +880,6 @@ end vme64x_pack;
package body vme64x_pack is
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
function f_latchDS (clk_period : integer) return integer is
begin
for I in 1 to 4 loop
......
hdl/vme64x-core/rtl/xvme64x_core.vhd
View file @ 62b13b5e
......@@ -39,7 +39,7 @@ entity xvme64x_core is
generic (
g_clock_period : integer := c_clk_period;
g_wb_data_width : integer := c_wishbone_data_width;
g_wb_addr_width : integer := c_wishbone_addr_width;
g_wb_addr_width : integer := c_wishbone_address_width;
-- CR/CSR
g_manufacturer_id : std_logic_vector(23 downto 0) := c_cern_id;
......@@ -52,11 +52,11 @@ entity xvme64x_core is
g_beg_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_end_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_beg_cram : std_logic_vector(23 downto 0) := x"001000";
g_beg_cram : std_logic_vector(23 downto 0) := x"001003";
g_end_cram : std_logic_vector(23 downto 0) := x"0013ff";
g_beg_user_csr : std_logic_vector(23 downto 0) := x"000000";
g_end_user_csr : std_logic_vector(23 downto 0) := x"000000";
g_beg_user_csr : std_logic_vector(23 downto 0) := x"07ff33";
g_end_user_csr : std_logic_vector(23 downto 0) := x"07ff5f";
g_beg_sn : std_logic_vector(23 downto 0) := x"000000";
g_end_sn : std_logic_vector(23 downto 0) := x"000000";
......@@ -142,11 +142,22 @@ end xvme64x_core;
architecture wrapper of xvme64x_core is
signal dat_out, dat_in : std_logic_vector(31 downto 0);
signal adr_out : std_logic_vector(63 downto 0);
signal dat_out,
dat_in : std_logic_vector(31 downto 0);
signal adr_out : std_logic_vector(31 downto 0);
signal irq_vector,
irq_level : std_logic_vector( 7 downto 0);
signal endian : std_logic_vector( 2 downto 0);
signal user_csr_addr : std_logic_vector(18 downto 2);
signal user_csr_data_i,
user_csr_data_o : std_logic_vector( 7 downto 0);
signal user_csr_we : std_logic;
signal rst : std_logic;
begin -- wrapper
rst <= not rst_n_i;
U_Wrapped_VME : VME64xCore_Top
generic map (
g_clock => g_clock_period,
......@@ -227,19 +238,31 @@ begin -- wrapper
VME_ADDR_DIR_o => VME_ADDR_DIR_o,
VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
DAT_i => dat_in,
DAT_o => dat_out,
ADR_o => adr_out,
CYC_o => master_o.cyc,
ERR_i => master_i.err,
RTY_i => master_i.rty,
SEL_o => open,
STB_o => master_o.stb,
ACK_i => master_i.ack,
WE_o => master_o.we,
STALL_i => master_i.stall,
IRQ_i => irq_i,
INT_ack_o => irq_ack_o
DAT_i => dat_in,
DAT_o => dat_out,
ADR_o => adr_out,
CYC_o => master_o.cyc,
ERR_i => master_i.err,
RTY_i => master_i.rty,
SEL_o => open,
STB_o => master_o.stb,
ACK_i => master_i.ack,
WE_o => master_o.we,
STALL_i => master_i.stall,
endian_i => endian,
user_csr_addr_o => user_csr_addr,
user_csr_data_i => user_csr_data_o,
user_csr_data_o => user_csr_data_i,
user_csr_we_o => user_csr_we,
user_cr_addr_o => open,
user_cr_data_i => x"00",
irq_i => irq_i,
irq_ack_o => irq_ack_o,
irq_vector_i => irq_vector,
irq_level_i => irq_level
);
master_o.dat <= dat_out(31 downto 0);
......@@ -247,6 +270,22 @@ begin -- wrapper
master_o.adr <= adr_out(29 downto 0) & "00";
dat_in <= master_i.dat;
-- VME_IRQ_n_o <= (others => '0');
U_User_CSR : VME_User_CSR
generic map (
g_wb_data_width => g_wb_data_width
)
port map (
clk_i => clk_i,
reset_i => rst,
addr_i => user_csr_addr,
data_i => user_csr_data_i,
data_o => user_csr_data_o,
we_i => user_csr_we,
irq_vector_o => irq_vector,
irq_level_o => irq_level,
endian_o => endian,
time_i => x"0000000000",
bytes_i => x"0000"
);
end wrapper;
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