vme_bus: simulation is OK.

60f29f5d · Tristan Gingold · a006c850 · 60f29f5d
Commit 60f29f5d authored Jan 23, 2020 by Tristan Gingold
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Showing with 20 additions and 7 deletions

vme_bus.vhd hdl/rtl/vme_bus.vhd +20 -7

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--- a/hdl/rtl/vme_bus.vhd
+++ b/hdl/rtl/vme_bus.vhd
@@ -655,8 +655,7 @@ begin
                and irq_pending_i = '1'
              then
                -- That's for us
-                vme_odff_data <= (others => '0');
-                vme_odff_data (7 downto 0) <= int_vector_i;
+                s_wb_start <= '1';
                s_irq_sel <= '1';
                irq_ack_o <= '1';

@@ -812,9 +811,13 @@ begin
                  data_reg (31 downto 1) <= vme_idff_addr;
                  data_reg (63 downto 32) <= vme_idff_data;
                else
-                  data_reg (31 downto 0) <= vme_idff_data;
-                  data_reg (32) <= vme_idff_lword_n;
-                  data_reg (63 downto 33) <= vme_idff_addr;
+                  if addr_reg(0) = '0' then
+                    --  32bit access
+                    data_reg (31 downto 0) <= vme_idff_data;
+                  else
+                    data_reg (15 downto  0) <= vme_idff_data (15 downto 0);
+                    data_reg (31 downto 16) <= vme_idff_data (15 downto 0);
+                  end if;
                end if;
              end if;

@@ -845,7 +848,17 @@ begin
              s_err <= '0';
              if s_card_sel = '1' then
                s_WBFSMstate <= MEMORY_REQ;
-              else
+              elsif s_conf_sel = '1' then
+                if vme_idff_write_n = '1' then
+                  --  Read the data
+                  data_reg(7 downto 0) <= cr_csr_data_i;
+                end if;
+
+                s_wb_done <= '1';
+                s_WBFSMstate <= IDLE;
+              elsif s_irq_sel = '1' then
+                data_reg (7 downto 0) <= int_vector_i;
+
                s_wb_done <= '1';
                s_WBFSMstate <= IDLE;
              end if;
@@ -910,7 +923,7 @@ begin
                data_reg(63 downto 32) <= data_reg(31 downto 0);
                data_reg(31 downto 0) <= (others => '0');
                if s_card_sel = '1' then
-                  if g_VME32 and vme_odff_lword_n = '1' and addr_reg(1) = '0'
+                  if g_VME32 and addr_reg(0) = '1' and addr_reg(1) = '0'
                  then
                    -- Word/byte access with A1 = 0 on a 32bit bus.
                    data_reg(15 downto 0) <= wb_dat_i(31 downto 16);