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VME64x core
Commit 5f7e38e7 authored by Tristan Gingold's avatar Tristan Gingold
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Fix style.

parent 19318a70
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Showing with 46 additions and 46 deletions
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @ 5f7e38e7
......@@ -236,7 +236,7 @@ entity VME64xCore_Top is
ADR_o : out std_logic_vector(g_WB_ADDR_WIDTH-1 downto 0);
CYC_o : out std_logic;
ERR_i : in std_logic;
SEL_o : out std_logic_vector(g_WB_DATA_WIDTH/8-1 downto 0);
SEL_o : out std_logic_vector(g_WB_DATA_WIDTH / 8 - 1 downto 0);
STB_o : out std_logic;
ACK_i : in std_logic;
WE_o : out std_logic;
......@@ -361,18 +361,18 @@ begin
process (clk_i)
begin
if rising_edge(clk_i) then
s_VME_RST_n <= VME_RST_n_i
& s_VME_RST_n(nbr_stages - 1 downto 1);
s_VME_AS_n <= VME_AS_n_i
& s_VME_AS_n(nbr_stages - 1 downto 1);
s_VME_WRITE_n <= VME_WRITE_n_i
& s_VME_WRITE_n(nbr_stages - 1 downto 1);
s_VME_DS_n <= VME_DS_n_i
& s_VME_DS_n(2 * nbr_stages - 1 downto 2);
s_VME_IACK_n <= VME_IACK_n_i
& s_VME_IACK_n(nbr_stages - 1 downto 1);
s_VME_IACKIN_n <= VME_IACKIN_n_i
& s_VME_IACKIN_n(nbr_stages - 1 downto 1);
s_VME_RST_n <= VME_RST_n_i
& s_VME_RST_n(nbr_stages - 1 downto 1);
s_VME_AS_n <= VME_AS_n_i
& s_VME_AS_n(nbr_stages - 1 downto 1);
s_VME_WRITE_n <= VME_WRITE_n_i
& s_VME_WRITE_n(nbr_stages - 1 downto 1);
s_VME_DS_n <= VME_DS_n_i
& s_VME_DS_n(2 * nbr_stages - 1 downto 2);
s_VME_IACK_n <= VME_IACK_n_i
& s_VME_IACK_n(nbr_stages - 1 downto 1);
s_VME_IACKIN_n <= VME_IACKIN_n_i
& s_VME_IACKIN_n(nbr_stages - 1 downto 1);
end if;
end process;
......@@ -483,7 +483,7 @@ begin
------------------------------------------------------------------------------
Inst_VME_IRQ_Controller : entity work.VME_IRQ_Controller
generic map (
g_RETRY_TIMEOUT => 1000000/g_CLOCK_PERIOD -- 1ms timeout
g_RETRY_TIMEOUT => 1000000 / g_CLOCK_PERIOD -- 1ms timeout
)
port map (
clk_i => clk_i,
......
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
View file @ 5f7e38e7
......@@ -208,10 +208,10 @@ architecture rtl of VME_CR_CSR_Space is
-- Addresses
subtype crcsr_addr is unsigned(18 downto 2);
constant c_BEG_CR : crcsr_addr := to_unsigned(16#00000#/4, 17);
constant c_END_CR : crcsr_addr := to_unsigned(16#00fff#/4, 17);
constant c_BEG_CSR : crcsr_addr := to_unsigned(16#7ff60#/4, 17);
constant c_END_CSR : crcsr_addr := to_unsigned(16#7ffff#/4, 17);
constant c_BEG_CR : crcsr_addr := to_unsigned(16#00000# / 4, 17);
constant c_END_CR : crcsr_addr := to_unsigned(16#00fff# / 4, 17);
constant c_BEG_CSR : crcsr_addr := to_unsigned(16#7ff60# / 4, 17);
constant c_END_CSR : crcsr_addr := to_unsigned(16#7ffff# / 4, 17);
constant c_BEG_USER_CR : crcsr_addr := unsigned(g_BEG_USER_CR(18 downto 2));
constant c_END_USER_CR : crcsr_addr := unsigned(g_END_USER_CR(18 downto 2));
constant c_BEG_USER_CSR : crcsr_addr := unsigned(g_BEG_USER_CSR(18 downto 2));
......@@ -219,14 +219,14 @@ architecture rtl of VME_CR_CSR_Space is
constant c_BEG_CRAM : crcsr_addr := unsigned(g_BEG_CRAM(18 downto 2));
constant c_END_CRAM : crcsr_addr := unsigned(g_END_CRAM(18 downto 2));
constant c_BAR_REG : integer := 16#7ffff#/4;
constant c_BIT_SET_REG : integer := 16#7fffb#/4;
constant c_BIT_CLR_REG : integer := 16#7fff7#/4;
constant c_CRAM_OWNER_REG : integer := 16#7fff3#/4;
constant c_USR_SET_REG : integer := 16#7ffef#/4;
constant c_USR_CLR_REG : integer := 16#7ffeb#/4;
constant c_ADER_REG_END : integer := 16#7ffdf#/4;
constant c_ADER_REG_BEG : integer := 16#7ff63#/4;
constant c_BAR_REG : integer := 16#7ffff# / 4;
constant c_BIT_SET_REG : integer := 16#7fffb# / 4;
constant c_BIT_CLR_REG : integer := 16#7fff7# / 4;
constant c_CRAM_OWNER_REG : integer := 16#7fff3# / 4;
constant c_USR_SET_REG : integer := 16#7ffef# / 4;
constant c_USR_CLR_REG : integer := 16#7ffeb# / 4;
constant c_ADER_REG_END : integer := 16#7ffdf# / 4;
constant c_ADER_REG_BEG : integer := 16#7ff63# / 4;
-- Indexes in bit set/clr register
constant c_RESET_BIT : integer := 7;
......@@ -246,10 +246,10 @@ architecture rtl of VME_CR_CSR_Space is
-- Function to generate a CR sub-array from a std_logic_vector
function f_cr_vec (v : std_logic_vector) return t_cr_array is
variable a : t_cr_array(0 to v'length/8-1);
variable a : t_cr_array(0 to v'length / 8 - 1);
begin
for i in 0 to a'length-1 loop
a(i) := v(v'length-(i*8)-1 downto v'length-(i*8)-8);
a(i) := v(v'length - (i*8) - 1 downto v'length - (i*8) - 8);
end loop;
return a;
end function;
......@@ -283,9 +283,9 @@ architecture rtl of VME_CR_CSR_Space is
cr(16#03d#) := x"0e"; -- Interrupt cap
cr(16#03f#) := x"81"; -- CRAM DAW
for i in 0 to 7 loop
cr(16#040#+i) := g_DAWPR(i); -- DAWPR
cr(16#048#+i*8 to 16#04f#+i*8) := f_cr_vec(g_AMCAP(i)); -- AMCAP
cr(16#188#+i*4 to 16#18b#+i*4) := f_cr_vec(g_ADEM(i)); -- ADEM
cr(16#040# + i) := g_DAWPR(i); -- DAWPR
cr(16#048# + i*8 to 16#04f# + i*8) := f_cr_vec(g_AMCAP(i)); -- AMCAP
cr(16#188# + i*4 to 16#18b# + i*4) := f_cr_vec(g_ADEM(i)); -- ADEM
end loop;
for i in cr'range loop
crc := crc + unsigned(cr(i));
......@@ -341,7 +341,7 @@ begin
begin
if g_ADEM (Idx) /= x"0000_0000" then
v_byte := 3 - to_integer(s_addr(3 downto 2));
s_reg_ader(Idx)(8*v_byte+7 downto 8*v_byte) <= data_i;
s_reg_ader(Idx)(8*v_byte + 7 downto 8*v_byte) <= data_i;
end if;
end Set_ADER;
......@@ -465,7 +465,7 @@ begin
v_byte := 3 - to_integer(s_addr(3 downto 2));
ader := s_reg_ader(Idx)
and ((g_ADEM(Idx) and c_ADEM_MASK) or c_ADER_MASK);
s_csr_data <= ader(8*v_byte+7 downto 8*v_byte);
s_csr_data <= ader(8*v_byte + 7 downto 8*v_byte);
end if;
end Get_ADER;
......
hdl/vme64x-core/rtl/VME_User_CSR.vhd
View file @ 5f7e38e7
......@@ -85,17 +85,17 @@ architecture rtl of VME_User_CSR is
constant c_UNUSED : std_logic_vector(7 downto 0) := x"ff";
-- Addresses
constant c_IRQ_VECTOR : integer := 16#0002f#/4;
constant c_IRQ_LEVEL : integer := 16#0002b#/4;
constant c_ENDIAN : integer := 16#00023#/4;
constant c_TIME0_NS : integer := 16#0001f#/4;
constant c_TIME1_NS : integer := 16#0001b#/4;
constant c_TIME2_NS : integer := 16#00017#/4;
constant c_TIME3_NS : integer := 16#00013#/4;
constant c_TIME4_NS : integer := 16#0000f#/4;
constant c_BYTES0 : integer := 16#0000b#/4;
constant c_BYTES1 : integer := 16#00007#/4;
constant c_WB32BITS : integer := 16#00003#/4;
constant c_IRQ_VECTOR : integer := 16#0002f# / 4;
constant c_IRQ_LEVEL : integer := 16#0002b# / 4;
constant c_ENDIAN : integer := 16#00023# / 4;
constant c_TIME0_NS : integer := 16#0001f# / 4;
constant c_TIME1_NS : integer := 16#0001b# / 4;
constant c_TIME2_NS : integer := 16#00017# / 4;
constant c_TIME3_NS : integer := 16#00013# / 4;
constant c_TIME4_NS : integer := 16#0000f# / 4;
constant c_BYTES0 : integer := 16#0000b# / 4;
constant c_BYTES1 : integer := 16#00007# / 4;
constant c_WB32BITS : integer := 16#00003# / 4;
begin
-- Write
......
hdl/vme64x-core/rtl/VME_bus.vhd
View file @ 5f7e38e7
......@@ -121,7 +121,7 @@ entity VME_bus is
am_o : out std_logic_vector( 5 downto 0);
decode_sel_i : in std_logic;
--CR/CSR space signals:
-- CR/CSR space signals:
cr_csr_addr_o : out std_logic_vector(18 downto 2);
cr_csr_data_i : in std_logic_vector( 7 downto 0);
cr_csr_data_o : out std_logic_vector( 7 downto 0);
......
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @ 5f7e38e7
......@@ -202,7 +202,7 @@ package vme64x_pack is
ADR_o : out std_logic_vector(g_WB_ADDR_WIDTH-1 downto 0);
CYC_o : out std_logic;
ERR_i : in std_logic;
SEL_o : out std_logic_vector(g_WB_DATA_WIDTH/8-1 downto 0);
SEL_o : out std_logic_vector(g_WB_DATA_WIDTH / 8 - 1 downto 0);
STB_o : out std_logic;
ACK_i : in std_logic;
WE_o : out std_logic;
......
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