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VME64x core
Commit 593dbebd authored by Tristan Gingold's avatar Tristan Gingold
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vme_irq_controller: rename reset_n_i to rst_n_i

parent 0343da4d
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doc/review-2017-11-13/GD-vme64x-core-review.txt
View file @ 593dbebd
......@@ -118,4 +118,4 @@
----------------------------
- general-cores submodule in wrong location. Move it from hdl/sim to
ip_cores/general-cores like we have for all the other repos.
Cf Maciej.
Done. Cf Maciej.
hdl/rtl/vme_irq_controller.vhd
View file @ 593dbebd
......@@ -133,7 +133,7 @@ entity vme_irq_controller is
);
port (
clk_i : in std_logic;
reset_n_i : in std_logic;
rst_n_i : in std_logic;
INT_Level_i : in std_logic_vector (2 downto 0);
INT_Req_i : in std_logic;
irq_pending_o : out std_logic;
......@@ -159,7 +159,7 @@ begin
p_retry_fsm : process (clk_i)
begin
if rising_edge(clk_i) then
if reset_n_i = '0' then
if rst_n_i = '0' then
retry_mask <= '1';
retry_state <= WAIT_IRQ;
else
......@@ -190,7 +190,7 @@ begin
p_main_fsm : process (clk_i)
begin
if rising_edge(clk_i) then
if reset_n_i = '0' then
if rst_n_i = '0' then
VME_IRQ_n_o <= (others => '1');
s_irq_pending <= '0';
else
......
hdl/rtl/xvme64x_core.vhd
View file @ 593dbebd
......@@ -431,7 +431,7 @@ begin
)
port map (
clk_i => clk_i,
reset_n_i => s_reset_n, -- asserted when low
rst_n_i => s_reset_n, -- asserted when low
INT_Level_i => s_irq_level,
INT_Req_i => wb_i.int,
irq_pending_o => s_irq_pending,
......
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