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VME64x core
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VME64x core
Commits
55e08827
Commit
55e08827
authored
Aug 05, 2020
by
Tom Levens
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Fix wrong end entity name
parent
f85c29db
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vme64x_core_verilog.vhd
hdl/rtl/vme64x_core_verilog.vhd
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hdl/rtl/vme64x_core_verilog.vhd
View file @
55e08827
...
@@ -100,7 +100,7 @@ entity vme64x_core_verilog is
...
@@ -100,7 +100,7 @@ entity vme64x_core_verilog is
return
BYTE
;
return
BYTE
;
end
if
;
end
if
;
end
string_to_wb_grn
;
end
string_to_wb_grn
;
end
vme64x_core_
wrap
;
end
vme64x_core_
verilog
;
architecture
wrapper
of
vme64x_core_verilog
is
architecture
wrapper
of
vme64x_core_verilog
is
begin
begin
...
...
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