First thoughts on the top-level module.

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@176 665b4545-5c6b-4c24-801b-41150b02b44b

First thoughts on the top-level module.
git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@176 665b4545-5c6b-4c24-801b-41150b02b44b
497d1b9d · serrano · bbe3b7f0 · 497d1b9d
Commit 497d1b9d authored Nov 02, 2012 by serrano
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javier.txt hdl/vme64x-core/rtl/CodeReview_2Nov2012/javier.txt +20 -0

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--- a/hdl/vme64x-core/rtl/CodeReview_2Nov2012/javier.txt
+++ b/hdl/vme64x-core/rtl/CodeReview_2Nov2012/javier.txt
+VME64xCore_Top.vhd
+------------------
+
+In the comments, it would be useful to explain a bit about the context
+this core expects in the PCB, e.g. what chips are used in the SVEC
+board (which is the reference platform for this core). This would help
+people understand e.g. how open collector outputs are dealt with, or
+what the VME_LWORD_n_o and VME_ADDR_o outputs are for.
+
+VME_AS_n_i and VME_DS_n_i are passed to two different synchronizer
+blocks in parallel. The actual implementation of this will depend on
+how clever the synthesis tool is. If it is not clever, it will not
+notice it can tap the three-FF synchronizer to get the double-FF
+output, and we will have two parallel synchronizers: not good,
+especially considering that one of them will not use the I/O FFs. If
+these double-clocked signals are really needed, the triple-clocking
+block could deliver an extra ouput port for them. 
+
+
+
 TODO:
 - Check iack_in -> iack_out part.
 - Make sure no interrupts can be missed.