Add support for d16 BLT

46f43275 · Tristan Gingold · 835a5c06 · 46f43275 · 46f43275 · 46f43275
Commit 46f43275 authored Feb 05, 2021 by Tristan Gingold
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Showing with 41 additions and 19 deletions

vme_bus.vhd hdl/rtl/vme_bus.vhd +31 -8

top_tb.vhd hdl/testbench/simple_tb/top_tb.vhd +9 -11

run.sh hdl/testbench/vme16/ghdl/run.sh +1 -0

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--- a/hdl/rtl/vme_bus.vhd
+++ b/hdl/rtl/vme_bus.vhd
@@ -153,6 +153,7 @@ architecture rtl of vme_bus is
  --  Register containing the address.  Initialized from VME, adjusted
  --  by address decoder, and incremented during DMA.
  signal addr_reg                  : std_logic_vector(31 downto 0);
+  signal lword_n_reg                 : std_logic;

  --  Load addr_reg from vme idff (for address phase1 and 2).
  signal load_addr_reg_phase1        : std_logic;
@@ -161,6 +162,10 @@ architecture rtl of vme_bus is
  --  Data register, owned by the WB fsm.
  signal data_reg                 : std_logic_vector(63 downto 0);

+  --  For block transfers, number of bytes by which the address is
+  --  incremented between transfers.
+  signal inc_reg : unsigned(2 downto 0);
+
  type t_transferType is (
    SINGLE,
    BLT,
@@ -913,6 +918,7 @@ begin
        wb_sel_o         <= "0000";
        wb_we_o          <= '0';
        addr_reg         <= (others => '0');
+        lword_n_reg      <= '0';

        s_err            <= '0';
        s_wb_done		     <= '0';
@@ -926,8 +932,8 @@ begin

            if load_addr_reg_phase1 = '1' then
              --  VME address phase 1.
-              addr_reg (31 downto 1) <= vme_idff_addr;
-              addr_reg (0) <= vme_idff_lword_n;
+              addr_reg <= vme_idff_addr & '0';
+              lword_n_reg <= vme_idff_lword_n;

              s_cross_boundary <= '0';

@@ -954,7 +960,8 @@ begin

            if load_addr_reg_phase2 = '1' then
              --  VME address phase 2 (for 2eVME oand 2eSST)
-              addr_reg(7 downto 0) <= vme_idff_addr (7 downto 1) & vme_idff_lword_n;
+              addr_reg (7 downto 0) <= vme_idff_addr (7 downto 1) & '0';
+              lword_n_reg <= vme_idff_lword_n;
            end if;

            if decode_done_i = '1' then
@@ -980,7 +987,7 @@ begin
                  data_reg (31 downto 1) <= vme_idff_addr;
                  data_reg (63 downto 32) <= vme_idff_data;
                else
-                  if addr_reg(0) = '0' then
+                  if lword_n_reg = '0' then
                    --  32bit access (lword is set)
                    data_reg (31 downto 0) <= vme_idff_data;
                  else
@@ -996,7 +1003,7 @@ begin
                --  16bit access on a 16bit bus.
                wb_sel_o (3 downto 2) <= "00";
                wb_sel_o (1 downto 0) <= not vme_idff_ds_n;
-              elsif addr_reg(0) = '0' or s_transferType = VME2E then
+              elsif lword_n_reg = '0' or s_transferType = VME2E then
                --  32bit access
                wb_sel_o <= "1111";
              else
@@ -1012,6 +1019,22 @@ begin
                end case;
              end if;

+              --  Compute beat size (and therefore increment) in case of block transfer.
+              if s_transferType = BLT then
+                if lword_n_reg = '0' then
+                  --  32-bit beat
+                  inc_reg <= "100";
+                elsif vme_idff_ds_n = "00" then
+                  --  16-bit beat
+                  inc_reg <= "010";
+                else
+                  --  8-bit beat
+                  inc_reg <= "001";
+                end if;
+              else
+                inc_reg <= "100";
+              end if;
+
              s_wb_dataphase <= f_to_std_logic (s_transferType = MBLT or s_transferType = VME2E);

              s_stall  <= '1';  -- Can stall
@@ -1062,8 +1085,8 @@ begin
                --    BLT must not cross any 256 byte boundary.
                --  VITA 1-1994 RULE 2.78
                --    MBLT cycles MUST not cross any 2048 byte boundary.
-                addr_reg (10 downto 2) <=
-                  std_logic_vector (unsigned(addr_reg (10 downto 2)) + 1);
+                addr_reg (10 downto 0) <=
+                  std_logic_vector (unsigned(addr_reg (10 downto 0)) + inc_reg);
                if addr_reg(7 downto 2) = b"1111_11" then
                  if s_transferType = MBLT and  addr_reg (10 downto 8) = "111" then
                    s_cross_boundary <= '1';
@@ -1099,7 +1122,7 @@ begin
                -- Mux (CS-CSR or WB)
                data_reg(63 downto 32) <= data_reg(31 downto 0);
                data_reg(31 downto 0) <= (others => '0');
-                if g_VME32 and addr_reg(0) = '1' and addr_reg(1) = '0'
+                if g_VME32 and lword_n_reg = '1' and addr_reg(1) = '0'
                then
                  -- Word/byte access with A1 = 0 on a 32bit bus.
                  data_reg(15 downto 0) <= wb_dat_i(31 downto 16);

--- a/hdl/testbench/simple_tb/top_tb.vhd
+++ b/hdl/testbench/simple_tb/top_tb.vhd
@@ -1318,17 +1318,15 @@ begin
          and  v32 (4) = x"8765_4321"
          report "incorrect BLT data 32" severity error;

-        if false then
-          --  D16 BLT not supported
-          read16_blt (x"64_00_00_14", c_AM_A32_BLT, v16 (0 to 5));
-          assert v16 (0) = x"0000"
-            and v16 (1) = x"0500"
-            and v16 (2) = x"0006"
-            and v16 (3) = x"0000"
-            and v16 (4) = x"0700"
-            and v16 (5) = x"0000"
-            report "incorrect BLT data 16" severity error;
-        end if;
+        --  D16 BLT now supported
+        read16_blt (x"64_00_00_14", c_AM_A32_BLT, v16 (0 to 5));
+        assert v16 (0) = x"0000"
+          and v16 (1) = x"0500"
+          and v16 (2) = x"0006"
+          and v16 (3) = x"0000"
+          and v16 (4) = x"0700"
+          and v16 (5) = x"0000"
+          report "incorrect BLT data 16" severity error;

        v32 (0 to 3) := (x"00_11_22_33",
                         x"44_55_66_77",

--- a/hdl/testbench/vme16/ghdl/run.sh
+++ b/hdl/testbench/vme16/ghdl/run.sh
+$GHDL -r --std=08 vme16_tb -gg_scenario=3 --assert-level=error