Commit 42f6c768 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

HDL: fixes in the verilog wrapper of the core

parent e2962d50
files = [ "vme64x_core.vhd",
"vme64x_core_verilog.vhd",
"vme64x_pkg.vhd",
"vme_bus.vhd",
"vme_cr_csr_space.vhd",
......
......@@ -23,6 +23,7 @@ entity vme64x_core_verilog is
g_VME32 : natural := 1;
g_VME_2e : natural := 0;
g_WB_GRANULARITY : string(1 to 4);
g_WB_MODE : string;
g_MANUFACTURER_ID : std_logic_vector(23 downto 0);
g_BOARD_ID : std_logic_vector(31 downto 0);
g_REVISION_ID : std_logic_vector(31 downto 0);
......@@ -131,8 +132,20 @@ entity vme64x_core_verilog is
return BYTE ;
end if;
end string_to_wb_grn ;
function string_to_wb_mode(X : string)
return t_wishbone_interface_mode is
begin
if X = "CLASSIC" then
return CLASSIC ;
end if;
if X = "PIPELINED" then
return PIPELINED ;
end if;
end string_to_wb_mode ;
end vme64x_core_verilog;
architecture wrapper of vme64x_core_verilog is
begin
inst : entity work.vme64x_core
......@@ -144,6 +157,7 @@ begin
g_VME32 => nat_to_bool(g_VME32),
g_VME_2e => nat_to_bool(g_VME_2e),
g_WB_GRANULARITY => string_to_wb_grn(g_WB_GRANULARITY),
g_WB_MODE => string_to_wb_mode(g_WB_MODE),
g_MANUFACTURER_ID => g_MANUFACTURER_ID,
g_BOARD_ID => g_BOARD_ID,
g_REVISION_ID => g_REVISION_ID,
......
......@@ -507,4 +507,42 @@ class CBusAccessor_VME64x extends CBusAccessor;
endtask // handle_irqs
endclass // CBusAccessor_VME64x
class CVME16to32Accessor extends CBusAccessor;
protected CBusAccessor_VME64x m_acc;
function new(CBusAccessor_VME64x acc_);
m_acc = acc_;
endfunction // new
virtual task automatic writem( input u64_vector_t addr, u64_vector_t data, input int size, ref int result);
endtask // writem
virtual task automatic readm( input u64_vector_t addr, ref u64_vector_t data, input int size,
ref int result);
endtask // readm
virtual task automatic read(uint64_t addr, ref uint64_t data, input int size = 4,
ref int result = _null);
uint64_t rv;
m_acc.read(addr, rv, D16Byte01 | A24 | SINGLE);
data = (rv << 16);
m_acc.read(addr + 2, rv, D16Byte23 | A24 | SINGLE);
data |= (rv & 'hffff);
endtask
virtual task automatic write(uint64_t addr, uint64_t data, int size = 4, ref int result = _null);
// $display("Write32to16 %x %x", addr, data);
m_acc.write(addr, (data >> 16), D16Byte01 | A24 | SINGLE);
m_acc.write(addr + 2, (data & 'hffff), D16Byte23 | A24 | SINGLE);
endtask
endclass // CWishboneAccessor
endpackage
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