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VME64x core
Commits
3a60c1ba
Commit
3a60c1ba
authored
Sep 22, 2017
by
Tristan Gingold
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Rescind DTACK.
parent
95591095
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13 additions
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11 deletions
+13
-11
VME_bus.vhd
hdl/vme64x-core/rtl/VME_bus.vhd
+13
-11
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hdl/vme64x-core/rtl/VME_bus.vhd
View file @
3a60c1ba
...
@@ -201,7 +201,7 @@ architecture RTL of VME_bus is
...
@@ -201,7 +201,7 @@ architecture RTL of VME_bus is
-- Main FSM signals
-- Main FSM signals
signal
s_mainFSMstate
:
t_mainFSMstates
;
signal
s_mainFSMstate
:
t_mainFSMstates
;
signal
s_
memReq
:
std_logic
;
-- Global memory request
signal
s_
conf_req
:
std_logic
;
-- Global memory request
signal
s_dataPhase
:
std_logic
;
-- for MBLT
signal
s_dataPhase
:
std_logic
;
-- for MBLT
-- Access decode signals
-- Access decode signals
...
@@ -295,7 +295,7 @@ begin
...
@@ -295,7 +295,7 @@ begin
-- FSM resetted after power up,
-- FSM resetted after power up,
-- software reset, manually reset,
-- software reset, manually reset,
-- on rising edge of AS.
-- on rising edge of AS.
s_
memReq
<=
'0'
;
s_
conf_req
<=
'0'
;
decode_start_o
<=
'0'
;
decode_start_o
<=
'0'
;
-- VME
-- VME
...
@@ -307,7 +307,7 @@ begin
...
@@ -307,7 +307,7 @@ begin
VME_ADDR_o
<=
(
others
=>
'0'
);
VME_ADDR_o
<=
(
others
=>
'0'
);
VME_LWORD_n_o
<=
'1'
;
VME_LWORD_n_o
<=
'1'
;
VME_DATA_o
<=
(
others
=>
'0'
);
VME_DATA_o
<=
(
others
=>
'0'
);
s_dataPhase
<=
'0'
;
s_dataPhase
<=
'0'
;
s_mainFSMstate
<=
IDLE
;
s_mainFSMstate
<=
IDLE
;
...
@@ -324,7 +324,7 @@ begin
...
@@ -324,7 +324,7 @@ begin
s_card_sel
<=
'0'
;
s_card_sel
<=
'0'
;
s_conf_sel
<=
'0'
;
s_conf_sel
<=
'0'
;
else
else
s_
memReq
<=
'0'
;
s_
conf_req
<=
'0'
;
decode_start_o
<=
'0'
;
decode_start_o
<=
'0'
;
VME_DTACK_OE_o
<=
'0'
;
VME_DTACK_OE_o
<=
'0'
;
VME_DTACK_n_o
<=
'1'
;
VME_DTACK_n_o
<=
'1'
;
...
@@ -416,7 +416,6 @@ begin
...
@@ -416,7 +416,6 @@ begin
when
WAIT_FOR_DS
=>
when
WAIT_FOR_DS
=>
-- wait until DS /= "11"
-- wait until DS /= "11"
VME_DTACK_OE_o
<=
'1'
;
VME_ADDR_DIR_o
<=
(
s_is_d64
)
and
VME_WRITE_n_i
;
VME_ADDR_DIR_o
<=
(
s_is_d64
)
and
VME_WRITE_n_i
;
s_dataPhase
<=
s_dataPhase
;
s_dataPhase
<=
s_dataPhase
;
...
@@ -430,7 +429,7 @@ begin
...
@@ -430,7 +429,7 @@ begin
when
LATCH_DS
=>
when
LATCH_DS
=>
-- this state is necessary indeed the VME master can assert the
-- this state is necessary indeed the VME master can assert the
-- DS lines not at the same time
-- DS lines not at the same time
VME_DTACK_OE_o
<=
'1'
;
-- VITA-1 Rule 2.53a
-- VITA-1 Rule 2.53a
-- During all read cycles [...], the responding slave MUST OT
-- During all read cycles [...], the responding slave MUST OT
-- drive the D[] lines until DSA* goes low.
-- drive the D[] lines until DSA* goes low.
...
@@ -480,14 +479,14 @@ begin
...
@@ -480,14 +479,14 @@ begin
end
if
;
end
if
;
s_mainFSMstate
<=
MEMORY_REQ
;
s_mainFSMstate
<=
MEMORY_REQ
;
s_
memReq
<=
'1'
;
s_
conf_req
<=
s_conf_sel
;
cyc_o
<=
s_card_sel
;
cyc_o
<=
s_card_sel
;
stb_o
<=
s_card_sel
;
stb_o
<=
s_card_sel
;
s_err
<=
'0'
;
s_err
<=
'0'
;
when
MEMORY_REQ
=>
when
MEMORY_REQ
=>
-- To request the memory CR/CSR or WB memory it is sufficient to
-- To request the memory CR/CSR or WB memory it is sufficient to
-- generate a pulse on s_
memR
eq signal
-- generate a pulse on s_
conf_r
eq signal
VME_DTACK_OE_o
<=
'1'
;
VME_DTACK_OE_o
<=
'1'
;
VME_DATA_DIR_o
<=
VME_WRITE_n_i
;
VME_DATA_DIR_o
<=
VME_WRITE_n_i
;
VME_ADDR_DIR_o
<=
(
s_is_d64
)
and
VME_WRITE_n_i
;
VME_ADDR_DIR_o
<=
(
s_is_d64
)
and
VME_WRITE_n_i
;
...
@@ -564,6 +563,10 @@ begin
...
@@ -564,6 +563,10 @@ begin
if
VME_DS_n_i
=
"11"
then
if
VME_DS_n_i
=
"11"
then
VME_DATA_DIR_o
<=
'0'
;
VME_DATA_DIR_o
<=
'0'
;
VME_BERR_n_o
<=
'1'
;
VME_BERR_n_o
<=
'1'
;
-- Rescind DTACK.
VME_DTACK_n_o
<=
'1'
;
case
s_transferType
is
case
s_transferType
is
when
SINGLE
=>
when
SINGLE
=>
-- Cycle should be finished, but allow another access at
-- Cycle should be finished, but allow another access at
...
@@ -632,7 +635,7 @@ begin
...
@@ -632,7 +635,7 @@ begin
adr_o
<=
"00"
&
s_ADDRlatched
(
31
downto
2
);
adr_o
<=
"00"
&
s_ADDRlatched
(
31
downto
2
);
we_o
<=
not
VME_WRITE_n_i
;
we_o
<=
not
VME_WRITE_n_i
;
dat_o
<=
s_locDataIn
(
31
downto
0
);
dat_o
<=
s_locDataIn
(
31
downto
0
);
-- Function Decoder
-- Function Decoder
addr_decoder_o
<=
s_ADDRlatched
&
'0'
;
addr_decoder_o
<=
s_ADDRlatched
&
'0'
;
am_o
<=
s_AMlatched
;
am_o
<=
s_AMlatched
;
...
@@ -641,8 +644,7 @@ begin
...
@@ -641,8 +644,7 @@ begin
cr_csr_data_o
<=
s_locDataIn
(
7
downto
0
);
cr_csr_data_o
<=
s_locDataIn
(
7
downto
0
);
cr_csr_addr_o
<=
s_ADDRlatched
(
18
downto
2
);
cr_csr_addr_o
<=
s_ADDRlatched
(
18
downto
2
);
cr_csr_we_o
<=
'1'
when
s_memReq
=
'1'
and
cr_csr_we_o
<=
'1'
when
s_conf_req
=
'1'
and
s_conf_sel
=
'1'
and
VME_WRITE_n_i
=
'0'
VME_WRITE_n_i
=
'0'
else
'0'
;
else
'0'
;
end
RTL
;
end
RTL
;
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