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VME64x core
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VME64x core
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36ef1f9b
Commit
36ef1f9b
authored
Oct 19, 2017
by
Tristan Gingold
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Minor spec update.
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173dd4e4
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VME64x_v2_specs.txt
documentation/specifications/VME64x_v2_specs.txt
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documentation/specifications/VME64x_v2_specs.txt
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36ef1f9b
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@@ -27,7 +27,7 @@ Changes
* No endianess convertion
* WB data bus is 32 bit
* Internal component declarations removed.
*
Number of sync registers (for async inputs) is configurable. Default is 2
.
*
Async inputs registered with gc_sync_register
.
VME interface
-------------
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