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VME64x core
Commit 36ef1f9b authored by Tristan Gingold's avatar Tristan Gingold
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Minor spec update.

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documentation/specifications/VME64x_v2_specs.txt
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...@@ -27,7 +27,7 @@ Changes ...@@ -27,7 +27,7 @@ Changes
* No endianess convertion * No endianess convertion
* WB data bus is 32 bit * WB data bus is 32 bit
* Internal component declarations removed. * Internal component declarations removed.
* Number of sync registers (for async inputs) is configurable. Default is 2. * Async inputs registered with gc_sync_register.
VME interface VME interface
------------- -------------
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