Commit 337d49a9 authored by Tom Levens's avatar Tom Levens

Implement all generics in verilog wrapper

parent 55e08827
......@@ -5,8 +5,7 @@
--
-- Different tools interpret verilog/vhdl parameters in different ways
-- This file is intended to use parameter types most commonly supported
-- and translate them to required VHDL values.
------------------------------------------------------------------------
......@@ -18,17 +17,49 @@ use work.vme64x_pkg.all;
entity vme64x_core_verilog is
generic (
g_CLOCK_PERIOD : natural;
g_DECODE_AM : natural;
g_ENABLE_CR_CSR : natural;
g_WB_GRANULARITY : string(1 to 4) := "BYTE";
g_DECODE_AM : natural := 1;
g_ENABLE_CR_CSR : natural := 1;
g_USER_CSR_EXT : natural := 0;
g_VME32 : natural := 1;
g_VME_2e : natural := 0;
g_WB_GRANULARITY : string(1 to 4);
g_MANUFACTURER_ID : std_logic_vector(23 downto 0);
g_BOARD_ID : std_logic_vector(31 downto 0);
g_REVISION_ID : std_logic_vector(31 downto 0);
g_PROGRAM_ID : std_logic_vector(7 downto 0);
g_ASCII_PTR : std_logic_vector(23 downto 0) := x"000000";
g_BEG_USER_CR : std_logic_vector(23 downto 0) := x"000000";
g_END_USER_CR : std_logic_vector(23 downto 0) := x"000000";
g_BEG_CRAM : std_logic_vector(23 downto 0) := x"000000";
g_END_CRAM : std_logic_vector(23 downto 0) := x"000000";
g_BEG_USER_CSR : std_logic_vector(23 downto 0) := x"07ff33";
g_END_USER_CSR : std_logic_vector(23 downto 0) := x"07ff5f";
g_BEG_SN : std_logic_vector(23 downto 0) := x"000000";
g_END_SN : std_logic_vector(23 downto 0) := x"000000";
g_DECODER_0_ADEM : std_logic_vector(31 downto 0) := x"ff000000";
g_DECODER_0_AMCAP : std_logic_vector(63 downto 0) := x"00000000_0000ff00";
g_DECODER_0_DAWPR : std_logic_vector(7 downto 0) := x"84";
g_DECODER_1_ADEM : std_logic_vector(31 downto 0) := x"fff80000";
g_DECODER_1_AMCAP : std_logic_vector(63 downto 0) := x"ff000000_00000000");
g_DECODER_1_AMCAP : std_logic_vector(63 downto 0) := x"ff000000_00000000";
g_DECODER_1_DAWPR : std_logic_vector(7 downto 0) := x"84";
g_DECODER_2_ADEM : std_logic_vector(31 downto 0) := x"00000000";
g_DECODER_2_AMCAP : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_DECODER_2_DAWPR : std_logic_vector(7 downto 0) := x"84";
g_DECODER_3_ADEM : std_logic_vector(31 downto 0) := x"00000000";
g_DECODER_3_AMCAP : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_DECODER_3_DAWPR : std_logic_vector(7 downto 0) := x"84";
g_DECODER_4_ADEM : std_logic_vector(31 downto 0) := x"00000000";
g_DECODER_4_AMCAP : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_DECODER_4_DAWPR : std_logic_vector(7 downto 0) := x"84";
g_DECODER_5_ADEM : std_logic_vector(31 downto 0) := x"00000000";
g_DECODER_5_AMCAP : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_DECODER_5_DAWPR : std_logic_vector(7 downto 0) := x"84";
g_DECODER_6_ADEM : std_logic_vector(31 downto 0) := x"00000000";
g_DECODER_6_AMCAP : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_DECODER_6_DAWPR : std_logic_vector(7 downto 0) := x"84";
g_DECODER_7_ADEM : std_logic_vector(31 downto 0) := x"00000000";
g_DECODER_7_AMCAP : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_DECODER_7_DAWPR : std_logic_vector(7 downto 0) := x"84");
port (
clk_i : std_logic;
rst_n_i : std_logic;
......@@ -109,15 +140,47 @@ begin
g_CLOCK_PERIOD => g_CLOCK_PERIOD,
g_DECODE_AM => nat_to_bool(g_DECODE_AM),
g_ENABLE_CR_CSR => nat_to_bool(g_ENABLE_CR_CSR),
g_USER_CSR_EXT => nat_to_bool(g_USER_CSR_EXT),
g_VME32 => nat_to_bool(g_VME32),
g_VME_2e => nat_to_bool(g_VME_2e),
g_WB_GRANULARITY => string_to_wb_grn(g_WB_GRANULARITY),
g_MANUFACTURER_ID => g_MANUFACTURER_ID,
g_BOARD_ID => g_BOARD_ID,
g_REVISION_ID => g_REVISION_ID,
g_PROGRAM_ID => g_PROGRAM_ID,
g_ASCII_PTR => g_ASCII_PTR,
g_BEG_USER_CR => g_BEG_USER_CR,
g_END_USER_CR => g_END_USER_CR,
g_BEG_CRAM => g_BEG_CRAM,
g_END_CRAM => g_END_CRAM,
g_BEG_USER_CSR => g_BEG_USER_CSR,
g_END_USER_CSR => g_END_USER_CSR,
g_BEG_SN => g_BEG_SN,
g_END_SN => g_END_SN,
g_DECODER_0_ADEM => g_DECODER_0_ADEM,
g_DECODER_0_AMCAP => g_DECODER_0_AMCAP,
g_DECODER_0_DAWPR => g_DECODER_0_DAWPR,
g_DECODER_1_ADEM => g_DECODER_1_ADEM,
g_DECODER_1_AMCAP => g_DECODER_1_AMCAP)
g_DECODER_1_AMCAP => g_DECODER_1_AMCAP,
g_DECODER_1_DAWPR => g_DECODER_1_DAWPR,
g_DECODER_2_ADEM => g_DECODER_2_ADEM,
g_DECODER_2_AMCAP => g_DECODER_2_AMCAP,
g_DECODER_2_DAWPR => g_DECODER_2_DAWPR,
g_DECODER_3_ADEM => g_DECODER_3_ADEM,
g_DECODER_3_AMCAP => g_DECODER_3_AMCAP,
g_DECODER_3_DAWPR => g_DECODER_3_DAWPR,
g_DECODER_4_ADEM => g_DECODER_4_ADEM,
g_DECODER_4_AMCAP => g_DECODER_4_AMCAP,
g_DECODER_4_DAWPR => g_DECODER_4_DAWPR,
g_DECODER_5_ADEM => g_DECODER_5_ADEM,
g_DECODER_5_AMCAP => g_DECODER_5_AMCAP,
g_DECODER_5_DAWPR => g_DECODER_5_DAWPR,
g_DECODER_6_ADEM => g_DECODER_6_ADEM,
g_DECODER_6_AMCAP => g_DECODER_6_AMCAP,
g_DECODER_6_DAWPR => g_DECODER_6_DAWPR,
g_DECODER_7_ADEM => g_DECODER_7_ADEM,
g_DECODER_7_AMCAP => g_DECODER_7_AMCAP,
g_DECODER_7_DAWPR => g_DECODER_7_DAWPR)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
......
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