Commit 3125363d authored by Tristan Gingold's avatar Tristan Gingold

vme_bus: address reset renaming.

parent 9174e0e7
...@@ -50,7 +50,7 @@ ...@@ -50,7 +50,7 @@
Done. Done.
- if you make VME_bus.vhd with reset active low, then you don't need s_reset - if you make VME_bus.vhd with reset active low, then you don't need s_reset
signal anymore (see also comment in VME_bus.vhd). signal anymore (see also comment in VME_bus.vhd).
OK. Done.
------------------------ ------------------------
-- VME_bus.vhd -- -- VME_bus.vhd --
...@@ -61,7 +61,7 @@ ...@@ -61,7 +61,7 @@
else than 32-bit to g_WB_ADDR_WIDTH will result in synthesis/simulation error else than 32-bit to g_WB_ADDR_WIDTH will result in synthesis/simulation error
Done. Done.
- why reset is active high (rst_i) and not active low like in all other modules? - why reset is active high (rst_i) and not active low like in all other modules?
OK. Done.
- constant num_latchDS misses "c_" prefix - constant num_latchDS misses "c_" prefix
OK. OK.
- line 431: 3 nested if-s. How about simplifying to: - line 431: 3 nested if-s. How about simplifying to:
......
...@@ -73,7 +73,7 @@ entity vme_bus is ...@@ -73,7 +73,7 @@ entity vme_bus is
); );
port ( port (
clk_i : in std_logic; clk_i : in std_logic;
rst_i : in std_logic; rst_n_i : in std_logic;
-- VME signals -- VME signals
VME_AS_n_i : in std_logic; VME_AS_n_i : in std_logic;
...@@ -295,7 +295,7 @@ begin ...@@ -295,7 +295,7 @@ begin
variable addr_word_incr : natural range 0 to 7; variable addr_word_incr : natural range 0 to 7;
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if rst_i = '1' or VME_AS_n_i = '1' then if rst_n_i = '0' or VME_AS_n_i = '1' then
-- FSM resetted after power up, -- FSM resetted after power up,
-- software reset, manually reset, -- software reset, manually reset,
-- on rising edge of AS. -- on rising edge of AS.
......
...@@ -196,7 +196,6 @@ end xvme64x_core; ...@@ -196,7 +196,6 @@ end xvme64x_core;
architecture rtl of xvme64x_core is architecture rtl of xvme64x_core is
signal s_reset : std_logic;
signal s_reset_n : std_logic; signal s_reset_n : std_logic;
signal s_VME_IRQ_n_o : std_logic_vector( 7 downto 1); signal s_VME_IRQ_n_o : std_logic_vector( 7 downto 1);
...@@ -333,7 +332,7 @@ begin ...@@ -333,7 +332,7 @@ begin
) )
port map ( port map (
clk_i => clk_i, clk_i => clk_i,
rst_i => s_reset, rst_n_i => s_reset_n,
-- VME -- VME
VME_AS_n_i => s_VME_AS_n, VME_AS_n_i => s_VME_AS_n,
...@@ -393,9 +392,8 @@ begin ...@@ -393,9 +392,8 @@ begin
irq_ack_o => s_irq_ack irq_ack_o => s_irq_ack
); );
s_reset <= (not rst_n_i) or (not s_VME_RST_n); s_reset_n <= rst_n_i and s_VME_RST_n;
s_reset_n <= not s_reset; rst_n_o <= s_reset_n and (not s_module_reset);
rst_n_o <= not (s_reset or s_module_reset);
vme_o.berr_n <= s_vme_berr_n; vme_o.berr_n <= s_vme_berr_n;
......
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