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VME64x core
Commit 29b8b02b authored by Tristan Gingold's avatar Tristan Gingold
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vme_bus: cleanup

parent 60f29f5d
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Showing with 2 additions and 106 deletions
hdl/rtl/vme_bus.vhd
View file @ 29b8b02b
......@@ -204,9 +204,6 @@ architecture rtl of vme_bus is
-- Assert DTACK
DTACK_LOW,
-- Increment address for block transfers
INCREMENT_ADDR,
-- Check if IACK is for this slave
IRQ_CHECK,
......@@ -214,13 +211,7 @@ architecture rtl of vme_bus is
IRQ_PASS,
-- Wait until AS is deasserted
WAIT_END,
-- Data2Bus during MBLT read
S1,
-- DtackLow during MBLT read
S2
WAIT_END
);
-- Main FSM signals
......@@ -264,14 +255,8 @@ architecture rtl of vme_bus is
-- Synch signals for MAIN FSM and WB FSM
signal s_wb_done : std_logic;
signal s_wb_start : std_logic;
signal s_wb_prefetch : std_logic;
signal s_wb_dataphase : std_logic;
signal s_data_on_bus : std_logic;
-- Set after address increment to enable a new prefetch.
signal s_pom : std_logic;
begin
-- These output signals are connected to the buffers on the board
-- SN74VMEH22501A Function table: (A is fpga, B is VME connector)
......@@ -347,11 +332,9 @@ begin
vme_iackout_n_o <= '1';
s_MBLT_Data <= '0';
s_mainFSMstate <= IDLE;
s_data_on_bus <= '0';
-- WB
s_wb_start <= '0';
s_wb_prefetch <= '0';
vme_idff_addr <= (others => '0');
vme_idff_am <= (others => '0');
......@@ -619,36 +602,6 @@ begin
s_mainFSMstate <= DTACK_LOW;
end if;
when INCREMENT_ADDR =>
vme_dtack_oe_o <= '1';
vme_addr_dir_o <= vme_odff_addr_dir;
s_mainFSMstate <= WAIT_FOR_DS;
if s_wb_prefetch = '1' then
s_pom <= '1';
end if;
if s_wb_prefetch = '1'
and s_transferType = MBLT
and s_WBFSMstate = IDLE
and vme_ds_n_i = "11"
and s_data_on_bus = '0'
then
-- Previous Data was read, new Data is prefetched, but a new
-- read req is not yet issued by the master
-- Already prepare data on vmebus
-- Put data to VME bus from s_wb_locDataOut
vme_addr_o <= data_reg(63 downto 33);
vme_lword_n_o <= data_reg(32);
vme_data_o <= data_reg(31 downto 0);
vme_data_dir_o <= '1';
vme_addr_dir_o <= '1';
vme_dtack_oe_o <= '1';
s_data_on_bus <= '1';
end if;
when IRQ_CHECK =>
if vme_iackin_n_i = '0' then
if vme_idff_addr(3 downto 1) = int_level_i
......@@ -678,66 +631,10 @@ begin
-- Will stay here until AS is released.
s_mainFSMstate <= WAIT_END;
when s1 =>
s_mainFSMstate <= s2;
vme_dtack_n_o <= '0';
s_wb_start <= '0';
vme_data_dir_o <= '1';
vme_addr_dir_o <= '1';
vme_dtack_oe_o <= '1';
when s2 =>
s_wb_start <= '0';
vme_data_dir_o <= '1';
vme_addr_dir_o <= '1';
vme_dtack_oe_o <= '1';
if vme_ds_n_i /= "11" then
s_mainFSMstate <= s2;
vme_dtack_n_o <= '0';
else
s_mainFSMstate <= INCREMENT_ADDR;
vme_dtack_n_o <= '1';
s_DS_latch_count <= s_DS_latch_count + 1;
end if;
if s_WBFSMstate = MEMORY_PAUSE then
s_pom <= '0';
end if;
if s_wb_prefetch = '1'
and s_transferType = MBLT
and s_WBFSMstate = IDLE
and vme_ds_n_i = "11"
and s_data_on_bus = '0'
then
-- Previous Data was read, new Data is prefetched, but a new read req is not yet issued by the master
-- Already prepare data on vmebus
-- Put data to VME bus from s_wb_locDataOut
vme_addr_o <= data_reg(63 downto 33);
vme_lword_n_o <= data_reg(32);
vme_data_o <= data_reg(31 downto 0);
vme_data_dir_o <= '1';
vme_addr_dir_o <= '1';
vme_dtack_oe_o <= '1';
s_data_on_bus <= '1';
end if;
when others =>
-- No-op, wait until AS is released.
s_mainFSMstate <= WAIT_END;
end case;
if s_WBFSMstate = MEMORY_REQ then
-- We want this state machine to drive them, but under the same condition
vme_dtack_oe_o <= '1';
vme_data_dir_o <= vme_idff_write_n;
vme_addr_dir_o <= vme_odff_addr_dir;
end if;
end if;
end if;
end process;
......@@ -791,7 +688,7 @@ begin
addr_reg (31 downto 1) <= addr_decoder_i;
end if;
if s_wb_start = '1' or s_wb_prefetch = '1' then
if s_wb_start = '1' then
-- Start WB cycle.
wb_cyc_o <= s_card_sel;
wb_stb_o <= s_card_sel;
......@@ -914,7 +811,6 @@ begin
else
s_wb_done <= '1';
s_WBFSMstate <= IDLE;
end if;
else
-- Read cycle
......
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