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VME64x core
Commits
26ae1414
Commit
26ae1414
authored
Mar 12, 2020
by
Tristan Gingold
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top_tb: add tests for prefetch on slow wb interfaces.
parent
e1f6b40e
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2 changed files
with
74 additions
and
7 deletions
+74
-7
run_all.sh
hdl/testbench/simple_tb/ghdl/run_all.sh
+1
-1
top_tb.vhd
hdl/testbench/simple_tb/top_tb.vhd
+73
-6
No files found.
hdl/testbench/simple_tb/ghdl/run_all.sh
View file @
26ae1414
...
@@ -3,7 +3,7 @@ set -e
...
@@ -3,7 +3,7 @@ set -e
GHDL
=
${
GHDL
:-
ghdl
}
GHDL
=
${
GHDL
:-
ghdl
}
for
i
in
1 2 3 4 5 6 7 8 9
;
do
for
i
in
1 2 3 4 5 6 7 8 9
11
;
do
echo
echo
echo
"Scenario
$i
"
echo
"Scenario
$i
"
$GHDL
-r
--ieee
=
synopsys top_tb
-gg_scenario
=
$i
--stop-time
=
5us
--assert-level
=
error
--ieee-asserts
=
disable-at-0 |
tee
sim.log
$GHDL
-r
--ieee
=
synopsys top_tb
-gg_scenario
=
$i
--stop-time
=
5us
--assert-level
=
error
--ieee-asserts
=
disable-at-0 |
tee
sim.log
...
...
hdl/testbench/simple_tb/top_tb.vhd
View file @
26ae1414
...
@@ -30,7 +30,7 @@
...
@@ -30,7 +30,7 @@
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
entity
top_tb
is
entity
top_tb
is
generic
(
g_SCENARIO
:
natural
range
0
to
1
0
:
=
6
);
generic
(
g_SCENARIO
:
natural
range
0
to
1
1
:
=
6
);
end
top_tb
;
end
top_tb
;
library
ieee
;
library
ieee
;
...
@@ -391,7 +391,7 @@ begin
...
@@ -391,7 +391,7 @@ begin
state
:
=
WAIT_DS
;
state
:
=
WAIT_DS
;
end
if
;
end
if
;
when
WAIT_DS
=>
when
WAIT_DS
=>
count
:
=
2
0
;
count
:
=
6
0
;
if
VME_DS_n_i
/=
"11"
then
if
VME_DS_n_i
/=
"11"
then
state
:
=
COUNTING
;
state
:
=
COUNTING
;
end
if
;
end
if
;
...
@@ -433,6 +433,8 @@ begin
...
@@ -433,6 +433,8 @@ begin
-- 0x4004 BERR
-- 0x4004 BERR
-- 0x8XXX 0x2XXX
-- 0x8XXX 0x2XXX
-- 0x8000 invalid (use to detect wrap-arounds on prefetch)
-- 0x8000 invalid (use to detect wrap-arounds on prefetch)
-- 0xcXXX 0x3XXX
-- 0-0xfff patterns with delayed ACK
wb_p
:
process
(
clk_i
)
wb_p
:
process
(
clk_i
)
constant
sram_addr_wd
:
natural
:
=
10
;
constant
sram_addr_wd
:
natural
:
=
10
;
type
sram_array
is
array
(
0
to
2
**
sram_addr_wd
-
1
)
type
sram_array
is
array
(
0
to
2
**
sram_addr_wd
-
1
)
...
@@ -449,6 +451,7 @@ begin
...
@@ -449,6 +451,7 @@ begin
others
=>
x"8765_4321"
);
others
=>
x"8765_4321"
);
variable
idx
:
natural
;
variable
idx
:
natural
;
variable
int_cnt
:
natural
;
variable
int_cnt
:
natural
;
variable
ack_cnt
:
natural
;
begin
begin
if
rising_edge
(
clk_i
)
then
if
rising_edge
(
clk_i
)
then
if
rst_n_o
=
'0'
then
if
rst_n_o
=
'0'
then
...
@@ -458,6 +461,7 @@ begin
...
@@ -458,6 +461,7 @@ begin
int_cnt
:
=
0
;
int_cnt
:
=
0
;
err_8000
<=
0
;
err_8000
<=
0
;
ack_cnt
:
=
0
;
else
else
ACK_i
<=
'0'
;
ACK_i
<=
'0'
;
ERR_i
<=
'0'
;
ERR_i
<=
'0'
;
...
@@ -505,14 +509,29 @@ begin
...
@@ -505,14 +509,29 @@ begin
ERR_i
<=
'1'
;
ERR_i
<=
'1'
;
end
if
;
end
if
;
when
"0010"
=>
when
"0010"
=>
report
hex8
(
ADR_o
);
--
report hex8(ADR_o);
if
ADR_o
(
8
downto
0
)
=
b"0_0000_0000"
then
if
ADR_o
(
8
downto
0
)
=
b"0_0000_0000"
then
err_8000
<=
err_8000
+
1
;
err_8000
<=
err_8000
+
1
;
end
if
;
end
if
;
DAT_i
<=
x"8000"
&
ADR_o
(
15
downto
0
);
DAT_i
<=
x"8000"
&
ADR_o
(
15
downto
0
);
when
"0011"
=>
DAT_i
<=
x"c000"
&
ADR_o
(
15
downto
0
);
if
ACK_i
=
'1'
then
-- Was ack'ed, waiting until cyc/stb are deasserted.
null
;
elsif
ack_cnt
=
16
then
-- End of delay (note that ACK was set)
ack_cnt
:
=
0
;
else
-- Ack is being delayed. As ACK was set, clear it.
ack_cnt
:
=
ack_cnt
+
1
;
ACK_i
<=
'0'
;
end
if
;
when
others
=>
when
others
=>
DAT_i
<=
(
others
=>
'0'
);
DAT_i
<=
(
others
=>
'0'
);
end
case
;
end
case
;
else
assert
ack_cnt
=
0
report
"cyc/stb interrupted"
severity
warning
;
end
if
;
end
if
;
end
if
;
end
if
;
end
if
;
end
if
;
...
@@ -521,7 +540,7 @@ begin
...
@@ -521,7 +540,7 @@ begin
VME_IACKIN_n_i
<=
VME_IACK_n_i
;
VME_IACKIN_n_i
<=
VME_IACK_n_i
;
tb
:
process
tb
:
process
constant
c_log
:
boolean
:
=
f
alse
;
constant
c_log
:
boolean
:
=
F
alse
;
-- Convert a CR/CSR address to the VME address: insert GA.
-- Convert a CR/CSR address to the VME address: insert GA.
-- The ADDR is on 20 bits (so the x"" notation can be used), but as
-- The ADDR is on 20 bits (so the x"" notation can be used), but as
...
@@ -655,7 +674,11 @@ begin
...
@@ -655,7 +674,11 @@ begin
if
bus_timer
=
'0'
then
if
bus_timer
=
'0'
then
res
:
=
VME_DATA_o
(
31
downto
0
);
res
:
=
VME_DATA_o
(
31
downto
0
);
else
else
if
c_log
then
write
(
output
,
" TIMEOUT!"
&
LF
);
end
if
;
res
:
=
(
others
=>
'X'
);
res
:
=
(
others
=>
'X'
);
wait
for
1
ns
;
end
if
;
end
if
;
data
:
=
res
;
data
:
=
res
;
...
@@ -1486,8 +1509,52 @@ begin
...
@@ -1486,8 +1509,52 @@ begin
and
v64
(
1
)
=
x"0006_0000_0700_0000"
and
v64
(
1
)
=
x"0006_0000_0700_0000"
report
"incorrect MBLT data 64"
severity
error
;
report
"incorrect MBLT data 64"
severity
error
;
when
11
=>
-- TODO: check IACK propagation.
-- Test MBLT prefetching
-- Set ADER
write8_conf
(
x"7_ff63"
,
x"64"
);
write8_conf
(
x"7_ff6f"
,
c_AM_A32_MBLT
&
"00"
);
write8_conf
(
x"7_ff73"
,
x"00"
);
write8_conf
(
x"7_ff77"
,
x"30"
);
write8_conf
(
x"7_ff7f"
,
c_AM_A24
&
"00"
);
-- Enable card
write8_conf
(
x"7_fffb"
,
b"0001_0000"
);
assert
err_8000
=
0
report
"no 0x8000 error expected"
severity
error
;
read64_mblt
(
x"64_00_87_e0"
,
c_AM_A32_MBLT
,
v64
(
0
to
3
));
report
"at e0: "
&
hex8
(
v64
(
0
)(
63
downto
32
));
report
"at e8: "
&
hex8
(
v64
(
0
)(
31
downto
0
));
report
"at f0: "
&
hex8
(
v64
(
1
)(
63
downto
32
));
report
"at f8: "
&
hex8
(
v64
(
1
)(
31
downto
0
));
assert
v64
(
0
to
3
)
=
(
x"80_00_21_f8_80_00_21_f9"
,
x"80_00_21_fa_80_00_21_fb"
,
x"80_00_21_fc_80_00_21_fd"
,
x"80_00_21_fe_80_00_21_ff"
)
report
"incorrect MBLT data 64"
severity
error
;
assert
err_8000
=
0
report
"no 0x8000 error expected"
severity
error
;
read64_mblt
(
x"64_00_c0_00"
,
c_AM_A32_MBLT
,
v64
(
0
to
3
));
report
"at 00: "
&
hex8
(
v64
(
0
)(
63
downto
32
));
report
"at 08: "
&
hex8
(
v64
(
0
)(
31
downto
0
));
report
"at 00: "
&
hex8
(
v64
(
1
)(
63
downto
32
));
report
"at 08: "
&
hex8
(
v64
(
1
)(
31
downto
0
));
assert
v64
(
0
to
3
)
=
(
x"c0_00_30_00_c0_00_30_01"
,
x"c0_00_30_02_c0_00_30_03"
,
x"c0_00_30_04_c0_00_30_05"
,
x"c0_00_30_06_c0_00_30_07"
)
report
"incorrect MBLT data 64"
severity
error
;
read32
(
x"00_30_c0_10"
,
c_AM_A24
,
d32
);
report
"at 10: "
&
hex8
(
d32
);
assert
d32
=
x"C000_3004"
report
"incorrect read 32"
severity
error
;
-- TODO: check IACK propagation.
end
case
;
end
case
;
wait
for
4
*
g_CLOCK_PERIOD
*
1
ns
;
wait
for
4
*
g_CLOCK_PERIOD
*
1
ns
;
...
...
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