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VME64x core
Commits
22994dc6
Commit
22994dc6
authored
Nov 24, 2017
by
Tristan Gingold
Browse files
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Plain Diff
Rework top-level generics.
parent
ebbf1287
Show whitespace changes
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Side-by-side
Showing
2 changed files
with
84 additions
and
256 deletions
+84
-256
vme64x_pkg.vhd
hdl/rtl/vme64x_pkg.vhd
+39
-41
xvme64x_core.vhd
hdl/rtl/xvme64x_core.vhd
+45
-215
No files found.
hdl/rtl/vme64x_pkg.vhd
View file @
22994dc6
...
...
@@ -43,14 +43,14 @@ package vme64x_pkg is
-- Constants
------------------------------------------------------------------------------
constant
c_CLOCK_PERIOD
:
integer
:
=
10
;
-- Clock period (ns)
constant
c_DATA_WIDTH
:
integer
:
=
32
;
-- WB data width: must be 32
constant
c_ADDR_WIDTH
:
integer
:
=
32
;
-- WB addr width: 32.
-- Manufactuer IDs.
constant
c_CERN_ID
:
std_logic_vector
(
23
downto
0
)
:
=
x"080030"
;
-- Default boards IDs
-- Boards IDs / Revision IDs.
-- For SVEC:
constant
c_SVEC_ID
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000198"
;
constant
c_
CERN_ID
:
std_logic_vector
(
23
downto
0
)
:
=
x"080030
"
;
constant
c_REVISION_ID
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000001"
;
constant
c_
SVEC_REVISION_ID
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000001
"
;
constant
c_PROGRAM_ID
:
std_logic_vector
(
7
downto
0
)
:
=
x"5a"
;
-- Bits in ADEM/ADER registers
...
...
@@ -226,15 +226,13 @@ package vme64x_pkg is
component
vme64x_core
generic
(
g_CLOCK_PERIOD
:
integer
:
=
c_CLOCK_PERIOD
;
g_WB_DATA_WIDTH
:
integer
:
=
c_DATA_WIDTH
;
g_WB_ADDR_WIDTH
:
integer
:
=
c_ADDR_WIDTH
;
g_CLOCK_PERIOD
:
integer
:
=
-1
;
g_DECODE_AM
:
boolean
:
=
true
;
g_USER_CSR_EXT
:
boolean
:
=
false
;
g_MANUFACTURER_ID
:
std_logic_vector
(
23
downto
0
)
:
=
c_CERN_ID
;
g_BOARD_ID
:
std_logic_vector
(
31
downto
0
)
:
=
c_SVEC_ID
;
g_REVISION_ID
:
std_logic_vector
(
31
downto
0
)
:
=
c_REVISION_ID
;
g_PROGRAM_ID
:
std_logic_vector
(
7
downto
0
)
:
=
c_PROGRAM_ID
;
g_MANUFACTURER_ID
:
std_logic_vector
(
23
downto
0
);
g_BOARD_ID
:
std_logic_vector
(
31
downto
0
);
g_REVISION_ID
:
std_logic_vector
(
31
downto
0
);
g_PROGRAM_ID
:
std_logic_vector
(
7
downto
0
)
:
=
c_PROGRAM_ID
;
g_ASCII_PTR
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_BEG_USER_CR
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_END_USER_CR
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
...
...
@@ -245,29 +243,29 @@ package vme64x_pkg is
g_BEG_SN
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_END_SN
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_F0_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"ff000000"
;
g_F0_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_0000ff00"
;
g_F0_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"ff000000"
;
g_F0_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_0000ff00"
;
g_F0_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F1_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"fff80000"
;
g_F1_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"ff000000_00000000"
;
g_F1_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"fff80000"
;
g_F1_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"ff000000_00000000"
;
g_F1_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F2_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F2_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F2_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F2_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F2_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F3_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F3_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F3_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F3_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F3_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F4_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F4_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F4_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F4_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F4_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F5_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F5_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F5_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F5_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F5_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F6_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F6_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F6_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F6_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F6_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F7_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F7_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F7_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F7_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F7_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
);
port
(
...
...
@@ -299,12 +297,12 @@ package vme64x_pkg is
VME_ADDR_DIR_o
:
out
std_logic
;
VME_ADDR_OE_N_o
:
out
std_logic
;
VME_RETRY_OE_o
:
out
std_logic
;
DAT_i
:
in
std_logic_vector
(
g_WB_DATA_WIDTH
-
1
downto
0
);
DAT_o
:
out
std_logic_vector
(
g_WB_DATA_WIDTH
-
1
downto
0
);
ADR_o
:
out
std_logic_vector
(
g_WB_ADDR_WIDTH
-
1
downto
0
);
DAT_i
:
in
std_logic_vector
(
3
1
downto
0
);
DAT_o
:
out
std_logic_vector
(
3
1
downto
0
);
ADR_o
:
out
std_logic_vector
(
3
1
downto
0
);
CYC_o
:
out
std_logic
;
ERR_i
:
in
std_logic
;
SEL_o
:
out
std_logic_vector
(
g_WB_DATA_WIDTH
/
8
-
1
downto
0
);
SEL_o
:
out
std_logic_vector
(
3
downto
0
);
STB_o
:
out
std_logic
;
ACK_i
:
in
std_logic
;
WE_o
:
out
std_logic
;
...
...
hdl/rtl/xvme64x_core.vhd
View file @
22994dc6
...
...
@@ -37,114 +37,49 @@ use work.vme64x_pkg.all;
entity
xvme64x_core
is
generic
(
g_CLOCK_PERIOD
:
integer
:
=
c_CLOCK_PERIOD
;
g_WB_DATA_WIDTH
:
integer
:
=
c_DATA_WIDTH
;
g_WB_ADDR_WIDTH
:
integer
:
=
c_ADDR_WIDTH
;
g_CLOCK_PERIOD
:
integer
:
=
-1
;
g_DECODE_AM
:
boolean
:
=
true
;
g_USER_CSR_EXT
:
boolean
:
=
false
;
-- CR/CSR
g_MANUFACTURER_ID
:
std_logic_vector
(
23
downto
0
)
:
=
c_CERN_ID
;
g_BOARD_ID
:
std_logic_vector
(
31
downto
0
)
:
=
c_SVEC_ID
;
g_REVISION_ID
:
std_logic_vector
(
31
downto
0
)
:
=
c_REVISION_ID
;
g_PROGRAM_ID
:
std_logic_vector
(
7
downto
0
)
:
=
c_PROGRAM_ID
;
g_MANUFACTURER_ID
:
std_logic_vector
(
23
downto
0
);
g_BOARD_ID
:
std_logic_vector
(
31
downto
0
);
g_REVISION_ID
:
std_logic_vector
(
31
downto
0
);
g_PROGRAM_ID
:
std_logic_vector
(
7
downto
0
)
:
=
c_PROGRAM_ID
;
g_ASCII_PTR
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_BEG_USER_CR
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_END_USER_CR
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_BEG_CRAM
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_END_CRAM
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_BEG_USER_CSR
:
std_logic_vector
(
23
downto
0
)
:
=
x"07ff33"
;
g_END_USER_CSR
:
std_logic_vector
(
23
downto
0
)
:
=
x"07ff5f"
;
g_BEG_SN
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_END_SN
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_F0_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"ff000000"
;
g_F0_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_0000ee00"
;
g_F0_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F1_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"fff80000"
;
g_F1_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"ee000000_00000000"
;
g_F1_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F2_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F2_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F2_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F3_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F3_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F3_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F4_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F4_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F4_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F5_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F5_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F5_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F6_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F6_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F6_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F7_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F7_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F7_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
);
g_nbr_decoders
:
natural
range
1
to
8
:
=
2
;
g_address_decoder
:
t_vme64x_decoder_arr
:
=
c_vme64x_decoders_default
);
port
(
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
rst_n_o
:
out
std_logic
;
VME_AS_n_i
:
in
std_logic
;
VME_RST_n_i
:
in
std_logic
;
VME_WRITE_n_i
:
in
std_logic
;
VME_AM_i
:
in
std_logic_vector
(
5
downto
0
);
VME_DS_n_i
:
in
std_logic_vector
(
1
downto
0
);
VME_GA_i
:
in
std_logic_vector
(
5
downto
0
);
VME_BERR_o
:
out
std_logic
;
VME_DTACK_n_o
:
out
std_logic
;
VME_RETRY_n_o
:
out
std_logic
;
VME_RETRY_OE_o
:
out
std_logic
;
VME_LWORD_n_b_i
:
in
std_logic
;
VME_LWORD_n_b_o
:
out
std_logic
;
VME_ADDR_b_i
:
in
std_logic_vector
(
31
downto
1
);
VME_ADDR_b_o
:
out
std_logic_vector
(
31
downto
1
);
VME_DATA_b_i
:
in
std_logic_vector
(
31
downto
0
);
VME_DATA_b_o
:
out
std_logic_vector
(
31
downto
0
);
VME_IRQ_n_o
:
out
std_logic_vector
(
7
downto
1
);
VME_IACKIN_n_i
:
in
std_logic
;
VME_IACK_n_i
:
in
std_logic
;
VME_IACKOUT_n_o
:
out
std_logic
;
VME_DTACK_OE_o
:
out
std_logic
;
VME_DATA_DIR_o
:
out
std_logic
;
VME_DATA_OE_N_o
:
out
std_logic
;
VME_ADDR_DIR_o
:
out
std_logic
;
VME_ADDR_OE_N_o
:
out
std_logic
;
vme_i
:
in
t_vme64x_in
;
vme_o
:
in
t_vme64x_out
;
master_o
:
out
t_wishbone_master_out
;
master_i
:
in
t_wishbone_master_in
;
wb_o
:
out
t_wishbone_master_out
;
wb_i
:
in
t_wishbone_master_in
;
irq_i
:
in
std_logic
;
irq_ack_o
:
out
std_logic
;
irq_level_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
irq_vector_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
endian_i
:
in
std_logic_vector
(
2
downto
0
)
:
=
(
others
=>
'0'
);
user_csr_addr_o
:
out
std_logic_vector
(
18
downto
2
);
user_csr_data_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
user_csr_data_o
:
out
std_logic_vector
(
7
downto
0
);
user_csr_we_o
:
out
std_logic
;
user_cr_addr_o
:
out
std_logic_vector
(
18
downto
2
);
user_cr_data_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
)
);
end
xvme64x_core
;
architecture
wrapper
of
xvme64x_core
is
...
...
@@ -155,111 +90,6 @@ architecture wrapper of xvme64x_core is
begin
-- wrapper
U_Wrapped_VME
:
vme64x_core
generic
map
(
g_CLOCK_PERIOD
=>
g_CLOCK_PERIOD
,
g_WB_DATA_WIDTH
=>
g_WB_DATA_WIDTH
,
g_WB_ADDR_WIDTH
=>
g_WB_ADDR_WIDTH
,
g_DECODE_AM
=>
g_DECODE_AM
,
g_USER_CSR_EXT
=>
g_USER_CSR_EXT
,
g_MANUFACTURER_ID
=>
g_MANUFACTURER_ID
,
g_BOARD_ID
=>
g_BOARD_ID
,
g_REVISION_ID
=>
g_REVISION_ID
,
g_PROGRAM_ID
=>
g_PROGRAM_ID
,
g_ASCII_PTR
=>
g_ASCII_PTR
,
g_BEG_USER_CR
=>
g_BEG_USER_CR
,
g_END_USER_CR
=>
g_END_USER_CR
,
g_BEG_CRAM
=>
g_BEG_CRAM
,
g_END_CRAM
=>
g_END_CRAM
,
g_BEG_USER_CSR
=>
g_BEG_USER_CSR
,
g_END_USER_CSR
=>
g_END_USER_CSR
,
g_BEG_SN
=>
g_BEG_SN
,
g_END_SN
=>
g_END_SN
,
g_F0_ADEM
=>
g_F0_ADEM
,
g_F0_AMCAP
=>
g_F0_AMCAP
,
g_F0_DAWPR
=>
g_F0_DAWPR
,
g_F1_ADEM
=>
g_F1_ADEM
,
g_F1_AMCAP
=>
g_F1_AMCAP
,
g_F1_DAWPR
=>
g_F1_DAWPR
,
g_F2_ADEM
=>
g_F2_ADEM
,
g_F2_AMCAP
=>
g_F2_AMCAP
,
g_F2_DAWPR
=>
g_F2_DAWPR
,
g_F3_ADEM
=>
g_F3_ADEM
,
g_F3_AMCAP
=>
g_F3_AMCAP
,
g_F3_DAWPR
=>
g_F3_DAWPR
,
g_F4_ADEM
=>
g_F4_ADEM
,
g_F4_AMCAP
=>
g_F4_AMCAP
,
g_F4_DAWPR
=>
g_F4_DAWPR
,
g_F5_ADEM
=>
g_F5_ADEM
,
g_F5_AMCAP
=>
g_F5_AMCAP
,
g_F5_DAWPR
=>
g_F5_DAWPR
,
g_F6_ADEM
=>
g_F6_ADEM
,
g_F6_AMCAP
=>
g_F6_AMCAP
,
g_F6_DAWPR
=>
g_F6_DAWPR
,
g_F7_ADEM
=>
g_F7_ADEM
,
g_F7_AMCAP
=>
g_F7_AMCAP
,
g_F7_DAWPR
=>
g_F7_DAWPR
)
port
map
(
clk_i
=>
clk_i
,
rst_n_i
=>
rst_n_i
,
rst_n_o
=>
rst_n_o
,
VME_AS_n_i
=>
VME_AS_n_i
,
VME_RST_n_i
=>
VME_RST_n_i
,
VME_WRITE_n_i
=>
VME_WRITE_n_i
,
VME_AM_i
=>
VME_AM_i
,
VME_DS_n_i
=>
VME_DS_n_i
,
VME_GA_i
=>
VME_GA_i
,
VME_BERR_o
=>
VME_BERR_o
,
VME_DTACK_n_o
=>
VME_DTACK_n_o
,
VME_RETRY_n_o
=>
VME_RETRY_n_o
,
VME_LWORD_n_i
=>
VME_LWORD_n_b_i
,
VME_LWORD_n_o
=>
VME_LWORD_n_b_o
,
VME_ADDR_i
=>
VME_ADDR_b_i
,
VME_ADDR_o
=>
VME_ADDR_b_o
,
VME_DATA_i
=>
VME_DATA_b_i
,
VME_DATA_o
=>
VME_DATA_b_o
,
VME_IRQ_o
=>
VME_IRQ_n_o
,
VME_IACKIN_n_i
=>
VME_IACKIN_n_i
,
VME_IACK_n_i
=>
VME_IACK_n_i
,
VME_IACKOUT_n_o
=>
VME_IACKOUT_n_o
,
VME_DTACK_OE_o
=>
VME_DTACK_OE_o
,
VME_DATA_DIR_o
=>
VME_DATA_DIR_o
,
VME_DATA_OE_N_o
=>
VME_DATA_OE_N_o
,
VME_ADDR_DIR_o
=>
VME_ADDR_DIR_o
,
VME_ADDR_OE_N_o
=>
VME_ADDR_OE_N_o
,
VME_RETRY_OE_o
=>
VME_RETRY_OE_o
,
DAT_i
=>
dat_in
,
DAT_o
=>
dat_out
,
ADR_o
=>
adr_out
,
CYC_o
=>
master_o
.
cyc
,
ERR_i
=>
master_i
.
err
,
SEL_o
=>
open
,
STB_o
=>
master_o
.
stb
,
ACK_i
=>
master_i
.
ack
,
WE_o
=>
master_o
.
we
,
STALL_i
=>
master_i
.
stall
,
irq_level_i
=>
irq_level_i
,
irq_vector_i
=>
irq_vector_i
,
user_csr_addr_o
=>
user_csr_addr_o
,
user_csr_data_i
=>
user_csr_data_i
,
user_csr_data_o
=>
user_csr_data_o
,
user_csr_we_o
=>
user_csr_we_o
,
user_cr_addr_o
=>
user_cr_addr_o
,
user_cr_data_i
=>
user_cr_data_i
,
irq_ack_o
=>
irq_ack_o
,
irq_i
=>
irq_i
);
master_o
.
dat
<=
dat_out
(
31
downto
0
);
master_o
.
sel
<=
(
others
=>
'1'
);
master_o
.
adr
<=
adr_out
(
29
downto
0
)
&
"00"
;
dat_in
<=
master_i
.
dat
;
assert
master_i
.
rty
=
'0'
report
"rty not supported"
;
assert
wb_i
.
rty
=
'0'
report
"rty not supported"
;
assert
endian_i
=
"000"
report
"endian_i not supported"
;
end
wrapper
;
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