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VME64x core
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VME64x core
Commits
1f90e1aa
Commit
1f90e1aa
authored
Feb 05, 2021
by
Tristan Gingold
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Adjust blt d16 cross boundary detection
parent
64092a3e
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1 changed file
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10 additions
and
5 deletions
+10
-5
vme_bus.vhd
hdl/rtl/vme_bus.vhd
+10
-5
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hdl/rtl/vme_bus.vhd
View file @
1f90e1aa
...
...
@@ -155,6 +155,9 @@ architecture rtl of vme_bus is
signal
addr_reg
:
std_logic_vector
(
31
downto
0
);
signal
lword_n_reg
:
std_logic
;
-- Next address (within the page) for a burst transfer
signal
n_addr_reg
:
std_logic_vector
(
10
downto
0
);
-- Load addr_reg from vme idff (for address phase1 and 2).
signal
load_addr_reg_phase1
:
std_logic
;
signal
load_addr_reg_phase2
:
std_logic
;
...
...
@@ -900,6 +903,8 @@ begin
end
if
;
end
process
;
n_addr_reg
<=
std_logic_vector
(
unsigned
(
addr_reg
(
10
downto
0
))
+
inc_reg
);
------------------------------------------------------------------------------
-- WB FSM
------------------------------------------------------------------------------
...
...
@@ -1086,12 +1091,12 @@ begin
-- BLT must not cross any 256 byte boundary.
-- VITA 1-1994 RULE 2.78
-- MBLT cycles MUST not cross any 2048 byte boundary.
addr_reg
(
10
downto
0
)
<=
std_logic_vector
(
unsigned
(
addr_reg
(
10
downto
0
))
+
inc_reg
);
addr_reg
(
10
downto
0
)
<=
n_addr_reg
;
if
addr_reg
(
7
downto
2
)
=
b"1111_11"
then
if
s_transferType
=
MBLT
and
addr_reg
(
10
downto
8
)
=
"111"
then
s_cross_boundary
<=
'1'
;
elsif
s_transferType
=
BLT
then
elsif
s_transferType
=
BLT
and
n_addr_reg
(
1
downto
0
)
=
"00"
then
-- For BLT, crossing depends on the data size.
s_cross_boundary
<=
'1'
;
end
if
;
end
if
;
...
...
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