hdl/boards/svec/testbench: fixed compile errors with new VME64x core interface

199c8e94 · Tomasz Wlostowski · b2fc3ce7 · 199c8e94 · 199c8e94 · 199c8e94
Commit 199c8e94 authored Aug 04, 2014 by Tomasz Wlostowski
6 changed files
--- a/hdl/boards/svec/rtl/Manifest.py
+++ b/hdl/boards/svec/rtl/Manifest.py
+files=["IRQ_Generator_Top.vhd",
+"IRQ_generator.vhd",
+"ram_8bits.vhd",
+"spram.vhd",
+"TOP_LEVEL.vhd",
+"WB_Bridge.vhd",
+"xwb_ram.vhd",
+"wishbone_pkg.vhd",
+"genram_pkg.vhd"];
\ No newline at end of file
--- a/hdl/boards/svec/rtl/TOP_LEVEL.vhd
+++ b/hdl/boards/svec/rtl/TOP_LEVEL.vhd
--- a/hdl/boards/svec/sim/testbench/Manifest.py
+++ b/hdl/boards/svec/sim/testbench/Manifest.py
+files =["VME64x_Package.vhd",
+"VME64x_SIM_Package.vhd",
+"VME64x_TB.vhd",
+  "../../../../vme64x-core/rtl/VME64xCore_Top.vhd",
+  "../../../../vme64x-core/rtl/vme64x_pack.vhd",
+  "../../../../vme64x-core/rtl/VME_Access_Decode.vhd",
+  "../../../../vme64x-core/rtl/VME_Am_Match.vhd",
+  "../../../../vme64x-core/rtl/VME_bus.vhd",
+  "../../../../vme64x-core/rtl/VME_CR_CSR_Space.vhd",
+  "../../../../vme64x-core/rtl/VME_CR_pack.vhd",
+  "../../../../vme64x-core/rtl/VME_CSR_pack.vhd",
+  "../../../../vme64x-core/rtl/VME_CRAM.vhd",
+  "../../../../vme64x-core/rtl/VME_Funct_Match.vhd",
+  "../../../../vme64x-core/rtl/VME_Init.vhd",
+  "../../../../vme64x-core/rtl/VME_IRQ_Controller.vhd",
+  "../../../../vme64x-core/rtl/VME_SharedComps.vhd",
+  "../../../../vme64x-core/rtl/VME_swapper.vhd",
+  "../../../../vme64x-core/rtl/VME_Wb_master.vhd"];
+
+
+modules = {"local":[ "../../rtl"]};
+
--- a/hdl/boards/svec/sim/testbench/VME64x_TB.vhd
+++ b/hdl/boards/svec/sim/testbench/VME64x_TB.vhd
@@ -13,7 +13,7 @@ use work.VME_CR_pack.all;
 use work.VME_CSR_pack.all; 
 use work.VME64xSim.all;
 use work.VME64x.all;
-use work.wishbone_pkg.all;
+--use work.wishbone_pkg.all;
 use std.textio.all; 
 use work.vme64x_pack.all; 

@@ -173,7 +173,9 @@ BEGIN
   test_VME64x : process
      
   begin
-
+     wait for 100ns;
+     Reset <= '0';
+     
      wait for 8800 ns;  -- wait until the initialization finish (wait more than 8705 ns)
                         -- Write in CSR:
      VME64xBus_Out.Vme64xIACK <= '1';

--- a/hdl/boards/svec/sim/testbench/run.do
+++ b/hdl/boards/svec/sim/testbench/run.do
+vlib work
+make
+vsim -t 1ps -L unisim -c work.vme64x_tb
+do wave1.do
+run 100us
\ No newline at end of file
--- a/hdl/boards/svec/sim/testbench/wave1.do
+++ b/hdl/boards/svec/sim/testbench/wave1.do