Skip to content

V
VME64x core
Commit 0c0cd06f authored by Tristan Gingold's avatar Tristan Gingold
Browse files
Options

Remove ADEM fake -1 value.

parent e2b58f6b
Show whitespace changes
Inline Side-by-side
Showing with 11 additions and 9 deletions
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @ 0c0cd06f
......@@ -354,8 +354,7 @@ architecture RTL of VME64xCore_Top is
-- CR/CSR parameter arrays
-- ADEM array has an extra index (-1) to simplify looping while checking the
-- EFM bit of the previous function.
constant c_ADEM : t_adem_array(-1 to 7) := (
x"0000_0000",
constant c_ADEM : t_adem_array(0 to 7) := (
g_F0_ADEM, g_F1_ADEM, g_F2_ADEM, g_F3_ADEM,
g_F4_ADEM, g_F5_ADEM, g_F6_ADEM, g_F7_ADEM
);
......@@ -422,7 +421,6 @@ begin
VME_RETRY_OE_o => VME_RETRY_OE_o,
VME_WRITE_n_i => s_VME_WRITE_n(2),
VME_DS_n_i => s_VME_DS_n(5 downto 4),
VME_DS_ant_n_i => s_VME_DS_n(3 downto 2),
VME_DTACK_n_o => s_VME_DTACK_VMEbus,
VME_DTACK_OE_o => s_VME_DTACK_OE_VMEbus,
VME_BERR_n_o => s_vme_berr_n,
......
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
View file @ 0c0cd06f
......@@ -122,7 +122,7 @@ entity VME_CR_CSR_Space is
g_END_USER_CSR : std_logic_vector(23 downto 0);
g_BEG_SN : std_logic_vector(23 downto 0);
g_END_SN : std_logic_vector(23 downto 0);
g_ADEM : t_adem_array(-1 to 7);
g_ADEM : t_adem_array(0 to 7);
g_AMCAP : t_amcap_array(0 to 7);
g_XAMCAP : t_xamcap_array(0 to 7);
g_DAWPR : t_dawpr_array(0 to 7)
......@@ -404,15 +404,18 @@ begin
for i in 0 to 7 loop
-- When FAF function or upper bits of previous FAF function, readback
-- and output ADER given at the FAF inputs.
if (g_ADEM(i-1)(c_ADEM_EFM) = '1' and g_ADEM(i-1)(c_ADEM_FAF) = '1') or
(g_ADEM(i-1)(c_ADEM_EFM) = '0' and g_ADEM( i )(c_ADEM_FAF) = '1')
if (i /= 0 and
g_ADEM(i-1)(c_ADEM_EFM) = '1' and g_ADEM(i-1)(c_ADEM_FAF) = '1') or
((i = 0 or g_ADEM(i-1)(c_ADEM_EFM) = '0') and
g_ADEM( i )(c_ADEM_FAF) = '1')
then
s_ader(i) <= faf_ader_i(i);
ader_o(i) <= faf_ader_i(i);
-- When upper bits of previous DFS function and DFSR enabled, readback
-- the ADEM value and output zero.
elsif g_ADEM(i-1)(c_ADEM_EFM) = '1' and g_ADEM(i-1)(c_ADEM_DFS) = '1' and
elsif i /= 0 and
g_ADEM(i-1)(c_ADEM_EFM) = '1' and g_ADEM(i-1)(c_ADEM_DFS) = '1' and
s_reg_ader(i-1)(c_ADER_DFSR) = '1'
then
s_ader(i) <= dfs_adem_i(i);
......@@ -420,7 +423,8 @@ begin
-- When a DFS function and DFSR enabled, readback the ADEM and output
-- zero.
elsif g_ADEM(i-1)(c_ADEM_EFM) = '0' and g_ADEM(i)(c_ADEM_DFS) = '1' and
elsif (i = 0 or g_ADEM(i-1)(c_ADEM_EFM) = '0') and
g_ADEM(i)(c_ADEM_DFS) = '1' and
s_reg_ader(i)(c_ADER_DFSR) = '1'
then
v_ader_b0 := (c_ADER_DFSR => s_reg_ader(i)(c_ADER_DFSR),
......
hdl/vme64x-core/rtl/VME_Funct_Match.vhd
View file @ 0c0cd06f
......@@ -38,7 +38,7 @@ use work.vme64x_pack.all;
entity VME_Funct_Match is
generic (
g_ADEM : t_adem_array(-1 to 7);
g_ADEM : t_adem_array(0 to 7);
g_AMCAP : t_amcap_array(0 to 7);
g_XAMCAP : t_xamcap_array(0 to 7)
);
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment